[deliverable/linux.git] / arch / arm / plat-s3c24xx / s3c2443-clock.c

/* linux/arch/arm/plat-s3c24xx/s3c2443-clock.c
 *
 * Copyright (c) 2007, 2010 Simtec Electronics
 *	Ben Dooks <ben@simtec.co.uk>
 *
 * S3C2443 Clock control suport - common code
 */

#include <linux/init.h>
#include <linux/clk.h>
#include <linux/io.h>

#include <mach/regs-s3c2443-clock.h>

#include <plat/s3c2443.h>
#include <plat/clock.h>
#include <plat/clock-clksrc.h>
#include <plat/cpu.h>

#include <plat/cpu-freq.h>


static int s3c2443_gate(void __iomem *reg, struct clk *clk, int enable)
{
	u32 ctrlbit = clk->ctrlbit;
	u32 con = __raw_readl(reg);

	if (enable)
		con |= ctrlbit;
	else
		con &= ~ctrlbit;

	__raw_writel(con, reg);
	return 0;
}

int s3c2443_clkcon_enable_h(struct clk *clk, int enable)
{
	return s3c2443_gate(S3C2443_HCLKCON, clk, enable);
}

int s3c2443_clkcon_enable_p(struct clk *clk, int enable)
{
	return s3c2443_gate(S3C2443_PCLKCON, clk, enable);
}

int s3c2443_clkcon_enable_s(struct clk *clk, int enable)
{
	return s3c2443_gate(S3C2443_SCLKCON, clk, enable);
}

/* mpllref is a direct descendant of clk_xtal by default, but it is not
 * elided as the EPLL can be either sourced by the XTAL or EXTCLK and as
 * such directly equating the two source clocks is impossible.
 */
struct clk clk_mpllref = {
	.name		= "mpllref",
	.parent		= &clk_xtal,
};

static struct clk *clk_epllref_sources[] = {
	[0] = &clk_mpllref,
	[1] = &clk_mpllref,
	[2] = &clk_xtal,
	[3] = &clk_ext,
};

struct clksrc_clk clk_epllref = {
	.clk	= {
		.name		= "epllref",
	},
	.sources = &(struct clksrc_sources) {
		.sources = clk_epllref_sources,
		.nr_sources = ARRAY_SIZE(clk_epllref_sources),
	},
	.reg_src = { .reg = S3C2443_CLKSRC, .size = 2, .shift = 7 },
};

/* esysclk
 *
 * this is sourced from either the EPLL or the EPLLref clock
*/

static struct clk *clk_sysclk_sources[] = {
	[0] = &clk_epllref.clk,
	[1] = &clk_epll,
};

struct clksrc_clk clk_esysclk = {
	.clk	= {
		.name		= "esysclk",
		.parent		= &clk_epll,
	},
	.sources = &(struct clksrc_sources) {
		.sources = clk_sysclk_sources,
		.nr_sources = ARRAY_SIZE(clk_sysclk_sources),
	},
	.reg_src = { .reg = S3C2443_CLKSRC, .size = 1, .shift = 6 },
};

static unsigned long s3c2443_getrate_mdivclk(struct clk *clk)
{
	unsigned long parent_rate = clk_get_rate(clk->parent);
	unsigned long div = __raw_readl(S3C2443_CLKDIV0);

	div  &= S3C2443_CLKDIV0_EXTDIV_MASK;
	div >>= (S3C2443_CLKDIV0_EXTDIV_SHIFT-1);	/* x2 */

	return parent_rate / (div + 1);
}

static struct clk clk_mdivclk = {
	.name		= "mdivclk",
	.parent		= &clk_mpllref,
	.ops		= &(struct clk_ops) {
		.get_rate	= s3c2443_getrate_mdivclk,
	},
};

static struct clk *clk_msysclk_sources[] = {
	[0] = &clk_mpllref,
	[1] = &clk_mpll,
	[2] = &clk_mdivclk,
	[3] = &clk_mpllref,
};

struct clksrc_clk clk_msysclk = {
	.clk	= {
		.name		= "msysclk",
		.parent		= &clk_xtal,
	},
	.sources = &(struct clksrc_sources) {
		.sources = clk_msysclk_sources,
		.nr_sources = ARRAY_SIZE(clk_msysclk_sources),
	},
	.reg_src = { .reg = S3C2443_CLKSRC, .size = 2, .shift = 3 },
};

/* prediv
 *
 * this divides the msysclk down to pass to h/p/etc.
 */

static unsigned long s3c2443_prediv_getrate(struct clk *clk)
{
	unsigned long rate = clk_get_rate(clk->parent);
	unsigned long clkdiv0 = __raw_readl(S3C2443_CLKDIV0);

	clkdiv0 &= S3C2443_CLKDIV0_PREDIV_MASK;
	clkdiv0 >>= S3C2443_CLKDIV0_PREDIV_SHIFT;

	return rate / (clkdiv0 + 1);
}

static struct clk clk_prediv = {
	.name		= "prediv",
	.parent		= &clk_msysclk.clk,
	.ops		= &(struct clk_ops) {
		.get_rate	= s3c2443_prediv_getrate,
	},
};

/* usbhost
 *
 * usb host bus-clock, usually 48MHz to provide USB bus clock timing
*/

static struct clksrc_clk clk_usb_bus_host = {
	.clk	= {
		.name		= "usb-bus-host-parent",
		.parent		= &clk_esysclk.clk,
		.ctrlbit	= S3C2443_SCLKCON_USBHOST,
		.enable		= s3c2443_clkcon_enable_s,
	},
	.reg_div = { .reg = S3C2443_CLKDIV1, .size = 2, .shift = 4 },
};

/* common clksrc clocks */

static struct clksrc_clk clksrc_clks[] = {
	{
		/* ART baud-rate clock sourced from esysclk via a divisor */
		.clk	= {
			.name		= "uartclk",
			.parent		= &clk_esysclk.clk,
		},
		.reg_div = { .reg = S3C2443_CLKDIV1, .size = 4, .shift = 8 },
	}, {
		/* camera interface bus-clock, divided down from esysclk */
		.clk	= {
			.name		= "camif-upll",	/* same as 2440 name */
			.parent		= &clk_esysclk.clk,
			.ctrlbit	= S3C2443_SCLKCON_CAMCLK,
			.enable		= s3c2443_clkcon_enable_s,
		},
		.reg_div = { .reg = S3C2443_CLKDIV1, .size = 4, .shift = 26 },
	}, {
		.clk	= {
			.name		= "display-if",
			.parent		= &clk_esysclk.clk,
			.ctrlbit	= S3C2443_SCLKCON_DISPCLK,
			.enable		= s3c2443_clkcon_enable_s,
		},
		.reg_div = { .reg = S3C2443_CLKDIV1, .size = 8, .shift = 16 },
	},
};

static struct clk clk_i2s_ext = {
	.name		= "i2s-ext",
};

/* i2s_eplldiv
 *
 * This clock is the output from the I2S divisor of ESYSCLK, and is separate
 * from the mux that comes after it (cannot merge into one single clock)
*/

static struct clksrc_clk clk_i2s_eplldiv = {
	.clk	= {
		.name		= "i2s-eplldiv",
		.parent		= &clk_esysclk.clk,
	},
	.reg_div = { .reg = S3C2443_CLKDIV1, .size = 4, .shift = 12, },
};

/* i2s-ref
 *
 * i2s bus reference clock, selectable from external, esysclk or epllref
 *
 * Note, this used to be two clocks, but was compressed into one.
*/

static struct clk *clk_i2s_srclist[] = {
	[0] = &clk_i2s_eplldiv.clk,
	[1] = &clk_i2s_ext,
	[2] = &clk_epllref.clk,
	[3] = &clk_epllref.clk,
};

static struct clksrc_clk clk_i2s = {
	.clk	= {
		.name		= "i2s-if",
		.ctrlbit	= S3C2443_SCLKCON_I2SCLK,
		.enable		= s3c2443_clkcon_enable_s,

	},
	.sources = &(struct clksrc_sources) {
		.sources = clk_i2s_srclist,
		.nr_sources = ARRAY_SIZE(clk_i2s_srclist),
	},
	.reg_src = { .reg = S3C2443_CLKSRC, .size = 2, .shift = 14 },
};

static struct clk init_clocks_off[] = {
	{
		.name		= "iis",
		.parent		= &clk_p,
		.enable		= s3c2443_clkcon_enable_p,
		.ctrlbit	= S3C2443_PCLKCON_IIS,
	}, {
		.name		= "hsspi",
		.parent		= &clk_p,
		.enable		= s3c2443_clkcon_enable_p,
		.ctrlbit	= S3C2443_PCLKCON_HSSPI,
	}, {
		.name		= "adc",
		.parent		= &clk_p,
		.enable		= s3c2443_clkcon_enable_p,
		.ctrlbit	= S3C2443_PCLKCON_ADC,
	}, {
		.name		= "i2c",
		.parent		= &clk_p,
		.enable		= s3c2443_clkcon_enable_p,
		.ctrlbit	= S3C2443_PCLKCON_IIC,
	}
};

static struct clk init_clocks[] = {
	{
		.name		= "dma",
		.parent		= &clk_h,
		.enable		= s3c2443_clkcon_enable_h,
		.ctrlbit	= S3C2443_HCLKCON_DMA0,
	}, {
		.name		= "dma",
		.parent		= &clk_h,
		.enable		= s3c2443_clkcon_enable_h,
		.ctrlbit	= S3C2443_HCLKCON_DMA1,
	}, {
		.name		= "dma",
		.parent		= &clk_h,
		.enable		= s3c2443_clkcon_enable_h,
		.ctrlbit	= S3C2443_HCLKCON_DMA2,
	}, {
		.name		= "dma",
		.parent		= &clk_h,
		.enable		= s3c2443_clkcon_enable_h,
		.ctrlbit	= S3C2443_HCLKCON_DMA3,
	}, {
		.name		= "dma",
		.parent		= &clk_h,
		.enable		= s3c2443_clkcon_enable_h,
		.ctrlbit	= S3C2443_HCLKCON_DMA4,
	}, {
		.name		= "dma",
		.parent		= &clk_h,
		.enable		= s3c2443_clkcon_enable_h,
		.ctrlbit	= S3C2443_HCLKCON_DMA5,
	}, {
		.name		= "hsmmc",
		.parent		= &clk_h,
		.enable		= s3c2443_clkcon_enable_h,
		.ctrlbit	= S3C2443_HCLKCON_HSMMC,
	}, {
		.name		= "gpio",
		.parent		= &clk_p,
		.enable		= s3c2443_clkcon_enable_p,
		.ctrlbit	= S3C2443_PCLKCON_GPIO,
	}, {
		.name		= "usb-host",
		.parent		= &clk_h,
		.enable		= s3c2443_clkcon_enable_h,
		.ctrlbit	= S3C2443_HCLKCON_USBH,
	}, {
		.name		= "usb-device",
		.parent		= &clk_h,
		.enable		= s3c2443_clkcon_enable_h,
		.ctrlbit	= S3C2443_HCLKCON_USBD,
	}, {
		.name		= "lcd",
		.parent		= &clk_h,
		.enable		= s3c2443_clkcon_enable_h,
		.ctrlbit	= S3C2443_HCLKCON_LCDC,

	}, {
		.name		= "timers",
		.parent		= &clk_p,
		.enable		= s3c2443_clkcon_enable_p,
		.ctrlbit	= S3C2443_PCLKCON_PWMT,
	}, {
		.name		= "cfc",
		.parent		= &clk_h,
		.enable		= s3c2443_clkcon_enable_h,
		.ctrlbit	= S3C2443_HCLKCON_CFC,
	}, {
		.name		= "ssmc",
		.parent		= &clk_h,
		.enable		= s3c2443_clkcon_enable_h,
		.ctrlbit	= S3C2443_HCLKCON_SSMC,
	}, {
		.name		= "uart",
		.devname	= "s3c2440-uart.0",
		.parent		= &clk_p,
		.enable		= s3c2443_clkcon_enable_p,
		.ctrlbit	= S3C2443_PCLKCON_UART0,
	}, {
		.name		= "uart",
		.devname	= "s3c2440-uart.1",
		.parent		= &clk_p,
		.enable		= s3c2443_clkcon_enable_p,
		.ctrlbit	= S3C2443_PCLKCON_UART1,
	}, {
		.name		= "uart",
		.devname	= "s3c2440-uart.2",
		.parent		= &clk_p,
		.enable		= s3c2443_clkcon_enable_p,
		.ctrlbit	= S3C2443_PCLKCON_UART2,
	}, {
		.name		= "uart",
		.devname	= "s3c2440-uart.3",
		.parent		= &clk_p,
		.enable		= s3c2443_clkcon_enable_p,
		.ctrlbit	= S3C2443_PCLKCON_UART3,
	}, {
		.name		= "rtc",
		.parent		= &clk_p,
		.enable		= s3c2443_clkcon_enable_p,
		.ctrlbit	= S3C2443_PCLKCON_RTC,
	}, {
		.name		= "watchdog",
		.parent		= &clk_p,
		.ctrlbit	= S3C2443_PCLKCON_WDT,
	}, {
		.name		= "ac97",
		.parent		= &clk_p,
		.ctrlbit	= S3C2443_PCLKCON_AC97,
	}, {
		.name		= "nand",
		.parent		= &clk_h,
	}, {
		.name		= "usb-bus-host",
		.parent		= &clk_usb_bus_host.clk,
	}
};

static inline unsigned long s3c2443_get_hdiv(unsigned long clkcon0)
{
	clkcon0 &= S3C2443_CLKDIV0_HCLKDIV_MASK;

	return clkcon0 + 1;
}

/* EPLLCON compatible enough to get on/off information */

void __init_or_cpufreq s3c2443_common_setup_clocks(pll_fn get_mpll,
						   fdiv_fn get_fdiv)
{
	unsigned long epllcon = __raw_readl(S3C2443_EPLLCON);
	unsigned long mpllcon = __raw_readl(S3C2443_MPLLCON);
	unsigned long clkdiv0 = __raw_readl(S3C2443_CLKDIV0);
	struct clk *xtal_clk;
	unsigned long xtal;
	unsigned long pll;
	unsigned long fclk;
	unsigned long hclk;
	unsigned long pclk;
	int ptr;

	xtal_clk = clk_get(NULL, "xtal");
	xtal = clk_get_rate(xtal_clk);
	clk_put(xtal_clk);

	pll = get_mpll(mpllcon, xtal);
	clk_msysclk.clk.rate = pll;

	fclk = pll / get_fdiv(clkdiv0);
	hclk = s3c2443_prediv_getrate(&clk_prediv);
	hclk /= s3c2443_get_hdiv(clkdiv0);
	pclk = hclk / ((clkdiv0 & S3C2443_CLKDIV0_HALF_PCLK) ? 2 : 1);

	s3c24xx_setup_clocks(fclk, hclk, pclk);

	printk("CPU: MPLL %s %ld.%03ld MHz, cpu %ld.%03ld MHz, mem %ld.%03ld MHz, pclk %ld.%03ld MHz\n",
	       (mpllcon & S3C2443_PLLCON_OFF) ? "off":"on",
	       print_mhz(pll), print_mhz(fclk),
	       print_mhz(hclk), print_mhz(pclk));

	for (ptr = 0; ptr < ARRAY_SIZE(clksrc_clks); ptr++)
		s3c_set_clksrc(&clksrc_clks[ptr], true);

	/* ensure usb bus clock is within correct rate of 48MHz */

	if (clk_get_rate(&clk_usb_bus_host.clk) != (48 * 1000 * 1000)) {
		printk(KERN_INFO "Warning: USB host bus not at 48MHz\n");
		clk_set_rate(&clk_usb_bus_host.clk, 48*1000*1000);
	}

	printk("CPU: EPLL %s %ld.%03ld MHz, usb-bus %ld.%03ld MHz\n",
	       (epllcon & S3C2443_PLLCON_OFF) ? "off":"on",
	       print_mhz(clk_get_rate(&clk_epll)),
	       print_mhz(clk_get_rate(&clk_usb_bus)));
}

static struct clk *clks[] __initdata = {
	&clk_prediv,
	&clk_mpllref,
	&clk_mdivclk,
	&clk_ext,
	&clk_epll,
	&clk_usb_bus,
};

static struct clksrc_clk *clksrcs[] __initdata = {
	&clk_i2s_eplldiv,
	&clk_i2s,
	&clk_usb_bus_host,
	&clk_epllref,
	&clk_esysclk,
	&clk_msysclk,
};

void __init s3c2443_common_init_clocks(int xtal, pll_fn get_mpll,
				       fdiv_fn get_fdiv)
{
	int ptr;

	/* s3c2443 parents h and p clocks from prediv */
	clk_h.parent = &clk_prediv;
	clk_p.parent = &clk_prediv;

	clk_usb_bus.parent = &clk_usb_bus_host.clk;
	clk_epll.parent = &clk_epllref.clk;

	s3c24xx_register_baseclocks(xtal);
	s3c24xx_register_clocks(clks, ARRAY_SIZE(clks));

	for (ptr = 0; ptr < ARRAY_SIZE(clksrcs); ptr++)
		s3c_register_clksrc(clksrcs[ptr], 1);

	s3c_register_clksrc(clksrc_clks, ARRAY_SIZE(clksrc_clks));
	s3c_register_clocks(init_clocks, ARRAY_SIZE(init_clocks));

	/* See s3c2443/etc notes on disabling clocks at init time */
	s3c_register_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
	s3c_disable_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));

	s3c2443_common_setup_clocks(get_mpll, get_fdiv);
}
Commit	Line	Data
af337f3e BD	1	/* linux/arch/arm/plat-s3c24xx/s3c2443-clock.c
	2	*
	3	* Copyright (c) 2007, 2010 Simtec Electronics
	4	* Ben Dooks <ben@simtec.co.uk>
	5	*
	6	* S3C2443 Clock control suport - common code
	7	*/
	8
	9	#include <linux/init.h>
	10	#include <linux/clk.h>
	11	#include <linux/io.h>
	12
	13	#include <mach/regs-s3c2443-clock.h>
	14
	15	#include <plat/s3c2443.h>
	16	#include <plat/clock.h>
	17	#include <plat/clock-clksrc.h>
	18	#include <plat/cpu.h>
	19
	20	#include <plat/cpu-freq.h>
	21
	22
	23	static int s3c2443_gate(void __iomem reg, struct clk clk, int enable)
	24	{
	25	u32 ctrlbit = clk->ctrlbit;
	26	u32 con = __raw_readl(reg);
	27
	28	if (enable)
	29	con \|= ctrlbit;
	30	else
	31	con &= ~ctrlbit;
	32
	33	__raw_writel(con, reg);
	34	return 0;
	35	}
	36
	37	int s3c2443_clkcon_enable_h(struct clk *clk, int enable)
	38	{
	39	return s3c2443_gate(S3C2443_HCLKCON, clk, enable);
	40	}
	41
	42	int s3c2443_clkcon_enable_p(struct clk *clk, int enable)
	43	{
	44	return s3c2443_gate(S3C2443_PCLKCON, clk, enable);
	45	}
	46
	47	int s3c2443_clkcon_enable_s(struct clk *clk, int enable)
	48	{
	49	return s3c2443_gate(S3C2443_SCLKCON, clk, enable);
	50	}
	51
	52	/* mpllref is a direct descendant of clk_xtal by default, but it is not
	53	* elided as the EPLL can be either sourced by the XTAL or EXTCLK and as
	54	* such directly equating the two source clocks is impossible.
	55	*/
	56	struct clk clk_mpllref = {
	57	.name = "mpllref",
	58	.parent = &clk_xtal,
af337f3e BD	59	};
	60
	61	static struct clk *clk_epllref_sources[] = {
	62	[0] = &clk_mpllref,
	63	[1] = &clk_mpllref,
	64	[2] = &clk_xtal,
	65	[3] = &clk_ext,
	66	};
	67
	68	struct clksrc_clk clk_epllref = {
	69	.clk = {
	70	.name = "epllref",
af337f3e BD	71	},
	72	.sources = &(struct clksrc_sources) {
	73	.sources = clk_epllref_sources,
	74	.nr_sources = ARRAY_SIZE(clk_epllref_sources),
	75	},
	76	.reg_src = { .reg = S3C2443_CLKSRC, .size = 2, .shift = 7 },
	77	};
	78
	79	/* esysclk
	80	*
	81	* this is sourced from either the EPLL or the EPLLref clock
	82	*/
	83
	84	static struct clk *clk_sysclk_sources[] = {
	85	[0] = &clk_epllref.clk,
	86	[1] = &clk_epll,
	87	};
	88
	89	struct clksrc_clk clk_esysclk = {
	90	.clk = {
	91	.name = "esysclk",
	92	.parent = &clk_epll,
af337f3e BD	93	},
	94	.sources = &(struct clksrc_sources) {
	95	.sources = clk_sysclk_sources,
	96	.nr_sources = ARRAY_SIZE(clk_sysclk_sources),
	97	},
	98	.reg_src = { .reg = S3C2443_CLKSRC, .size = 1, .shift = 6 },
	99	};
	100
	101	static unsigned long s3c2443_getrate_mdivclk(struct clk *clk)
	102	{
	103	unsigned long parent_rate = clk_get_rate(clk->parent);
	104	unsigned long div = __raw_readl(S3C2443_CLKDIV0);
	105
	106	div &= S3C2443_CLKDIV0_EXTDIV_MASK;
	107	div >>= (S3C2443_CLKDIV0_EXTDIV_SHIFT-1); /* x2 */
	108
	109	return parent_rate / (div + 1);
	110	}
	111
	112	static struct clk clk_mdivclk = {
	113	.name = "mdivclk",
	114	.parent = &clk_mpllref,
af337f3e BD	115	.ops = &(struct clk_ops) {
	116	.get_rate = s3c2443_getrate_mdivclk,
	117	},
	118	};
	119
	120	static struct clk *clk_msysclk_sources[] = {
	121	[0] = &clk_mpllref,
	122	[1] = &clk_mpll,
	123	[2] = &clk_mdivclk,
	124	[3] = &clk_mpllref,
	125	};
	126
	127	struct clksrc_clk clk_msysclk = {
	128	.clk = {
	129	.name = "msysclk",
	130	.parent = &clk_xtal,
af337f3e BD	131	},
	132	.sources = &(struct clksrc_sources) {
	133	.sources = clk_msysclk_sources,
	134	.nr_sources = ARRAY_SIZE(clk_msysclk_sources),
	135	},
	136	.reg_src = { .reg = S3C2443_CLKSRC, .size = 2, .shift = 3 },
	137	};
	138
	139	/* prediv
	140	*
	141	* this divides the msysclk down to pass to h/p/etc.
	142	*/
	143
	144	static unsigned long s3c2443_prediv_getrate(struct clk *clk)
	145	{
	146	unsigned long rate = clk_get_rate(clk->parent);
	147	unsigned long clkdiv0 = __raw_readl(S3C2443_CLKDIV0);
	148
	149	clkdiv0 &= S3C2443_CLKDIV0_PREDIV_MASK;
	150	clkdiv0 >>= S3C2443_CLKDIV0_PREDIV_SHIFT;
	151
	152	return rate / (clkdiv0 + 1);
	153	}
	154
	155	static struct clk clk_prediv = {
	156	.name = "prediv",
af337f3e BD	157	.parent = &clk_msysclk.clk,
	158	.ops = &(struct clk_ops) {
	159	.get_rate = s3c2443_prediv_getrate,
	160	},
	161	};
	162
	163	/* usbhost
	164	*
	165	* usb host bus-clock, usually 48MHz to provide USB bus clock timing
	166	*/
	167
	168	static struct clksrc_clk clk_usb_bus_host = {
	169	.clk = {
	170	.name = "usb-bus-host-parent",
af337f3e BD	171	.parent = &clk_esysclk.clk,
	172	.ctrlbit = S3C2443_SCLKCON_USBHOST,
	173	.enable = s3c2443_clkcon_enable_s,
	174	},
	175	.reg_div = { .reg = S3C2443_CLKDIV1, .size = 2, .shift = 4 },
	176	};
	177
	178	/* common clksrc clocks */
	179
	180	static struct clksrc_clk clksrc_clks[] = {
	181	{
	182	/* ART baud-rate clock sourced from esysclk via a divisor */
	183	.clk = {
	184	.name = "uartclk",
af337f3e BD	185	.parent = &clk_esysclk.clk,
	186	},
	187	.reg_div = { .reg = S3C2443_CLKDIV1, .size = 4, .shift = 8 },
	188	}, {
	189	/* camera interface bus-clock, divided down from esysclk */
	190	.clk = {
	191	.name = "camif-upll", /* same as 2440 name */
af337f3e BD	192	.parent = &clk_esysclk.clk,
	193	.ctrlbit = S3C2443_SCLKCON_CAMCLK,
	194	.enable = s3c2443_clkcon_enable_s,
	195	},
	196	.reg_div = { .reg = S3C2443_CLKDIV1, .size = 4, .shift = 26 },
	197	}, {
	198	.clk = {
	199	.name = "display-if",
af337f3e BD	200	.parent = &clk_esysclk.clk,
	201	.ctrlbit = S3C2443_SCLKCON_DISPCLK,
	202	.enable = s3c2443_clkcon_enable_s,
	203	},
	204	.reg_div = { .reg = S3C2443_CLKDIV1, .size = 8, .shift = 16 },
	205	},
	206	};
	207
e3b454f7 HS	208	static struct clk clk_i2s_ext = {
	209	.name = "i2s-ext",
	210	};
	211
	212	/* i2s_eplldiv
	213	*
	214	* This clock is the output from the I2S divisor of ESYSCLK, and is separate
	215	* from the mux that comes after it (cannot merge into one single clock)
	216	*/
	217
	218	static struct clksrc_clk clk_i2s_eplldiv = {
	219	.clk = {
	220	.name = "i2s-eplldiv",
	221	.parent = &clk_esysclk.clk,
	222	},
	223	.reg_div = { .reg = S3C2443_CLKDIV1, .size = 4, .shift = 12, },
	224	};
	225
	226	/* i2s-ref
	227	*
	228	* i2s bus reference clock, selectable from external, esysclk or epllref
	229	*
	230	* Note, this used to be two clocks, but was compressed into one.
	231	*/
	232
	233	static struct clk *clk_i2s_srclist[] = {
	234	[0] = &clk_i2s_eplldiv.clk,
	235	[1] = &clk_i2s_ext,
	236	[2] = &clk_epllref.clk,
	237	[3] = &clk_epllref.clk,
	238	};
	239
	240	static struct clksrc_clk clk_i2s = {
	241	.clk = {
	242	.name = "i2s-if",
	243	.ctrlbit = S3C2443_SCLKCON_I2SCLK,
	244	.enable = s3c2443_clkcon_enable_s,
	245
	246	},
	247	.sources = &(struct clksrc_sources) {
	248	.sources = clk_i2s_srclist,
	249	.nr_sources = ARRAY_SIZE(clk_i2s_srclist),
	250	},
	251	.reg_src = { .reg = S3C2443_CLKSRC, .size = 2, .shift = 14 },
	252	};
af337f3e BD	253
	254	static struct clk init_clocks_off[] = {
	255	{
e3b454f7 HS	256	.name = "iis",
	257	.parent = &clk_p,
	258	.enable = s3c2443_clkcon_enable_p,
	259	.ctrlbit = S3C2443_PCLKCON_IIS,
8b069b77 HS	260	}, {
	261	.name = "hsspi",
	262	.parent = &clk_p,
	263	.enable = s3c2443_clkcon_enable_p,
	264	.ctrlbit = S3C2443_PCLKCON_HSSPI,
e3b454f7	265	}, {
af337f3e	266	.name = "adc",
af337f3e BD	267	.parent = &clk_p,
	268	.enable = s3c2443_clkcon_enable_p,
	269	.ctrlbit = S3C2443_PCLKCON_ADC,
	270	}, {
	271	.name = "i2c",
af337f3e BD	272	.parent = &clk_p,
	273	.enable = s3c2443_clkcon_enable_p,
	274	.ctrlbit = S3C2443_PCLKCON_IIC,
	275	}
	276	};
	277
	278	static struct clk init_clocks[] = {
	279	{
	280	.name = "dma",
af337f3e BD	281	.parent = &clk_h,
	282	.enable = s3c2443_clkcon_enable_h,
	283	.ctrlbit = S3C2443_HCLKCON_DMA0,
	284	}, {
	285	.name = "dma",
af337f3e BD	286	.parent = &clk_h,
	287	.enable = s3c2443_clkcon_enable_h,
	288	.ctrlbit = S3C2443_HCLKCON_DMA1,
	289	}, {
	290	.name = "dma",
af337f3e BD	291	.parent = &clk_h,
	292	.enable = s3c2443_clkcon_enable_h,
	293	.ctrlbit = S3C2443_HCLKCON_DMA2,
	294	}, {
	295	.name = "dma",
af337f3e BD	296	.parent = &clk_h,
	297	.enable = s3c2443_clkcon_enable_h,
	298	.ctrlbit = S3C2443_HCLKCON_DMA3,
	299	}, {
	300	.name = "dma",
af337f3e BD	301	.parent = &clk_h,
	302	.enable = s3c2443_clkcon_enable_h,
	303	.ctrlbit = S3C2443_HCLKCON_DMA4,
	304	}, {
	305	.name = "dma",
af337f3e BD	306	.parent = &clk_h,
	307	.enable = s3c2443_clkcon_enable_h,
	308	.ctrlbit = S3C2443_HCLKCON_DMA5,
	309	}, {
	310	.name = "hsmmc",
af337f3e BD	311	.parent = &clk_h,
	312	.enable = s3c2443_clkcon_enable_h,
	313	.ctrlbit = S3C2443_HCLKCON_HSMMC,
	314	}, {
	315	.name = "gpio",
af337f3e BD	316	.parent = &clk_p,
	317	.enable = s3c2443_clkcon_enable_p,
	318	.ctrlbit = S3C2443_PCLKCON_GPIO,
	319	}, {
	320	.name = "usb-host",
af337f3e BD	321	.parent = &clk_h,
	322	.enable = s3c2443_clkcon_enable_h,
	323	.ctrlbit = S3C2443_HCLKCON_USBH,
	324	}, {
	325	.name = "usb-device",
af337f3e BD	326	.parent = &clk_h,
	327	.enable = s3c2443_clkcon_enable_h,
	328	.ctrlbit = S3C2443_HCLKCON_USBD,
	329	}, {
	330	.name = "lcd",
af337f3e BD	331	.parent = &clk_h,
	332	.enable = s3c2443_clkcon_enable_h,
	333	.ctrlbit = S3C2443_HCLKCON_LCDC,
	334
	335	}, {
	336	.name = "timers",
af337f3e BD	337	.parent = &clk_p,
	338	.enable = s3c2443_clkcon_enable_p,
	339	.ctrlbit = S3C2443_PCLKCON_PWMT,
	340	}, {
	341	.name = "cfc",
af337f3e BD	342	.parent = &clk_h,
	343	.enable = s3c2443_clkcon_enable_h,
	344	.ctrlbit = S3C2443_HCLKCON_CFC,
	345	}, {
	346	.name = "ssmc",
af337f3e BD	347	.parent = &clk_h,
	348	.enable = s3c2443_clkcon_enable_h,
	349	.ctrlbit = S3C2443_HCLKCON_SSMC,
	350	}, {
	351	.name = "uart",
e83626f2	352	.devname = "s3c2440-uart.0",
af337f3e BD	353	.parent = &clk_p,
	354	.enable = s3c2443_clkcon_enable_p,
	355	.ctrlbit = S3C2443_PCLKCON_UART0,
	356	}, {
	357	.name = "uart",
e83626f2	358	.devname = "s3c2440-uart.1",
af337f3e BD	359	.parent = &clk_p,
	360	.enable = s3c2443_clkcon_enable_p,
	361	.ctrlbit = S3C2443_PCLKCON_UART1,
	362	}, {
	363	.name = "uart",
e83626f2	364	.devname = "s3c2440-uart.2",
af337f3e BD	365	.parent = &clk_p,
	366	.enable = s3c2443_clkcon_enable_p,
	367	.ctrlbit = S3C2443_PCLKCON_UART2,
	368	}, {
	369	.name = "uart",
e83626f2	370	.devname = "s3c2440-uart.3",
af337f3e BD	371	.parent = &clk_p,
	372	.enable = s3c2443_clkcon_enable_p,
	373	.ctrlbit = S3C2443_PCLKCON_UART3,
	374	}, {
	375	.name = "rtc",
af337f3e BD	376	.parent = &clk_p,
	377	.enable = s3c2443_clkcon_enable_p,
	378	.ctrlbit = S3C2443_PCLKCON_RTC,
	379	}, {
	380	.name = "watchdog",
af337f3e BD	381	.parent = &clk_p,
	382	.ctrlbit = S3C2443_PCLKCON_WDT,
	383	}, {
	384	.name = "ac97",
af337f3e BD	385	.parent = &clk_p,
	386	.ctrlbit = S3C2443_PCLKCON_AC97,
	387	}, {
	388	.name = "nand",
af337f3e BD	389	.parent = &clk_h,
	390	}, {
	391	.name = "usb-bus-host",
af337f3e BD	392	.parent = &clk_usb_bus_host.clk,
	393	}
	394	};
	395
	396	static inline unsigned long s3c2443_get_hdiv(unsigned long clkcon0)
	397	{
	398	clkcon0 &= S3C2443_CLKDIV0_HCLKDIV_MASK;
	399
	400	return clkcon0 + 1;
	401	}
	402
	403	/* EPLLCON compatible enough to get on/off information */
	404
	405	void __init_or_cpufreq s3c2443_common_setup_clocks(pll_fn get_mpll,
	406	fdiv_fn get_fdiv)
	407	{
	408	unsigned long epllcon = __raw_readl(S3C2443_EPLLCON);
	409	unsigned long mpllcon = __raw_readl(S3C2443_MPLLCON);
	410	unsigned long clkdiv0 = __raw_readl(S3C2443_CLKDIV0);
	411	struct clk *xtal_clk;
	412	unsigned long xtal;
	413	unsigned long pll;
	414	unsigned long fclk;
	415	unsigned long hclk;
	416	unsigned long pclk;
	417	int ptr;
	418
	419	xtal_clk = clk_get(NULL, "xtal");
	420	xtal = clk_get_rate(xtal_clk);
	421	clk_put(xtal_clk);
	422
	423	pll = get_mpll(mpllcon, xtal);
	424	clk_msysclk.clk.rate = pll;
	425
	426	fclk = pll / get_fdiv(clkdiv0);
	427	hclk = s3c2443_prediv_getrate(&clk_prediv);
	428	hclk /= s3c2443_get_hdiv(clkdiv0);
	429	pclk = hclk / ((clkdiv0 & S3C2443_CLKDIV0_HALF_PCLK) ? 2 : 1);
	430
	431	s3c24xx_setup_clocks(fclk, hclk, pclk);
	432
	433	printk("CPU: MPLL %s %ld.%03ld MHz, cpu %ld.%03ld MHz, mem %ld.%03ld MHz, pclk %ld.%03ld MHz\n",
	434	(mpllcon & S3C2443_PLLCON_OFF) ? "off":"on",
	435	print_mhz(pll), print_mhz(fclk),
	436	print_mhz(hclk), print_mhz(pclk));
	437
	438	for (ptr = 0; ptr < ARRAY_SIZE(clksrc_clks); ptr++)
	439	s3c_set_clksrc(&clksrc_clks[ptr], true);
	440
	441	/* ensure usb bus clock is within correct rate of 48MHz */
	442
	443	if (clk_get_rate(&clk_usb_bus_host.clk) != (48 * 1000 * 1000)) {
	444	printk(KERN_INFO "Warning: USB host bus not at 48MHz\n");
	445	clk_set_rate(&clk_usb_bus_host.clk, 4810001000);
	446	}
	447
	448	printk("CPU: EPLL %s %ld.%03ld MHz, usb-bus %ld.%03ld MHz\n",
	449	(epllcon & S3C2443_PLLCON_OFF) ? "off":"on",
	450	print_mhz(clk_get_rate(&clk_epll)),
	451	print_mhz(clk_get_rate(&clk_usb_bus)));
	452	}
	453
	454	static struct clk *clks[] __initdata = {
	455	&clk_prediv,
456	&clk_mpllref,
457	&clk_mdivclk,
458	&clk_ext,
459	&clk_epll,
460	&clk_usb_bus,
461	};
462
463	static struct clksrc_clk *clksrcs[] __initdata = {
e3b454f7 HS	464	&clk_i2s_eplldiv,
e3b454f7 HS	465	&clk_i2s,
af337f3e BD	466	&clk_usb_bus_host,
	467	&clk_epllref,
	468	&clk_esysclk,
	469	&clk_msysclk,
	470	};
	471
	472	void __init s3c2443_common_init_clocks(int xtal, pll_fn get_mpll,
	473	fdiv_fn get_fdiv)
	474	{
	475	int ptr;
	476
	477	/* s3c2443 parents h and p clocks from prediv */
	478	clk_h.parent = &clk_prediv;
	479	clk_p.parent = &clk_prediv;
	480
	481	clk_usb_bus.parent = &clk_usb_bus_host.clk;
	482	clk_epll.parent = &clk_epllref.clk;
	483
	484	s3c24xx_register_baseclocks(xtal);
	485	s3c24xx_register_clocks(clks, ARRAY_SIZE(clks));
	486
	487	for (ptr = 0; ptr < ARRAY_SIZE(clksrcs); ptr++)
	488	s3c_register_clksrc(clksrcs[ptr], 1);
	489
	490	s3c_register_clksrc(clksrc_clks, ARRAY_SIZE(clksrc_clks));
	491	s3c_register_clocks(init_clocks, ARRAY_SIZE(init_clocks));
	492
	493	/* See s3c2443/etc notes on disabling clocks at init time */
	494	s3c_register_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
	495	s3c_disable_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
	496
	497	s3c2443_common_setup_clocks(get_mpll, get_fdiv);
	498	}