[deliverable/linux.git] / arch / arm / plat-s3c64xx / cpu.c

/* linux/arch/arm/plat-s3c64xx/cpu.c
 *
 * Copyright 2008 Openmoko, Inc.
 * Copyright 2008 Simtec Electronics
 *	Ben Dooks <ben@simtec.co.uk>
 *	http://armlinux.simtec.co.uk/
 *
 * S3C64XX CPU Support
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
*/

#include <linux/init.h>
#include <linux/module.h>
#include <linux/interrupt.h>
#include <linux/ioport.h>
#include <linux/sysdev.h>
#include <linux/serial_core.h>
#include <linux/platform_device.h>
#include <linux/io.h>

#include <mach/hardware.h>
#include <mach/map.h>

#include <asm/mach/arch.h>
#include <asm/mach/map.h>

#include <plat/regs-serial.h>

#include <plat/cpu.h>
#include <plat/devs.h>
#include <plat/clock.h>

#include <plat/s3c6400.h>
#include <plat/s3c6410.h>

/* table of supported CPUs */

static const char name_s3c6400[] = "S3C6400";
static const char name_s3c6410[] = "S3C6410";

static struct cpu_table cpu_ids[] __initdata = {
	{
		.idcode		= 0x36400000,
		.idmask		= 0xfffff000,
		.map_io		= s3c6400_map_io,
		.init_clocks	= s3c6400_init_clocks,
		.init_uarts	= s3c6400_init_uarts,
		.init		= s3c6400_init,
		.name		= name_s3c6400,
	}, {
		.idcode		= 0x36410100,
		.idmask		= 0xffffff00,
		.map_io		= s3c6410_map_io,
		.init_clocks	= s3c6410_init_clocks,
		.init_uarts	= s3c6410_init_uarts,
		.init		= s3c6410_init,
		.name		= name_s3c6410,
	},
};

/* minimal IO mapping */

/* see notes on uart map in arch/arm/mach-s3c6400/include/mach/debug-macro.S */
#define UART_OFFS (S3C_PA_UART & 0xfffff)

static struct map_desc s3c_iodesc[] __initdata = {
	{
		.virtual	= (unsigned long)S3C_VA_SYS,
		.pfn		= __phys_to_pfn(S3C64XX_PA_SYSCON),
		.length		= SZ_4K,
		.type		= MT_DEVICE,
	}, {
		.virtual	= (unsigned long)(S3C_VA_UART + UART_OFFS),
		.pfn		= __phys_to_pfn(S3C_PA_UART),
		.length		= SZ_4K,
		.type		= MT_DEVICE,
	}, {
		.virtual	= (unsigned long)S3C_VA_VIC0,
		.pfn		= __phys_to_pfn(S3C64XX_PA_VIC0),
		.length		= SZ_16K,
		.type		= MT_DEVICE,
	}, {
		.virtual	= (unsigned long)S3C_VA_VIC1,
		.pfn		= __phys_to_pfn(S3C64XX_PA_VIC1),
		.length		= SZ_16K,
		.type		= MT_DEVICE,
	}, {
		.virtual	= (unsigned long)S3C_VA_TIMER,
		.pfn		= __phys_to_pfn(S3C_PA_TIMER),
		.length		= SZ_16K,
		.type		= MT_DEVICE,
	}, {
		.virtual	= (unsigned long)S3C64XX_VA_GPIO,
		.pfn		= __phys_to_pfn(S3C64XX_PA_GPIO),
		.length		= SZ_4K,
		.type		= MT_DEVICE,
	}, {
		.virtual	= (unsigned long)S3C64XX_VA_MODEM,
		.pfn		= __phys_to_pfn(S3C64XX_PA_MODEM),
		.length		= SZ_4K,
		.type		= MT_DEVICE,
	}, {
		.virtual	= (unsigned long)S3C_VA_WATCHDOG,
		.pfn		= __phys_to_pfn(S3C64XX_PA_WATCHDOG),
		.length		= SZ_4K,
		.type		= MT_DEVICE,
	},
};


struct sysdev_class s3c64xx_sysclass = {
	.name	= "s3c64xx-core",
};

static struct sys_device s3c64xx_sysdev = {
	.cls	= &s3c64xx_sysclass,
};


/* read cpu identification code */

void __init s3c64xx_init_io(struct map_desc *mach_desc, int size)
{
	unsigned long idcode;

	/* initialise the io descriptors we need for initialisation */
	iotable_init(s3c_iodesc, ARRAY_SIZE(s3c_iodesc));
	iotable_init(mach_desc, size);

	idcode = __raw_readl(S3C_VA_SYS + 0x118);
	if (!idcode) {
		/* S3C6400 has the ID register in a different place,
		 * and needs a write before it can be read. */

		__raw_writel(0x0, S3C_VA_SYS + 0xA1C);
		idcode = __raw_readl(S3C_VA_SYS + 0xA1C);
	}

	s3c_init_cpu(idcode, cpu_ids, ARRAY_SIZE(cpu_ids));
}

static __init int s3c64xx_sysdev_init(void)
{
	sysdev_class_register(&s3c64xx_sysclass);
	return sysdev_register(&s3c64xx_sysdev);
}

core_initcall(s3c64xx_sysdev_init);
Commit	Line	Data
beda30f6 BD	1	/* linux/arch/arm/plat-s3c64xx/cpu.c
	2	*
	3	* Copyright 2008 Openmoko, Inc.
	4	* Copyright 2008 Simtec Electronics
	5	* Ben Dooks <ben@simtec.co.uk>
	6	* http://armlinux.simtec.co.uk/
	7	*
	8	* S3C64XX CPU Support
	9	*
	10	* This program is free software; you can redistribute it and/or modify
	11	* it under the terms of the GNU General Public License version 2 as
	12	* published by the Free Software Foundation.
	13	*/
	14
	15	#include <linux/init.h>
	16	#include <linux/module.h>
	17	#include <linux/interrupt.h>
	18	#include <linux/ioport.h>
1deb507d	19	#include <linux/sysdev.h>
beda30f6 BD	20	#include <linux/serial_core.h>
beda30f6 BD	21	#include <linux/platform_device.h>
beda30f6 BD	22	#include <linux/io.h>
	23
	24	#include <mach/hardware.h>
	25	#include <mach/map.h>
	26
	27	#include <asm/mach/arch.h>
	28	#include <asm/mach/map.h>
	29
	30	#include <plat/regs-serial.h>
	31
	32	#include <plat/cpu.h>
	33	#include <plat/devs.h>
	34	#include <plat/clock.h>
	35
	36	#include <plat/s3c6400.h>
	37	#include <plat/s3c6410.h>
	38
	39	/* table of supported CPUs */
	40
	41	static const char name_s3c6400[] = "S3C6400";
	42	static const char name_s3c6410[] = "S3C6410";
	43
	44	static struct cpu_table cpu_ids[] __initdata = {
	45	{
	46	.idcode = 0x36400000,
	47	.idmask = 0xfffff000,
	48	.map_io = s3c6400_map_io,
	49	.init_clocks = s3c6400_init_clocks,
	50	.init_uarts = s3c6400_init_uarts,
	51	.init = s3c6400_init,
	52	.name = name_s3c6400,
	53	}, {
	54	.idcode = 0x36410100,
	55	.idmask = 0xffffff00,
	56	.map_io = s3c6410_map_io,
	57	.init_clocks = s3c6410_init_clocks,
	58	.init_uarts = s3c6410_init_uarts,
	59	.init = s3c6410_init,
	60	.name = name_s3c6410,
	61	},
	62	};
	63
	64	/* minimal IO mapping */
	65
	66	/* see notes on uart map in arch/arm/mach-s3c6400/include/mach/debug-macro.S */
	67	#define UART_OFFS (S3C_PA_UART & 0xfffff)
	68
	69	static struct map_desc s3c_iodesc[] __initdata = {
	70	{
f945ee13	71	.virtual = (unsigned long)S3C_VA_SYS,
beda30f6 BD	72	.pfn = __phys_to_pfn(S3C64XX_PA_SYSCON),
	73	.length = SZ_4K,
	74	.type = MT_DEVICE,
	75	}, {
	76	.virtual = (unsigned long)(S3C_VA_UART + UART_OFFS),
	77	.pfn = __phys_to_pfn(S3C_PA_UART),
	78	.length = SZ_4K,
	79	.type = MT_DEVICE,
	80	}, {
f945ee13	81	.virtual = (unsigned long)S3C_VA_VIC0,
beda30f6 BD	82	.pfn = __phys_to_pfn(S3C64XX_PA_VIC0),
	83	.length = SZ_16K,
	84	.type = MT_DEVICE,
	85	}, {
f945ee13	86	.virtual = (unsigned long)S3C_VA_VIC1,
beda30f6 BD	87	.pfn = __phys_to_pfn(S3C64XX_PA_VIC1),
	88	.length = SZ_16K,
	89	.type = MT_DEVICE,
f982dc53	90	}, {
f945ee13	91	.virtual = (unsigned long)S3C_VA_TIMER,
f982dc53 BD	92	.pfn = __phys_to_pfn(S3C_PA_TIMER),
	93	.length = SZ_16K,
	94	.type = MT_DEVICE,
94df868b	95	}, {
f945ee13	96	.virtual = (unsigned long)S3C64XX_VA_GPIO,
94df868b BD	97	.pfn = __phys_to_pfn(S3C64XX_PA_GPIO),
	98	.length = SZ_4K,
	99	.type = MT_DEVICE,
5b3d515f BD	100	}, {
	101	.virtual = (unsigned long)S3C64XX_VA_MODEM,
	102	.pfn = __phys_to_pfn(S3C64XX_PA_MODEM),
	103	.length = SZ_4K,
	104	.type = MT_DEVICE,
543899f6 BD	105	}, {
	106	.virtual = (unsigned long)S3C_VA_WATCHDOG,
	107	.pfn = __phys_to_pfn(S3C64XX_PA_WATCHDOG),
	108	.length = SZ_4K,
	109	.type = MT_DEVICE,
beda30f6 BD	110	},
	111	};
	112
1deb507d BD	113
	114	struct sysdev_class s3c64xx_sysclass = {
	115	.name = "s3c64xx-core",
	116	};
	117
	118	static struct sys_device s3c64xx_sysdev = {
	119	.cls = &s3c64xx_sysclass,
	120	};
	121
	122
beda30f6 BD	123	/* read cpu identification code */
beda30f6 BD	124
beda30f6 BD	125	void __init s3c64xx_init_io(struct map_desc *mach_desc, int size)
	126	{
	127	unsigned long idcode;
	128
	129	/* initialise the io descriptors we need for initialisation */
	130	iotable_init(s3c_iodesc, ARRAY_SIZE(s3c_iodesc));
	131	iotable_init(mach_desc, size);
	132
	133	idcode = __raw_readl(S3C_VA_SYS + 0x118);
e074f980 BD	134	if (!idcode) {
	135	/* S3C6400 has the ID register in a different place,
	136	* and needs a write before it can be read. */
	137
	138	__raw_writel(0x0, S3C_VA_SYS + 0xA1C);
	139	idcode = __raw_readl(S3C_VA_SYS + 0xA1C);
	140	}
	141
beda30f6 BD	142	s3c_init_cpu(idcode, cpu_ids, ARRAY_SIZE(cpu_ids));
beda30f6 BD	143	}
1deb507d BD	144
	145	static __init int s3c64xx_sysdev_init(void)
	146	{
	147	sysdev_class_register(&s3c64xx_sysclass);
	148	return sysdev_register(&s3c64xx_sysdev);
	149	}
	150
	151	core_initcall(s3c64xx_sysdev_init);