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1a0e8a52 KK |
1 | /* linux/arch/arm/plat-s5p/clock.c |
2 | * | |
3 | * Copyright 2009 Samsung Electronics Co., Ltd. | |
4 | * http://www.samsung.com/ | |
5 | * | |
6 | * S5P - Common clock support | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or modify | |
9 | * it under the terms of the GNU General Public License version 2 as | |
10 | * published by the Free Software Foundation. | |
11 | */ | |
12 | ||
13 | #include <linux/init.h> | |
14 | #include <linux/module.h> | |
15 | #include <linux/kernel.h> | |
16 | #include <linux/list.h> | |
17 | #include <linux/errno.h> | |
18 | #include <linux/err.h> | |
19 | #include <linux/clk.h> | |
20 | #include <linux/sysdev.h> | |
21 | #include <linux/io.h> | |
22 | #include <asm/div64.h> | |
23 | ||
24 | #include <plat/clock.h> | |
25 | #include <plat/clock-clksrc.h> | |
26 | #include <plat/s5p-clock.h> | |
27 | ||
28 | /* fin_apll, fin_mpll and fin_epll are all the same clock, which we call | |
29 | * clk_ext_xtal_mux. | |
30 | */ | |
31 | struct clk clk_ext_xtal_mux = { | |
32 | .name = "ext_xtal", | |
33 | .id = -1, | |
34 | }; | |
35 | ||
0c1945d3 KK |
36 | static struct clk s5p_clk_27m = { |
37 | .name = "clk_27m", | |
38 | .id = -1, | |
39 | .rate = 27000000, | |
40 | }; | |
41 | ||
1a0e8a52 KK |
42 | /* 48MHz USB Phy clock output */ |
43 | struct clk clk_48m = { | |
44 | .name = "clk_48m", | |
45 | .id = -1, | |
46 | .rate = 48000000, | |
47 | }; | |
48 | ||
49 | /* APLL clock output | |
50 | * No need .ctrlbit, this is always on | |
51 | */ | |
52 | struct clk clk_fout_apll = { | |
53 | .name = "fout_apll", | |
54 | .id = -1, | |
55 | }; | |
56 | ||
57 | /* MPLL clock output | |
58 | * No need .ctrlbit, this is always on | |
59 | */ | |
60 | struct clk clk_fout_mpll = { | |
61 | .name = "fout_mpll", | |
62 | .id = -1, | |
63 | }; | |
64 | ||
65 | /* EPLL clock output */ | |
66 | struct clk clk_fout_epll = { | |
67 | .name = "fout_epll", | |
68 | .id = -1, | |
69 | .ctrlbit = (1 << 31), | |
70 | }; | |
71 | ||
72 | /* ARM clock */ | |
73 | struct clk clk_arm = { | |
74 | .name = "armclk", | |
75 | .id = -1, | |
76 | .rate = 0, | |
77 | .ctrlbit = 0, | |
78 | }; | |
79 | ||
80 | /* Possible clock sources for APLL Mux */ | |
81 | static struct clk *clk_src_apll_list[] = { | |
82 | [0] = &clk_fin_apll, | |
83 | [1] = &clk_fout_apll, | |
84 | }; | |
85 | ||
86 | struct clksrc_sources clk_src_apll = { | |
87 | .sources = clk_src_apll_list, | |
88 | .nr_sources = ARRAY_SIZE(clk_src_apll_list), | |
89 | }; | |
90 | ||
91 | /* Possible clock sources for MPLL Mux */ | |
92 | static struct clk *clk_src_mpll_list[] = { | |
93 | [0] = &clk_fin_mpll, | |
94 | [1] = &clk_fout_mpll, | |
95 | }; | |
96 | ||
97 | struct clksrc_sources clk_src_mpll = { | |
98 | .sources = clk_src_mpll_list, | |
99 | .nr_sources = ARRAY_SIZE(clk_src_mpll_list), | |
100 | }; | |
101 | ||
102 | /* Possible clock sources for EPLL Mux */ | |
103 | static struct clk *clk_src_epll_list[] = { | |
104 | [0] = &clk_fin_epll, | |
105 | [1] = &clk_fout_epll, | |
106 | }; | |
107 | ||
108 | struct clksrc_sources clk_src_epll = { | |
109 | .sources = clk_src_epll_list, | |
110 | .nr_sources = ARRAY_SIZE(clk_src_epll_list), | |
111 | }; | |
112 | ||
0c1945d3 KK |
113 | struct clk clk_vpll = { |
114 | .name = "vpll", | |
115 | .id = -1, | |
116 | }; | |
117 | ||
1a0e8a52 KK |
118 | int s5p_gatectrl(void __iomem *reg, struct clk *clk, int enable) |
119 | { | |
120 | unsigned int ctrlbit = clk->ctrlbit; | |
121 | u32 con; | |
122 | ||
123 | con = __raw_readl(reg); | |
124 | con = enable ? (con | ctrlbit) : (con & ~ctrlbit); | |
125 | __raw_writel(con, reg); | |
126 | return 0; | |
127 | } | |
128 | ||
129 | static struct clk *s5p_clks[] __initdata = { | |
130 | &clk_ext_xtal_mux, | |
131 | &clk_48m, | |
0c1945d3 | 132 | &s5p_clk_27m, |
1a0e8a52 KK |
133 | &clk_fout_apll, |
134 | &clk_fout_mpll, | |
135 | &clk_fout_epll, | |
136 | &clk_arm, | |
0c1945d3 | 137 | &clk_vpll, |
1a0e8a52 KK |
138 | }; |
139 | ||
140 | void __init s5p_register_clocks(unsigned long xtal_freq) | |
141 | { | |
142 | int ret; | |
143 | ||
144 | clk_ext_xtal_mux.rate = xtal_freq; | |
145 | ||
146 | ret = s3c24xx_register_clocks(s5p_clks, ARRAY_SIZE(s5p_clks)); | |
147 | if (ret > 0) | |
148 | printk(KERN_ERR "Failed to register s5p clocks\n"); | |
149 | } |