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1a0e8a52 KK |
1 | /* linux/arch/arm/plat-s5p/clock.c |
2 | * | |
3 | * Copyright 2009 Samsung Electronics Co., Ltd. | |
4 | * http://www.samsung.com/ | |
5 | * | |
6 | * S5P - Common clock support | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or modify | |
9 | * it under the terms of the GNU General Public License version 2 as | |
10 | * published by the Free Software Foundation. | |
11 | */ | |
12 | ||
13 | #include <linux/init.h> | |
14 | #include <linux/module.h> | |
15 | #include <linux/kernel.h> | |
16 | #include <linux/list.h> | |
17 | #include <linux/errno.h> | |
18 | #include <linux/err.h> | |
19 | #include <linux/clk.h> | |
edbaa603 | 20 | #include <linux/device.h> |
1a0e8a52 KK |
21 | #include <linux/io.h> |
22 | #include <asm/div64.h> | |
23 | ||
d4b34c6c SY |
24 | #include <mach/regs-clock.h> |
25 | ||
1a0e8a52 KK |
26 | #include <plat/clock.h> |
27 | #include <plat/clock-clksrc.h> | |
28 | #include <plat/s5p-clock.h> | |
29 | ||
30 | /* fin_apll, fin_mpll and fin_epll are all the same clock, which we call | |
31 | * clk_ext_xtal_mux. | |
32 | */ | |
33 | struct clk clk_ext_xtal_mux = { | |
34 | .name = "ext_xtal", | |
35 | .id = -1, | |
36 | }; | |
37 | ||
f001d5b2 TA |
38 | struct clk clk_xusbxti = { |
39 | .name = "xusbxti", | |
40 | .id = -1, | |
41 | }; | |
42 | ||
a443a637 | 43 | struct clk s5p_clk_27m = { |
0c1945d3 KK |
44 | .name = "clk_27m", |
45 | .id = -1, | |
46 | .rate = 27000000, | |
47 | }; | |
48 | ||
1a0e8a52 KK |
49 | /* 48MHz USB Phy clock output */ |
50 | struct clk clk_48m = { | |
51 | .name = "clk_48m", | |
52 | .id = -1, | |
53 | .rate = 48000000, | |
54 | }; | |
55 | ||
56 | /* APLL clock output | |
57 | * No need .ctrlbit, this is always on | |
58 | */ | |
59 | struct clk clk_fout_apll = { | |
60 | .name = "fout_apll", | |
61 | .id = -1, | |
62 | }; | |
63 | ||
87b3c6ef KK |
64 | /* BPLL clock output */ |
65 | ||
66 | struct clk clk_fout_bpll = { | |
67 | .name = "fout_bpll", | |
68 | .id = -1, | |
69 | }; | |
70 | ||
71 | /* CPLL clock output */ | |
72 | ||
73 | struct clk clk_fout_cpll = { | |
74 | .name = "fout_cpll", | |
75 | .id = -1, | |
76 | }; | |
77 | ||
1a0e8a52 KK |
78 | /* MPLL clock output |
79 | * No need .ctrlbit, this is always on | |
80 | */ | |
81 | struct clk clk_fout_mpll = { | |
82 | .name = "fout_mpll", | |
83 | .id = -1, | |
84 | }; | |
85 | ||
86 | /* EPLL clock output */ | |
87 | struct clk clk_fout_epll = { | |
88 | .name = "fout_epll", | |
89 | .id = -1, | |
90 | .ctrlbit = (1 << 31), | |
91 | }; | |
92 | ||
3109e550 KK |
93 | /* DPLL clock output */ |
94 | struct clk clk_fout_dpll = { | |
95 | .name = "fout_dpll", | |
96 | .id = -1, | |
97 | .ctrlbit = (1 << 31), | |
98 | }; | |
99 | ||
f445dbd5 TA |
100 | /* VPLL clock output */ |
101 | struct clk clk_fout_vpll = { | |
102 | .name = "fout_vpll", | |
103 | .id = -1, | |
104 | .ctrlbit = (1 << 31), | |
105 | }; | |
106 | ||
1a0e8a52 KK |
107 | /* Possible clock sources for APLL Mux */ |
108 | static struct clk *clk_src_apll_list[] = { | |
109 | [0] = &clk_fin_apll, | |
110 | [1] = &clk_fout_apll, | |
111 | }; | |
112 | ||
113 | struct clksrc_sources clk_src_apll = { | |
114 | .sources = clk_src_apll_list, | |
115 | .nr_sources = ARRAY_SIZE(clk_src_apll_list), | |
116 | }; | |
117 | ||
87b3c6ef KK |
118 | /* Possible clock sources for BPLL Mux */ |
119 | static struct clk *clk_src_bpll_list[] = { | |
120 | [0] = &clk_fin_bpll, | |
121 | [1] = &clk_fout_bpll, | |
122 | }; | |
123 | ||
124 | struct clksrc_sources clk_src_bpll = { | |
125 | .sources = clk_src_bpll_list, | |
126 | .nr_sources = ARRAY_SIZE(clk_src_bpll_list), | |
127 | }; | |
128 | ||
129 | /* Possible clock sources for CPLL Mux */ | |
130 | static struct clk *clk_src_cpll_list[] = { | |
131 | [0] = &clk_fin_cpll, | |
132 | [1] = &clk_fout_cpll, | |
133 | }; | |
134 | ||
135 | struct clksrc_sources clk_src_cpll = { | |
136 | .sources = clk_src_cpll_list, | |
137 | .nr_sources = ARRAY_SIZE(clk_src_cpll_list), | |
138 | }; | |
139 | ||
1a0e8a52 KK |
140 | /* Possible clock sources for MPLL Mux */ |
141 | static struct clk *clk_src_mpll_list[] = { | |
142 | [0] = &clk_fin_mpll, | |
143 | [1] = &clk_fout_mpll, | |
144 | }; | |
145 | ||
146 | struct clksrc_sources clk_src_mpll = { | |
147 | .sources = clk_src_mpll_list, | |
148 | .nr_sources = ARRAY_SIZE(clk_src_mpll_list), | |
149 | }; | |
150 | ||
151 | /* Possible clock sources for EPLL Mux */ | |
152 | static struct clk *clk_src_epll_list[] = { | |
153 | [0] = &clk_fin_epll, | |
154 | [1] = &clk_fout_epll, | |
155 | }; | |
156 | ||
157 | struct clksrc_sources clk_src_epll = { | |
158 | .sources = clk_src_epll_list, | |
159 | .nr_sources = ARRAY_SIZE(clk_src_epll_list), | |
160 | }; | |
161 | ||
3109e550 KK |
162 | /* Possible clock sources for DPLL Mux */ |
163 | static struct clk *clk_src_dpll_list[] = { | |
164 | [0] = &clk_fin_dpll, | |
165 | [1] = &clk_fout_dpll, | |
166 | }; | |
167 | ||
168 | struct clksrc_sources clk_src_dpll = { | |
169 | .sources = clk_src_dpll_list, | |
170 | .nr_sources = ARRAY_SIZE(clk_src_dpll_list), | |
171 | }; | |
172 | ||
0c1945d3 KK |
173 | struct clk clk_vpll = { |
174 | .name = "vpll", | |
175 | .id = -1, | |
176 | }; | |
177 | ||
1a0e8a52 KK |
178 | int s5p_gatectrl(void __iomem *reg, struct clk *clk, int enable) |
179 | { | |
180 | unsigned int ctrlbit = clk->ctrlbit; | |
181 | u32 con; | |
182 | ||
183 | con = __raw_readl(reg); | |
184 | con = enable ? (con | ctrlbit) : (con & ~ctrlbit); | |
185 | __raw_writel(con, reg); | |
186 | return 0; | |
187 | } | |
188 | ||
d4b34c6c SY |
189 | int s5p_epll_enable(struct clk *clk, int enable) |
190 | { | |
191 | unsigned int ctrlbit = clk->ctrlbit; | |
192 | unsigned int epll_con = __raw_readl(S5P_EPLL_CON) & ~ctrlbit; | |
193 | ||
194 | if (enable) | |
195 | __raw_writel(epll_con | ctrlbit, S5P_EPLL_CON); | |
196 | else | |
197 | __raw_writel(epll_con, S5P_EPLL_CON); | |
198 | ||
199 | return 0; | |
200 | } | |
201 | ||
202 | unsigned long s5p_epll_get_rate(struct clk *clk) | |
203 | { | |
204 | return clk->rate; | |
205 | } | |
206 | ||
65f5eaa2 NKC |
207 | int s5p_spdif_set_rate(struct clk *clk, unsigned long rate) |
208 | { | |
209 | struct clk *pclk; | |
210 | int ret; | |
211 | ||
212 | pclk = clk_get_parent(clk); | |
213 | if (IS_ERR(pclk)) | |
214 | return -EINVAL; | |
215 | ||
216 | ret = pclk->ops->set_rate(pclk, rate); | |
217 | clk_put(pclk); | |
218 | ||
219 | return ret; | |
220 | } | |
221 | ||
222 | unsigned long s5p_spdif_get_rate(struct clk *clk) | |
223 | { | |
224 | struct clk *pclk; | |
225 | int rate; | |
226 | ||
227 | pclk = clk_get_parent(clk); | |
228 | if (IS_ERR(pclk)) | |
229 | return -EINVAL; | |
230 | ||
5d747c6f | 231 | rate = pclk->ops->get_rate(pclk); |
65f5eaa2 NKC |
232 | clk_put(pclk); |
233 | ||
234 | return rate; | |
235 | } | |
236 | ||
237 | struct clk_ops s5p_sclk_spdif_ops = { | |
238 | .set_rate = s5p_spdif_set_rate, | |
239 | .get_rate = s5p_spdif_get_rate, | |
240 | }; | |
241 | ||
1a0e8a52 KK |
242 | static struct clk *s5p_clks[] __initdata = { |
243 | &clk_ext_xtal_mux, | |
244 | &clk_48m, | |
0c1945d3 | 245 | &s5p_clk_27m, |
1a0e8a52 KK |
246 | &clk_fout_apll, |
247 | &clk_fout_mpll, | |
248 | &clk_fout_epll, | |
3109e550 | 249 | &clk_fout_dpll, |
f445dbd5 | 250 | &clk_fout_vpll, |
0c1945d3 | 251 | &clk_vpll, |
8fb9d2d7 | 252 | &clk_xusbxti, |
1a0e8a52 KK |
253 | }; |
254 | ||
255 | void __init s5p_register_clocks(unsigned long xtal_freq) | |
256 | { | |
257 | int ret; | |
258 | ||
259 | clk_ext_xtal_mux.rate = xtal_freq; | |
260 | ||
261 | ret = s3c24xx_register_clocks(s5p_clks, ARRAY_SIZE(s5p_clks)); | |
262 | if (ret > 0) | |
263 | printk(KERN_ERR "Failed to register s5p clocks\n"); | |
264 | } |