ARM: S5PV210: Add audio clocks as sysclk
[deliverable/linux.git] / arch / arm / plat-s5p / clock.c
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1/* linux/arch/arm/plat-s5p/clock.c
2 *
3 * Copyright 2009 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com/
5 *
6 * S5P - Common clock support
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11*/
12
13#include <linux/init.h>
14#include <linux/module.h>
15#include <linux/kernel.h>
16#include <linux/list.h>
17#include <linux/errno.h>
18#include <linux/err.h>
19#include <linux/clk.h>
20#include <linux/sysdev.h>
21#include <linux/io.h>
22#include <asm/div64.h>
23
24#include <plat/clock.h>
25#include <plat/clock-clksrc.h>
26#include <plat/s5p-clock.h>
27
28/* fin_apll, fin_mpll and fin_epll are all the same clock, which we call
29 * clk_ext_xtal_mux.
30*/
31struct clk clk_ext_xtal_mux = {
32 .name = "ext_xtal",
33 .id = -1,
34};
35
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36struct clk clk_xusbxti = {
37 .name = "xusbxti",
38 .id = -1,
39};
40
a443a637 41struct clk s5p_clk_27m = {
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42 .name = "clk_27m",
43 .id = -1,
44 .rate = 27000000,
45};
46
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47/* 48MHz USB Phy clock output */
48struct clk clk_48m = {
49 .name = "clk_48m",
50 .id = -1,
51 .rate = 48000000,
52};
53
54/* APLL clock output
55 * No need .ctrlbit, this is always on
56*/
57struct clk clk_fout_apll = {
58 .name = "fout_apll",
59 .id = -1,
60};
61
62/* MPLL clock output
63 * No need .ctrlbit, this is always on
64*/
65struct clk clk_fout_mpll = {
66 .name = "fout_mpll",
67 .id = -1,
68};
69
70/* EPLL clock output */
71struct clk clk_fout_epll = {
72 .name = "fout_epll",
73 .id = -1,
74 .ctrlbit = (1 << 31),
75};
76
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77/* DPLL clock output */
78struct clk clk_fout_dpll = {
79 .name = "fout_dpll",
80 .id = -1,
81 .ctrlbit = (1 << 31),
82};
83
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84/* VPLL clock output */
85struct clk clk_fout_vpll = {
86 .name = "fout_vpll",
87 .id = -1,
88 .ctrlbit = (1 << 31),
89};
90
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91/* Possible clock sources for APLL Mux */
92static struct clk *clk_src_apll_list[] = {
93 [0] = &clk_fin_apll,
94 [1] = &clk_fout_apll,
95};
96
97struct clksrc_sources clk_src_apll = {
98 .sources = clk_src_apll_list,
99 .nr_sources = ARRAY_SIZE(clk_src_apll_list),
100};
101
102/* Possible clock sources for MPLL Mux */
103static struct clk *clk_src_mpll_list[] = {
104 [0] = &clk_fin_mpll,
105 [1] = &clk_fout_mpll,
106};
107
108struct clksrc_sources clk_src_mpll = {
109 .sources = clk_src_mpll_list,
110 .nr_sources = ARRAY_SIZE(clk_src_mpll_list),
111};
112
113/* Possible clock sources for EPLL Mux */
114static struct clk *clk_src_epll_list[] = {
115 [0] = &clk_fin_epll,
116 [1] = &clk_fout_epll,
117};
118
119struct clksrc_sources clk_src_epll = {
120 .sources = clk_src_epll_list,
121 .nr_sources = ARRAY_SIZE(clk_src_epll_list),
122};
123
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124/* Possible clock sources for DPLL Mux */
125static struct clk *clk_src_dpll_list[] = {
126 [0] = &clk_fin_dpll,
127 [1] = &clk_fout_dpll,
128};
129
130struct clksrc_sources clk_src_dpll = {
131 .sources = clk_src_dpll_list,
132 .nr_sources = ARRAY_SIZE(clk_src_dpll_list),
133};
134
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135struct clk clk_vpll = {
136 .name = "vpll",
137 .id = -1,
138};
139
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140int s5p_gatectrl(void __iomem *reg, struct clk *clk, int enable)
141{
142 unsigned int ctrlbit = clk->ctrlbit;
143 u32 con;
144
145 con = __raw_readl(reg);
146 con = enable ? (con | ctrlbit) : (con & ~ctrlbit);
147 __raw_writel(con, reg);
148 return 0;
149}
150
151static struct clk *s5p_clks[] __initdata = {
152 &clk_ext_xtal_mux,
153 &clk_48m,
0c1945d3 154 &s5p_clk_27m,
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155 &clk_fout_apll,
156 &clk_fout_mpll,
157 &clk_fout_epll,
3109e550 158 &clk_fout_dpll,
f445dbd5 159 &clk_fout_vpll,
0c1945d3 160 &clk_vpll,
8fb9d2d7 161 &clk_xusbxti,
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162};
163
164void __init s5p_register_clocks(unsigned long xtal_freq)
165{
166 int ret;
167
168 clk_ext_xtal_mux.rate = xtal_freq;
169
170 ret = s3c24xx_register_clocks(s5p_clks, ARRAY_SIZE(s5p_clks));
171 if (ret > 0)
172 printk(KERN_ERR "Failed to register s5p clocks\n");
173}
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