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b7db51be KK |
1 | /* linux/arch/arm/plat-s5p/include/plat/irqs.h |
2 | * | |
3 | * Copyright (c) 2009 Samsung Electronics Co., Ltd. | |
4 | * http://www.samsung.com/ | |
5 | * | |
6 | * S5P Common IRQ support | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or modify | |
9 | * it under the terms of the GNU General Public License version 2 as | |
10 | * published by the Free Software Foundation. | |
11 | */ | |
12 | ||
13 | #ifndef __ASM_PLAT_S5P_IRQS_H | |
14 | #define __ASM_PLAT_S5P_IRQS_H __FILE__ | |
15 | ||
16 | /* we keep the first set of CPU IRQs out of the range of | |
17 | * the ISA space, so that the PC104 has them to itself | |
18 | * and we don't end up having to do horrible things to the | |
19 | * standard ISA drivers.... | |
20 | * | |
21 | * note, since we're using the VICs, our start must be a | |
22 | * mulitple of 32 to allow the common code to work | |
23 | */ | |
24 | ||
25 | #define S5P_IRQ_OFFSET (32) | |
26 | ||
27 | #define S5P_IRQ(x) ((x) + S5P_IRQ_OFFSET) | |
28 | ||
29 | #define S5P_VIC0_BASE S5P_IRQ(0) | |
30 | #define S5P_VIC1_BASE S5P_IRQ(32) | |
d9f18a98 | 31 | #define S5P_VIC2_BASE S5P_IRQ(64) |
2c798557 | 32 | #define S5P_VIC3_BASE S5P_IRQ(96) |
b7db51be | 33 | |
81317960 KK |
34 | #define VIC_BASE(x) (S5P_VIC0_BASE + ((x)*32)) |
35 | ||
b7db51be KK |
36 | #define IRQ_VIC0_BASE S5P_VIC0_BASE |
37 | #define IRQ_VIC1_BASE S5P_VIC1_BASE | |
d9f18a98 | 38 | #define IRQ_VIC2_BASE S5P_VIC2_BASE |
b7db51be KK |
39 | |
40 | /* UART interrupts, each UART has 4 intterupts per channel so | |
41 | * use the space between the ISA and S3C main interrupts. Note, these | |
42 | * are not in the same order as the S3C24XX series! */ | |
43 | ||
44 | #define IRQ_S5P_UART_BASE0 (16) | |
45 | #define IRQ_S5P_UART_BASE1 (20) | |
46 | #define IRQ_S5P_UART_BASE2 (24) | |
47 | #define IRQ_S5P_UART_BASE3 (28) | |
48 | ||
49 | #define UART_IRQ_RXD (0) | |
50 | #define UART_IRQ_ERR (1) | |
51 | #define UART_IRQ_TXD (2) | |
52 | ||
53 | #define IRQ_S5P_UART_RX0 (IRQ_S5P_UART_BASE0 + UART_IRQ_RXD) | |
54 | #define IRQ_S5P_UART_TX0 (IRQ_S5P_UART_BASE0 + UART_IRQ_TXD) | |
55 | #define IRQ_S5P_UART_ERR0 (IRQ_S5P_UART_BASE0 + UART_IRQ_ERR) | |
56 | ||
57 | #define IRQ_S5P_UART_RX1 (IRQ_S5P_UART_BASE1 + UART_IRQ_RXD) | |
58 | #define IRQ_S5P_UART_TX1 (IRQ_S5P_UART_BASE1 + UART_IRQ_TXD) | |
59 | #define IRQ_S5P_UART_ERR1 (IRQ_S5P_UART_BASE1 + UART_IRQ_ERR) | |
60 | ||
61 | #define IRQ_S5P_UART_RX2 (IRQ_S5P_UART_BASE2 + UART_IRQ_RXD) | |
62 | #define IRQ_S5P_UART_TX2 (IRQ_S5P_UART_BASE2 + UART_IRQ_TXD) | |
63 | #define IRQ_S5P_UART_ERR2 (IRQ_S5P_UART_BASE2 + UART_IRQ_ERR) | |
64 | ||
65 | #define IRQ_S5P_UART_RX3 (IRQ_S5P_UART_BASE3 + UART_IRQ_RXD) | |
66 | #define IRQ_S5P_UART_TX3 (IRQ_S5P_UART_BASE3 + UART_IRQ_TXD) | |
67 | #define IRQ_S5P_UART_ERR3 (IRQ_S5P_UART_BASE3 + UART_IRQ_ERR) | |
68 | ||
69 | /* S3C compatibilty defines */ | |
70 | #define IRQ_S3CUART_RX0 IRQ_S5P_UART_RX0 | |
71 | #define IRQ_S3CUART_RX1 IRQ_S5P_UART_RX1 | |
72 | #define IRQ_S3CUART_RX2 IRQ_S5P_UART_RX2 | |
73 | #define IRQ_S3CUART_RX3 IRQ_S5P_UART_RX3 | |
74 | ||
75 | /* VIC based IRQs */ | |
76 | ||
77 | #define S5P_IRQ_VIC0(x) (S5P_VIC0_BASE + (x)) | |
78 | #define S5P_IRQ_VIC1(x) (S5P_VIC1_BASE + (x)) | |
d9f18a98 | 79 | #define S5P_IRQ_VIC2(x) (S5P_VIC2_BASE + (x)) |
2c798557 | 80 | #define S5P_IRQ_VIC3(x) (S5P_VIC3_BASE + (x)) |
b7db51be | 81 | |
1131379b | 82 | #define S5P_TIMER_IRQ(x) (11 + (x)) |
b7db51be KK |
83 | |
84 | #define IRQ_TIMER0 S5P_TIMER_IRQ(0) | |
85 | #define IRQ_TIMER1 S5P_TIMER_IRQ(1) | |
86 | #define IRQ_TIMER2 S5P_TIMER_IRQ(2) | |
87 | #define IRQ_TIMER3 S5P_TIMER_IRQ(3) | |
88 | #define IRQ_TIMER4 S5P_TIMER_IRQ(4) | |
89 | ||
5fae4058 PB |
90 | #define IRQ_EINT(x) ((x) < 16 ? ((x) + S5P_EINT_BASE1) \ |
91 | : ((x) - 16 + S5P_EINT_BASE2)) | |
92 | ||
93 | #define EINT_OFFSET(irq) ((irq) < S5P_EINT_BASE2 ? \ | |
94 | ((irq) - S5P_EINT_BASE1) : \ | |
95 | ((irq) + 16 - S5P_EINT_BASE2)) | |
96 | ||
170a4617 MS |
97 | /* Typically only a few gpio chips require gpio interrupt support. |
98 | To avoid memory waste irq descriptors are allocated only for | |
99 | S5P_GPIOINT_GROUP_COUNT chips, each with total number of | |
100 | S5P_GPIOINT_GROUP_SIZE pins/irqs. Each GPIOINT group can be assiged | |
101 | to any gpio chip with the s5p_register_gpio_interrupt() function */ | |
102 | #define S5P_GPIOINT_GROUP_COUNT 4 | |
103 | #define S5P_GPIOINT_GROUP_SIZE 8 | |
104 | #define S5P_GPIOINT_COUNT (S5P_GPIOINT_GROUP_COUNT * S5P_GPIOINT_GROUP_SIZE) | |
105 | ||
b7db51be | 106 | #endif /* __ASM_PLAT_S5P_IRQS_H */ |