Commit | Line | Data |
---|---|---|
b7db51be KK |
1 | /* linux/arch/arm/plat-s5p/include/plat/irqs.h |
2 | * | |
3 | * Copyright (c) 2009 Samsung Electronics Co., Ltd. | |
4 | * http://www.samsung.com/ | |
5 | * | |
6 | * S5P Common IRQ support | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or modify | |
9 | * it under the terms of the GNU General Public License version 2 as | |
10 | * published by the Free Software Foundation. | |
11 | */ | |
12 | ||
13 | #ifndef __ASM_PLAT_S5P_IRQS_H | |
14 | #define __ASM_PLAT_S5P_IRQS_H __FILE__ | |
15 | ||
16 | /* we keep the first set of CPU IRQs out of the range of | |
17 | * the ISA space, so that the PC104 has them to itself | |
18 | * and we don't end up having to do horrible things to the | |
19 | * standard ISA drivers.... | |
20 | * | |
21 | * note, since we're using the VICs, our start must be a | |
22 | * mulitple of 32 to allow the common code to work | |
23 | */ | |
24 | ||
25 | #define S5P_IRQ_OFFSET (32) | |
26 | ||
27 | #define S5P_IRQ(x) ((x) + S5P_IRQ_OFFSET) | |
28 | ||
29 | #define S5P_VIC0_BASE S5P_IRQ(0) | |
30 | #define S5P_VIC1_BASE S5P_IRQ(32) | |
31 | ||
32 | #define IRQ_VIC0_BASE S5P_VIC0_BASE | |
33 | #define IRQ_VIC1_BASE S5P_VIC1_BASE | |
34 | ||
35 | /* UART interrupts, each UART has 4 intterupts per channel so | |
36 | * use the space between the ISA and S3C main interrupts. Note, these | |
37 | * are not in the same order as the S3C24XX series! */ | |
38 | ||
39 | #define IRQ_S5P_UART_BASE0 (16) | |
40 | #define IRQ_S5P_UART_BASE1 (20) | |
41 | #define IRQ_S5P_UART_BASE2 (24) | |
42 | #define IRQ_S5P_UART_BASE3 (28) | |
43 | ||
44 | #define UART_IRQ_RXD (0) | |
45 | #define UART_IRQ_ERR (1) | |
46 | #define UART_IRQ_TXD (2) | |
47 | ||
48 | #define IRQ_S5P_UART_RX0 (IRQ_S5P_UART_BASE0 + UART_IRQ_RXD) | |
49 | #define IRQ_S5P_UART_TX0 (IRQ_S5P_UART_BASE0 + UART_IRQ_TXD) | |
50 | #define IRQ_S5P_UART_ERR0 (IRQ_S5P_UART_BASE0 + UART_IRQ_ERR) | |
51 | ||
52 | #define IRQ_S5P_UART_RX1 (IRQ_S5P_UART_BASE1 + UART_IRQ_RXD) | |
53 | #define IRQ_S5P_UART_TX1 (IRQ_S5P_UART_BASE1 + UART_IRQ_TXD) | |
54 | #define IRQ_S5P_UART_ERR1 (IRQ_S5P_UART_BASE1 + UART_IRQ_ERR) | |
55 | ||
56 | #define IRQ_S5P_UART_RX2 (IRQ_S5P_UART_BASE2 + UART_IRQ_RXD) | |
57 | #define IRQ_S5P_UART_TX2 (IRQ_S5P_UART_BASE2 + UART_IRQ_TXD) | |
58 | #define IRQ_S5P_UART_ERR2 (IRQ_S5P_UART_BASE2 + UART_IRQ_ERR) | |
59 | ||
60 | #define IRQ_S5P_UART_RX3 (IRQ_S5P_UART_BASE3 + UART_IRQ_RXD) | |
61 | #define IRQ_S5P_UART_TX3 (IRQ_S5P_UART_BASE3 + UART_IRQ_TXD) | |
62 | #define IRQ_S5P_UART_ERR3 (IRQ_S5P_UART_BASE3 + UART_IRQ_ERR) | |
63 | ||
64 | /* S3C compatibilty defines */ | |
65 | #define IRQ_S3CUART_RX0 IRQ_S5P_UART_RX0 | |
66 | #define IRQ_S3CUART_RX1 IRQ_S5P_UART_RX1 | |
67 | #define IRQ_S3CUART_RX2 IRQ_S5P_UART_RX2 | |
68 | #define IRQ_S3CUART_RX3 IRQ_S5P_UART_RX3 | |
69 | ||
70 | /* VIC based IRQs */ | |
71 | ||
72 | #define S5P_IRQ_VIC0(x) (S5P_VIC0_BASE + (x)) | |
73 | #define S5P_IRQ_VIC1(x) (S5P_VIC1_BASE + (x)) | |
74 | ||
75 | #define S5P_TIMER_IRQ(x) S5P_IRQ(64 + (x)) | |
76 | ||
77 | #define IRQ_TIMER0 S5P_TIMER_IRQ(0) | |
78 | #define IRQ_TIMER1 S5P_TIMER_IRQ(1) | |
79 | #define IRQ_TIMER2 S5P_TIMER_IRQ(2) | |
80 | #define IRQ_TIMER3 S5P_TIMER_IRQ(3) | |
81 | #define IRQ_TIMER4 S5P_TIMER_IRQ(4) | |
82 | ||
83 | #endif /* __ASM_PLAT_S5P_IRQS_H */ |