[deliverable/linux.git] / arch / arm / plat-s5p / irq-eint.c

/* linux/arch/arm/plat-s5p/irq-eint.c
 *
 * Copyright (c) 2010 Samsung Electronics Co., Ltd.
 *		http://www.samsung.com
 *
 * S5P - IRQ EINT support
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
*/

#include <linux/kernel.h>
#include <linux/interrupt.h>
#include <linux/irq.h>
#include <linux/io.h>
#include <linux/device.h>
#include <linux/gpio.h>

#include <asm/hardware/vic.h>

#include <plat/regs-irqtype.h>

#include <mach/map.h>
#include <plat/cpu.h>
#include <plat/pm.h>

#include <plat/gpio-cfg.h>
#include <mach/regs-gpio.h>

static inline void s5p_irq_eint_mask(struct irq_data *data)
{
	u32 mask;

	mask = __raw_readl(S5P_EINT_MASK(EINT_REG_NR(data->irq)));
	mask |= eint_irq_to_bit(data->irq);
	__raw_writel(mask, S5P_EINT_MASK(EINT_REG_NR(data->irq)));
}

static void s5p_irq_eint_unmask(struct irq_data *data)
{
	u32 mask;

	mask = __raw_readl(S5P_EINT_MASK(EINT_REG_NR(data->irq)));
	mask &= ~(eint_irq_to_bit(data->irq));
	__raw_writel(mask, S5P_EINT_MASK(EINT_REG_NR(data->irq)));
}

static inline void s5p_irq_eint_ack(struct irq_data *data)
{
	__raw_writel(eint_irq_to_bit(data->irq),
		     S5P_EINT_PEND(EINT_REG_NR(data->irq)));
}

static void s5p_irq_eint_maskack(struct irq_data *data)
{
	/* compiler should in-line these */
	s5p_irq_eint_mask(data);
	s5p_irq_eint_ack(data);
}

static int s5p_irq_eint_set_type(struct irq_data *data, unsigned int type)
{
	int offs = EINT_OFFSET(data->irq);
	int shift;
	u32 ctrl, mask;
	u32 newvalue = 0;

	switch (type) {
	case IRQ_TYPE_EDGE_RISING:
		newvalue = S5P_IRQ_TYPE_EDGE_RISING;
		break;

	case IRQ_TYPE_EDGE_FALLING:
		newvalue = S5P_IRQ_TYPE_EDGE_FALLING;
		break;

	case IRQ_TYPE_EDGE_BOTH:
		newvalue = S5P_IRQ_TYPE_EDGE_BOTH;
		break;

	case IRQ_TYPE_LEVEL_LOW:
		newvalue = S5P_IRQ_TYPE_LEVEL_LOW;
		break;

	case IRQ_TYPE_LEVEL_HIGH:
		newvalue = S5P_IRQ_TYPE_LEVEL_HIGH;
		break;

	default:
		printk(KERN_ERR "No such irq type %d", type);
		return -EINVAL;
	}

	shift = (offs & 0x7) * 4;
	mask = 0x7 << shift;

	ctrl = __raw_readl(S5P_EINT_CON(EINT_REG_NR(data->irq)));
	ctrl &= ~mask;
	ctrl |= newvalue << shift;
	__raw_writel(ctrl, S5P_EINT_CON(EINT_REG_NR(data->irq)));

	if ((0 <= offs) && (offs < 8))
		s3c_gpio_cfgpin(EINT_GPIO_0(offs & 0x7), EINT_MODE);

	else if ((8 <= offs) && (offs < 16))
		s3c_gpio_cfgpin(EINT_GPIO_1(offs & 0x7), EINT_MODE);

	else if ((16 <= offs) && (offs < 24))
		s3c_gpio_cfgpin(EINT_GPIO_2(offs & 0x7), EINT_MODE);

	else if ((24 <= offs) && (offs < 32))
		s3c_gpio_cfgpin(EINT_GPIO_3(offs & 0x7), EINT_MODE);

	else
		printk(KERN_ERR "No such irq number %d", offs);

	return 0;
}

static struct irq_chip s5p_irq_eint = {
	.name		= "s5p-eint",
	.irq_mask	= s5p_irq_eint_mask,
	.irq_unmask	= s5p_irq_eint_unmask,
	.irq_mask_ack	= s5p_irq_eint_maskack,
	.irq_ack	= s5p_irq_eint_ack,
	.irq_set_type	= s5p_irq_eint_set_type,
#ifdef CONFIG_PM
	.irq_set_wake	= s3c_irqext_wake,
#endif
};

/* s5p_irq_demux_eint
 *
 * This function demuxes the IRQ from the group0 external interrupts,
 * from EINTs 16 to 31. It is designed to be inlined into the specific
 * handler s5p_irq_demux_eintX_Y.
 *
 * Each EINT pend/mask registers handle eight of them.
 */
static inline void s5p_irq_demux_eint(unsigned int start)
{
	u32 status = __raw_readl(S5P_EINT_PEND(EINT_REG_NR(start)));
	u32 mask = __raw_readl(S5P_EINT_MASK(EINT_REG_NR(start)));
	unsigned int irq;

	status &= ~mask;
	status &= 0xff;

	while (status) {
		irq = fls(status) - 1;
		generic_handle_irq(irq + start);
		status &= ~(1 << irq);
	}
}

static void s5p_irq_demux_eint16_31(unsigned int irq, struct irq_desc *desc)
{
	s5p_irq_demux_eint(IRQ_EINT(16));
	s5p_irq_demux_eint(IRQ_EINT(24));
}

static inline void s5p_irq_vic_eint_mask(struct irq_data *data)
{
	void __iomem *base = irq_data_get_irq_chip_data(data);

	s5p_irq_eint_mask(data);
	writel(1 << EINT_OFFSET(data->irq), base + VIC_INT_ENABLE_CLEAR);
}

static void s5p_irq_vic_eint_unmask(struct irq_data *data)
{
	void __iomem *base = irq_data_get_irq_chip_data(data);

	s5p_irq_eint_unmask(data);
	writel(1 << EINT_OFFSET(data->irq), base + VIC_INT_ENABLE);
}

static inline void s5p_irq_vic_eint_ack(struct irq_data *data)
{
	__raw_writel(eint_irq_to_bit(data->irq),
		     S5P_EINT_PEND(EINT_REG_NR(data->irq)));
}

static void s5p_irq_vic_eint_maskack(struct irq_data *data)
{
	s5p_irq_vic_eint_mask(data);
	s5p_irq_vic_eint_ack(data);
}

static struct irq_chip s5p_irq_vic_eint = {
	.name		= "s5p_vic_eint",
	.irq_mask	= s5p_irq_vic_eint_mask,
	.irq_unmask	= s5p_irq_vic_eint_unmask,
	.irq_mask_ack	= s5p_irq_vic_eint_maskack,
	.irq_ack	= s5p_irq_vic_eint_ack,
	.irq_set_type	= s5p_irq_eint_set_type,
#ifdef CONFIG_PM
	.irq_set_wake	= s3c_irqext_wake,
#endif
};

static int __init s5p_init_irq_eint(void)
{
	int irq;

	for (irq = IRQ_EINT(0); irq <= IRQ_EINT(15); irq++)
		irq_set_chip(irq, &s5p_irq_vic_eint);

	for (irq = IRQ_EINT(16); irq <= IRQ_EINT(31); irq++) {
		irq_set_chip_and_handler(irq, &s5p_irq_eint, handle_level_irq);
		set_irq_flags(irq, IRQF_VALID);
	}

	irq_set_chained_handler(IRQ_EINT16_31, s5p_irq_demux_eint16_31);
	return 0;
}

arch_initcall(s5p_init_irq_eint);
Commit	Line	Data
0df04f82 JL	1	/* linux/arch/arm/plat-s5p/irq-eint.c
	2	*
	3	* Copyright (c) 2010 Samsung Electronics Co., Ltd.
	4	* http://www.samsung.com
	5	*
	6	* S5P - IRQ EINT support
	7	*
	8	* This program is free software; you can redistribute it and/or modify
	9	* it under the terms of the GNU General Public License version 2 as
	10	* published by the Free Software Foundation.
	11	*/
	12
	13	#include <linux/kernel.h>
	14	#include <linux/interrupt.h>
	15	#include <linux/irq.h>
	16	#include <linux/io.h>
edbaa603	17	#include <linux/device.h>
0df04f82 JL	18	#include <linux/gpio.h>
	19
	20	#include <asm/hardware/vic.h>
	21
	22	#include <plat/regs-irqtype.h>
	23
	24	#include <mach/map.h>
	25	#include <plat/cpu.h>
	26	#include <plat/pm.h>
	27
	28	#include <plat/gpio-cfg.h>
	29	#include <mach/regs-gpio.h>
	30
bb0b2374	31	static inline void s5p_irq_eint_mask(struct irq_data *data)
0df04f82 JL	32	{
	33	u32 mask;
	34
bb0b2374 LB	35	mask = __raw_readl(S5P_EINT_MASK(EINT_REG_NR(data->irq)));
	36	mask \|= eint_irq_to_bit(data->irq);
	37	__raw_writel(mask, S5P_EINT_MASK(EINT_REG_NR(data->irq)));
0df04f82 JL	38	}
0df04f82 JL	39
bb0b2374	40	static void s5p_irq_eint_unmask(struct irq_data *data)
0df04f82 JL	41	{
	42	u32 mask;
	43
bb0b2374 LB	44	mask = __raw_readl(S5P_EINT_MASK(EINT_REG_NR(data->irq)));
	45	mask &= ~(eint_irq_to_bit(data->irq));
	46	__raw_writel(mask, S5P_EINT_MASK(EINT_REG_NR(data->irq)));
0df04f82 JL	47	}
0df04f82 JL	48
bb0b2374	49	static inline void s5p_irq_eint_ack(struct irq_data *data)
0df04f82	50	{
bb0b2374 LB	51	__raw_writel(eint_irq_to_bit(data->irq),
bb0b2374 LB	52	S5P_EINT_PEND(EINT_REG_NR(data->irq)));
0df04f82 JL	53	}
0df04f82 JL	54
bb0b2374	55	static void s5p_irq_eint_maskack(struct irq_data *data)
0df04f82 JL	56	{
0df04f82 JL	57	/* compiler should in-line these */
bb0b2374 LB	58	s5p_irq_eint_mask(data);
bb0b2374 LB	59	s5p_irq_eint_ack(data);
0df04f82 JL	60	}
0df04f82 JL	61
bb0b2374	62	static int s5p_irq_eint_set_type(struct irq_data *data, unsigned int type)
0df04f82	63	{
bb0b2374	64	int offs = EINT_OFFSET(data->irq);
0df04f82 JL	65	int shift;
	66	u32 ctrl, mask;
	67	u32 newvalue = 0;
	68
	69	switch (type) {
	70	case IRQ_TYPE_EDGE_RISING:
9adf5d22	71	newvalue = S5P_IRQ_TYPE_EDGE_RISING;
0df04f82 JL	72	break;
	73
	74	case IRQ_TYPE_EDGE_FALLING:
9adf5d22	75	newvalue = S5P_IRQ_TYPE_EDGE_FALLING;
0df04f82 JL	76	break;
	77
	78	case IRQ_TYPE_EDGE_BOTH:
9adf5d22	79	newvalue = S5P_IRQ_TYPE_EDGE_BOTH;
0df04f82 JL	80	break;
	81
	82	case IRQ_TYPE_LEVEL_LOW:
9adf5d22	83	newvalue = S5P_IRQ_TYPE_LEVEL_LOW;
0df04f82 JL	84	break;
	85
	86	case IRQ_TYPE_LEVEL_HIGH:
9adf5d22	87	newvalue = S5P_IRQ_TYPE_LEVEL_HIGH;
0df04f82 JL	88	break;
	89
	90	default:
	91	printk(KERN_ERR "No such irq type %d", type);
	92	return -EINVAL;
	93	}
	94
	95	shift = (offs & 0x7) * 4;
	96	mask = 0x7 << shift;
	97
bb0b2374	98	ctrl = __raw_readl(S5P_EINT_CON(EINT_REG_NR(data->irq)));
0df04f82 JL	99	ctrl &= ~mask;
0df04f82 JL	100	ctrl \|= newvalue << shift;
bb0b2374	101	__raw_writel(ctrl, S5P_EINT_CON(EINT_REG_NR(data->irq)));
0df04f82 JL	102
	103	if ((0 <= offs) && (offs < 8))
	104	s3c_gpio_cfgpin(EINT_GPIO_0(offs & 0x7), EINT_MODE);
	105
	106	else if ((8 <= offs) && (offs < 16))
	107	s3c_gpio_cfgpin(EINT_GPIO_1(offs & 0x7), EINT_MODE);
	108
	109	else if ((16 <= offs) && (offs < 24))
	110	s3c_gpio_cfgpin(EINT_GPIO_2(offs & 0x7), EINT_MODE);
	111
	112	else if ((24 <= offs) && (offs < 32))
	113	s3c_gpio_cfgpin(EINT_GPIO_3(offs & 0x7), EINT_MODE);
	114
	115	else
	116	printk(KERN_ERR "No such irq number %d", offs);
	117
	118	return 0;
	119	}
	120
	121	static struct irq_chip s5p_irq_eint = {
	122	.name = "s5p-eint",
bb0b2374 LB	123	.irq_mask = s5p_irq_eint_mask,
	124	.irq_unmask = s5p_irq_eint_unmask,
	125	.irq_mask_ack = s5p_irq_eint_maskack,
	126	.irq_ack = s5p_irq_eint_ack,
	127	.irq_set_type = s5p_irq_eint_set_type,
0df04f82	128	#ifdef CONFIG_PM
f5aeffb7	129	.irq_set_wake = s3c_irqext_wake,
0df04f82 JL	130	#endif
	131	};
	132
	133	/* s5p_irq_demux_eint
	134	*
	135	* This function demuxes the IRQ from the group0 external interrupts,
	136	* from EINTs 16 to 31. It is designed to be inlined into the specific
	137	* handler s5p_irq_demux_eintX_Y.
	138	*
	139	* Each EINT pend/mask registers handle eight of them.
	140	*/
	141	static inline void s5p_irq_demux_eint(unsigned int start)
	142	{
5fae4058	143	u32 status = __raw_readl(S5P_EINT_PEND(EINT_REG_NR(start)));
0df04f82 JL	144	u32 mask = __raw_readl(S5P_EINT_MASK(EINT_REG_NR(start)));
	145	unsigned int irq;
	146
0df04f82 JL	147	status &= ~mask;
	148	status &= 0xff;
	149
	150	while (status) {
5fae4058 PB	151	irq = fls(status) - 1;
5fae4058 PB	152	generic_handle_irq(irq + start);
0df04f82 JL	153	status &= ~(1 << irq);
	154	}
	155	}
	156
	157	static void s5p_irq_demux_eint16_31(unsigned int irq, struct irq_desc *desc)
	158	{
	159	s5p_irq_demux_eint(IRQ_EINT(16));
	160	s5p_irq_demux_eint(IRQ_EINT(24));
	161	}
	162
bb0b2374	163	static inline void s5p_irq_vic_eint_mask(struct irq_data *data)
0df04f82	164	{
bb0b2374	165	void __iomem *base = irq_data_get_irq_chip_data(data);
5fae4058	166
bb0b2374 LB	167	s5p_irq_eint_mask(data);
bb0b2374 LB	168	writel(1 << EINT_OFFSET(data->irq), base + VIC_INT_ENABLE_CLEAR);
0df04f82 JL	169	}
0df04f82 JL	170
bb0b2374	171	static void s5p_irq_vic_eint_unmask(struct irq_data *data)
0df04f82	172	{
bb0b2374	173	void __iomem *base = irq_data_get_irq_chip_data(data);
5fae4058	174
bb0b2374 LB	175	s5p_irq_eint_unmask(data);
bb0b2374 LB	176	writel(1 << EINT_OFFSET(data->irq), base + VIC_INT_ENABLE);
0df04f82 JL	177	}
0df04f82 JL	178
bb0b2374	179	static inline void s5p_irq_vic_eint_ack(struct irq_data *data)
0df04f82	180	{
bb0b2374 LB	181	__raw_writel(eint_irq_to_bit(data->irq),
bb0b2374 LB	182	S5P_EINT_PEND(EINT_REG_NR(data->irq)));
0df04f82 JL	183	}
0df04f82 JL	184
bb0b2374	185	static void s5p_irq_vic_eint_maskack(struct irq_data *data)
0df04f82	186	{
bb0b2374 LB	187	s5p_irq_vic_eint_mask(data);
bb0b2374 LB	188	s5p_irq_vic_eint_ack(data);
0df04f82 JL	189	}
	190
	191	static struct irq_chip s5p_irq_vic_eint = {
	192	.name = "s5p_vic_eint",
bb0b2374 LB	193	.irq_mask = s5p_irq_vic_eint_mask,
	194	.irq_unmask = s5p_irq_vic_eint_unmask,
	195	.irq_mask_ack = s5p_irq_vic_eint_maskack,
	196	.irq_ack = s5p_irq_vic_eint_ack,
	197	.irq_set_type = s5p_irq_eint_set_type,
0df04f82	198	#ifdef CONFIG_PM
f5aeffb7	199	.irq_set_wake = s3c_irqext_wake,
0df04f82 JL	200	#endif
	201	};
	202
6d259a25	203	static int __init s5p_init_irq_eint(void)
0df04f82 JL	204	{
	205	int irq;
	206
	207	for (irq = IRQ_EINT(0); irq <= IRQ_EINT(15); irq++)
6845664a	208	irq_set_chip(irq, &s5p_irq_vic_eint);
0df04f82 JL	209
0df04f82 JL	210	for (irq = IRQ_EINT(16); irq <= IRQ_EINT(31); irq++) {
f38c02f3	211	irq_set_chip_and_handler(irq, &s5p_irq_eint, handle_level_irq);
0df04f82 JL	212	set_irq_flags(irq, IRQF_VALID);
	213	}
	214
6845664a	215	irq_set_chained_handler(IRQ_EINT16_31, s5p_irq_demux_eint16_31);
0df04f82 JL	216	return 0;
	217	}
	218
	219	arch_initcall(s5p_init_irq_eint);