[deliverable/linux.git] / arch / arm / plat-s5p / irq-gpioint.c

/* linux/arch/arm/plat-s5p/irq-gpioint.c
 *
 * Copyright (c) 2010 Samsung Electronics Co., Ltd.
 * Author: Kyungmin Park <kyungmin.park@samsung.com>
 * Author: Joonyoung Shim <jy0922.shim@samsung.com>
 * Author: Marek Szyprowski <m.szyprowski@samsung.com>
 *
 *  This program is free software; you can redistribute  it and/or modify it
 *  under  the terms of  the GNU General  Public License as published by the
 *  Free Software Foundation;  either version 2 of the  License, or (at your
 *  option) any later version.
 *
 */

#include <linux/kernel.h>
#include <linux/interrupt.h>
#include <linux/irq.h>
#include <linux/io.h>
#include <linux/gpio.h>
#include <linux/slab.h>

#include <mach/map.h>
#include <plat/gpio-core.h>
#include <plat/gpio-cfg.h>

#include <asm/mach/irq.h>

#define GPIO_BASE(chip)		(((unsigned long)(chip)->base) & 0xFFFFF000u)

#define CON_OFFSET		0x700
#define MASK_OFFSET		0x900
#define PEND_OFFSET		0xA00
#define REG_OFFSET(x)		((x) << 2)

struct s5p_gpioint_bank {
	struct list_head	list;
	int			start;
	int			nr_groups;
	int			irq;
	struct samsung_gpio_chip	**chips;
	void			(*handler)(unsigned int, struct irq_desc *);
};

static LIST_HEAD(banks);

static int s5p_gpioint_set_type(struct irq_data *d, unsigned int type)
{
	struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
	struct irq_chip_type *ct = gc->chip_types;
	unsigned int shift = (d->irq - gc->irq_base) << 2;

	switch (type) {
	case IRQ_TYPE_EDGE_RISING:
		type = S5P_IRQ_TYPE_EDGE_RISING;
		break;
	case IRQ_TYPE_EDGE_FALLING:
		type = S5P_IRQ_TYPE_EDGE_FALLING;
		break;
	case IRQ_TYPE_EDGE_BOTH:
		type = S5P_IRQ_TYPE_EDGE_BOTH;
		break;
	case IRQ_TYPE_LEVEL_HIGH:
		type = S5P_IRQ_TYPE_LEVEL_HIGH;
		break;
	case IRQ_TYPE_LEVEL_LOW:
		type = S5P_IRQ_TYPE_LEVEL_LOW;
		break;
	case IRQ_TYPE_NONE:
	default:
		printk(KERN_WARNING "No irq type\n");
		return -EINVAL;
	}

	gc->type_cache &= ~(0x7 << shift);
	gc->type_cache |= type << shift;
	writel(gc->type_cache, gc->reg_base + ct->regs.type);
	return 0;
}

static void s5p_gpioint_handler(unsigned int irq, struct irq_desc *desc)
{
	struct s5p_gpioint_bank *bank = irq_get_handler_data(irq);
	int group, pend_offset, mask_offset;
	unsigned int pend, mask;

	struct irq_chip *chip = irq_get_chip(irq);
	chained_irq_enter(chip, desc);

	for (group = 0; group < bank->nr_groups; group++) {
		struct samsung_gpio_chip *chip = bank->chips[group];
		if (!chip)
			continue;

		pend_offset = REG_OFFSET(group);
		pend = __raw_readl(GPIO_BASE(chip) + PEND_OFFSET + pend_offset);
		if (!pend)
			continue;

		mask_offset = REG_OFFSET(group);
		mask = __raw_readl(GPIO_BASE(chip) + MASK_OFFSET + mask_offset);
		pend &= ~mask;

		while (pend) {
			int offset = fls(pend) - 1;
			int real_irq = chip->irq_base + offset;
			generic_handle_irq(real_irq);
			pend &= ~BIT(offset);
		}
	}
	chained_irq_exit(chip, desc);
}

static __init int s5p_gpioint_add(struct samsung_gpio_chip *chip)
{
	static int used_gpioint_groups = 0;
	int group = chip->group;
	struct s5p_gpioint_bank *b, *bank = NULL;
	struct irq_chip_generic *gc;
	struct irq_chip_type *ct;

	if (used_gpioint_groups >= S5P_GPIOINT_GROUP_COUNT)
		return -ENOMEM;

	list_for_each_entry(b, &banks, list) {
		if (group >= b->start && group < b->start + b->nr_groups) {
			bank = b;
			break;
		}
	}
	if (!bank)
		return -EINVAL;

	if (!bank->handler) {
		bank->chips = kzalloc(sizeof(struct samsung_gpio_chip *) *
				      bank->nr_groups, GFP_KERNEL);
		if (!bank->chips)
			return -ENOMEM;

		irq_set_chained_handler(bank->irq, s5p_gpioint_handler);
		irq_set_handler_data(bank->irq, bank);
		bank->handler = s5p_gpioint_handler;
		printk(KERN_INFO "Registered chained gpio int handler for interrupt %d.\n",
		       bank->irq);
	}

	/*
	 * chained GPIO irq has been successfully registered, allocate new gpio
	 * int group and assign irq nubmers
	 */
	chip->irq_base = S5P_GPIOINT_BASE +
			 used_gpioint_groups * S5P_GPIOINT_GROUP_SIZE;
	used_gpioint_groups++;

	bank->chips[group - bank->start] = chip;

	gc = irq_alloc_generic_chip("s5p_gpioint", 1, chip->irq_base,
				    (void __iomem *)GPIO_BASE(chip),
				    handle_level_irq);
	if (!gc)
		return -ENOMEM;
	ct = gc->chip_types;
	ct->chip.irq_ack = irq_gc_ack_set_bit;
	ct->chip.irq_mask = irq_gc_mask_set_bit;
	ct->chip.irq_unmask = irq_gc_mask_clr_bit;
	ct->chip.irq_set_type = s5p_gpioint_set_type,
	ct->regs.ack = PEND_OFFSET + REG_OFFSET(group - bank->start);
	ct->regs.mask = MASK_OFFSET + REG_OFFSET(group - bank->start);
	ct->regs.type = CON_OFFSET + REG_OFFSET(group - bank->start);
	irq_setup_generic_chip(gc, IRQ_MSK(chip->chip.ngpio),
			       IRQ_GC_INIT_MASK_CACHE,
			       IRQ_NOREQUEST | IRQ_NOPROBE, 0);
	return 0;
}

int __init s5p_register_gpio_interrupt(int pin)
{
	struct samsung_gpio_chip *my_chip = samsung_gpiolib_getchip(pin);
	int offset, group;
	int ret;

	if (!my_chip)
		return -EINVAL;

	offset = pin - my_chip->chip.base;
	group = my_chip->group;

	/* check if the group has been already registered */
	if (my_chip->irq_base)
		return my_chip->irq_base + offset;

	/* register gpio group */
	ret = s5p_gpioint_add(my_chip);
	if (ret == 0) {
		my_chip->chip.to_irq = samsung_gpiolib_to_irq;
		printk(KERN_INFO "Registered interrupt support for gpio group %d.\n",
		       group);
		return my_chip->irq_base + offset;
	}
	return ret;
}

int __init s5p_register_gpioint_bank(int chain_irq, int start, int nr_groups)
{
	struct s5p_gpioint_bank *bank;

	bank = kzalloc(sizeof(*bank), GFP_KERNEL);
	if (!bank)
		return -ENOMEM;

	bank->start = start;
	bank->nr_groups = nr_groups;
	bank->irq = chain_irq;

	list_add_tail(&bank->list, &banks);
	return 0;
}
Commit	Line	Data
170a4617 MS	1	/* linux/arch/arm/plat-s5p/irq-gpioint.c
	2	*
	3	* Copyright (c) 2010 Samsung Electronics Co., Ltd.
	4	* Author: Kyungmin Park <kyungmin.park@samsung.com>
	5	* Author: Joonyoung Shim <jy0922.shim@samsung.com>
	6	* Author: Marek Szyprowski <m.szyprowski@samsung.com>
	7	*
	8	* This program is free software; you can redistribute it and/or modify it
	9	* under the terms of the GNU General Public License as published by the
	10	* Free Software Foundation; either version 2 of the License, or (at your
	11	* option) any later version.
	12	*
	13	*/
	14
	15	#include <linux/kernel.h>
	16	#include <linux/interrupt.h>
	17	#include <linux/irq.h>
	18	#include <linux/io.h>
	19	#include <linux/gpio.h>
a43efddc	20	#include <linux/slab.h>
170a4617 MS	21
	22	#include <mach/map.h>
	23	#include <plat/gpio-core.h>
	24	#include <plat/gpio-cfg.h>
	25
3f6065dd MS	26	#include <asm/mach/irq.h>
3f6065dd MS	27
2de09262	28	#define GPIO_BASE(chip) (((unsigned long)(chip)->base) & 0xFFFFF000u)
170a4617	29
2de09262 MS	30	#define CON_OFFSET 0x700
	31	#define MASK_OFFSET 0x900
	32	#define PEND_OFFSET 0xA00
	33	#define REG_OFFSET(x) ((x) << 2)
170a4617	34
a43efddc MS	35	struct s5p_gpioint_bank {
	36	struct list_head list;
	37	int start;
	38	int nr_groups;
	39	int irq;
782d8a3c	40	struct samsung_gpio_chip **chips;
a43efddc MS	41	void (handler)(unsigned int, struct irq_desc );
	42	};
	43
6d259a25	44	static LIST_HEAD(banks);
170a4617	45
ad739dcf	46	static int s5p_gpioint_set_type(struct irq_data *d, unsigned int type)
170a4617	47	{
ad739dcf TG	48	struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
	49	struct irq_chip_type *ct = gc->chip_types;
	50	unsigned int shift = (d->irq - gc->irq_base) << 2;
170a4617 MS	51
	52	switch (type) {
	53	case IRQ_TYPE_EDGE_RISING:
9adf5d22	54	type = S5P_IRQ_TYPE_EDGE_RISING;
170a4617 MS	55	break;
170a4617 MS	56	case IRQ_TYPE_EDGE_FALLING:
9adf5d22	57	type = S5P_IRQ_TYPE_EDGE_FALLING;
170a4617 MS	58	break;
170a4617 MS	59	case IRQ_TYPE_EDGE_BOTH:
9adf5d22	60	type = S5P_IRQ_TYPE_EDGE_BOTH;
170a4617 MS	61	break;
170a4617 MS	62	case IRQ_TYPE_LEVEL_HIGH:
9adf5d22	63	type = S5P_IRQ_TYPE_LEVEL_HIGH;
170a4617 MS	64	break;
170a4617 MS	65	case IRQ_TYPE_LEVEL_LOW:
9adf5d22	66	type = S5P_IRQ_TYPE_LEVEL_LOW;
170a4617 MS	67	break;
	68	case IRQ_TYPE_NONE:
	69	default:
	70	printk(KERN_WARNING "No irq type\n");
	71	return -EINVAL;
	72	}
	73
ad739dcf TG	74	gc->type_cache &= ~(0x7 << shift);
	75	gc->type_cache \|= type << shift;
	76	writel(gc->type_cache, gc->reg_base + ct->regs.type);
170a4617 MS	77	return 0;
	78	}
	79
170a4617 MS	80	static void s5p_gpioint_handler(unsigned int irq, struct irq_desc *desc)
170a4617 MS	81	{
6845664a	82	struct s5p_gpioint_bank *bank = irq_get_handler_data(irq);
2de09262	83	int group, pend_offset, mask_offset;
170a4617 MS	84	unsigned int pend, mask;
170a4617 MS	85
3f6065dd MS	86	struct irq_chip *chip = irq_get_chip(irq);
	87	chained_irq_enter(chip, desc);
	88
a43efddc	89	for (group = 0; group < bank->nr_groups; group++) {
782d8a3c	90	struct samsung_gpio_chip *chip = bank->chips[group];
2de09262 MS	91	if (!chip)
	92	continue;
	93
	94	pend_offset = REG_OFFSET(group);
	95	pend = __raw_readl(GPIO_BASE(chip) + PEND_OFFSET + pend_offset);
170a4617 MS	96	if (!pend)
	97	continue;
	98
2de09262 MS	99	mask_offset = REG_OFFSET(group);
2de09262 MS	100	mask = __raw_readl(GPIO_BASE(chip) + MASK_OFFSET + mask_offset);
170a4617 MS	101	pend &= ~mask;
170a4617 MS	102
2de09262 MS	103	while (pend) {
	104	int offset = fls(pend) - 1;
	105	int real_irq = chip->irq_base + offset;
	106	generic_handle_irq(real_irq);
	107	pend &= ~BIT(offset);
170a4617 MS	108	}
170a4617 MS	109	}
3f6065dd	110	chained_irq_exit(chip, desc);
170a4617 MS	111	}
170a4617 MS	112
782d8a3c	113	static __init int s5p_gpioint_add(struct samsung_gpio_chip *chip)
170a4617 MS	114	{
170a4617 MS	115	static int used_gpioint_groups = 0;
ad739dcf	116	int group = chip->group;
b76f7cdc	117	struct s5p_gpioint_bank b, bank = NULL;
ad739dcf TG	118	struct irq_chip_generic *gc;
ad739dcf TG	119	struct irq_chip_type *ct;
170a4617 MS	120
	121	if (used_gpioint_groups >= S5P_GPIOINT_GROUP_COUNT)
	122	return -ENOMEM;
	123
b76f7cdc MS	124	list_for_each_entry(b, &banks, list) {
	125	if (group >= b->start && group < b->start + b->nr_groups) {
	126	bank = b;
a43efddc	127	break;
b76f7cdc	128	}
a43efddc MS	129	}
	130	if (!bank)
	131	return -EINVAL;
	132
	133	if (!bank->handler) {
782d8a3c	134	bank->chips = kzalloc(sizeof(struct samsung_gpio_chip )
a43efddc MS	135	bank->nr_groups, GFP_KERNEL);
	136	if (!bank->chips)
	137	return -ENOMEM;
	138
6845664a TG	139	irq_set_chained_handler(bank->irq, s5p_gpioint_handler);
6845664a TG	140	irq_set_handler_data(bank->irq, bank);
a43efddc MS	141	bank->handler = s5p_gpioint_handler;
	142	printk(KERN_INFO "Registered chained gpio int handler for interrupt %d.\n",
	143	bank->irq);
	144	}
	145
	146	/*
25985edc	147	* chained GPIO irq has been successfully registered, allocate new gpio
a43efddc MS	148	* int group and assign irq nubmers
a43efddc MS	149	*/
170a4617 MS	150	chip->irq_base = S5P_GPIOINT_BASE +
	151	used_gpioint_groups * S5P_GPIOINT_GROUP_SIZE;
	152	used_gpioint_groups++;
	153
a43efddc	154	bank->chips[group - bank->start] = chip;
ad739dcf TG	155
	156	gc = irq_alloc_generic_chip("s5p_gpioint", 1, chip->irq_base,
	157	(void __iomem *)GPIO_BASE(chip),
	158	handle_level_irq);
	159	if (!gc)
	160	return -ENOMEM;
	161	ct = gc->chip_types;
659fb32d	162	ct->chip.irq_ack = irq_gc_ack_set_bit;
ad739dcf TG	163	ct->chip.irq_mask = irq_gc_mask_set_bit;
	164	ct->chip.irq_unmask = irq_gc_mask_clr_bit;
	165	ct->chip.irq_set_type = s5p_gpioint_set_type,
1052cff3 MS	166	ct->regs.ack = PEND_OFFSET + REG_OFFSET(group - bank->start);
	167	ct->regs.mask = MASK_OFFSET + REG_OFFSET(group - bank->start);
	168	ct->regs.type = CON_OFFSET + REG_OFFSET(group - bank->start);
ad739dcf TG	169	irq_setup_generic_chip(gc, IRQ_MSK(chip->chip.ngpio),
	170	IRQ_GC_INIT_MASK_CACHE,
	171	IRQ_NOREQUEST \| IRQ_NOPROBE, 0);
170a4617 MS	172	return 0;
	173	}
	174
	175	int __init s5p_register_gpio_interrupt(int pin)
	176	{
782d8a3c	177	struct samsung_gpio_chip *my_chip = samsung_gpiolib_getchip(pin);
170a4617 MS	178	int offset, group;
	179	int ret;
	180
	181	if (!my_chip)
	182	return -EINVAL;
	183
	184	offset = pin - my_chip->chip.base;
	185	group = my_chip->group;
	186
	187	/* check if the group has been already registered */
	188	if (my_chip->irq_base)
	189	return my_chip->irq_base + offset;
	190
	191	/* register gpio group */
	192	ret = s5p_gpioint_add(my_chip);
	193	if (ret == 0) {
8ce14a22	194	my_chip->chip.to_irq = samsung_gpiolib_to_irq;
170a4617 MS	195	printk(KERN_INFO "Registered interrupt support for gpio group %d.\n",
	196	group);
	197	return my_chip->irq_base + offset;
	198	}
	199	return ret;
	200	}
a43efddc MS	201
	202	int __init s5p_register_gpioint_bank(int chain_irq, int start, int nr_groups)
	203	{
	204	struct s5p_gpioint_bank *bank;
	205
	206	bank = kzalloc(sizeof(*bank), GFP_KERNEL);
	207	if (!bank)
	208	return -ENOMEM;
	209
	210	bank->start = start;
	211	bank->nr_groups = nr_groups;
	212	bank->irq = chain_irq;
	213
	214	list_add_tail(&bank->list, &banks);
	215	return 0;
	216	}