[deliverable/linux.git] / arch / arm / plat-s5p / irq-gpioint.c

/* linux/arch/arm/plat-s5p/irq-gpioint.c
 *
 * Copyright (c) 2010 Samsung Electronics Co., Ltd.
 * Author: Kyungmin Park <kyungmin.park@samsung.com>
 * Author: Joonyoung Shim <jy0922.shim@samsung.com>
 * Author: Marek Szyprowski <m.szyprowski@samsung.com>
 *
 *  This program is free software; you can redistribute  it and/or modify it
 *  under  the terms of  the GNU General  Public License as published by the
 *  Free Software Foundation;  either version 2 of the  License, or (at your
 *  option) any later version.
 *
 */

#include <linux/kernel.h>
#include <linux/interrupt.h>
#include <linux/irq.h>
#include <linux/io.h>
#include <linux/gpio.h>
#include <linux/slab.h>

#include <mach/map.h>
#include <plat/gpio-core.h>
#include <plat/gpio-cfg.h>

#define GPIO_BASE(chip)		(((unsigned long)(chip)->base) & 0xFFFFF000u)

#define CON_OFFSET		0x700
#define MASK_OFFSET		0x900
#define PEND_OFFSET		0xA00
#define REG_OFFSET(x)		((x) << 2)

struct s5p_gpioint_bank {
	struct list_head	list;
	int			start;
	int			nr_groups;
	int			irq;
	struct s3c_gpio_chip	**chips;
	void			(*handler)(unsigned int, struct irq_desc *);
};

LIST_HEAD(banks);

static int s5p_gpioint_get_offset(struct irq_data *data)
{
	struct s3c_gpio_chip *chip = irq_data_get_irq_handler_data(data);
	return data->irq - chip->irq_base;
}

static void s5p_gpioint_ack(struct irq_data *data)
{
	struct s3c_gpio_chip *chip = irq_data_get_irq_handler_data(data);
	int group, offset, pend_offset;
	unsigned int value;

	group = chip->group;
	offset = s5p_gpioint_get_offset(data);
	pend_offset = REG_OFFSET(group);

	value = __raw_readl(GPIO_BASE(chip) + PEND_OFFSET + pend_offset);
	value |= BIT(offset);
	__raw_writel(value, GPIO_BASE(chip) + PEND_OFFSET + pend_offset);
}

static void s5p_gpioint_mask(struct irq_data *data)
{
	struct s3c_gpio_chip *chip = irq_data_get_irq_handler_data(data);
	int group, offset, mask_offset;
	unsigned int value;

	group = chip->group;
	offset = s5p_gpioint_get_offset(data);
	mask_offset = REG_OFFSET(group);

	value = __raw_readl(GPIO_BASE(chip) + MASK_OFFSET + mask_offset);
	value |= BIT(offset);
	__raw_writel(value, GPIO_BASE(chip) + MASK_OFFSET + mask_offset);
}

static void s5p_gpioint_unmask(struct irq_data *data)
{
	struct s3c_gpio_chip *chip = irq_data_get_irq_handler_data(data);
	int group, offset, mask_offset;
	unsigned int value;

	group = chip->group;
	offset = s5p_gpioint_get_offset(data);
	mask_offset = REG_OFFSET(group);

	value = __raw_readl(GPIO_BASE(chip) + MASK_OFFSET + mask_offset);
	value &= ~BIT(offset);
	__raw_writel(value, GPIO_BASE(chip) + MASK_OFFSET + mask_offset);
}

static void s5p_gpioint_mask_ack(struct irq_data *data)
{
	s5p_gpioint_mask(data);
	s5p_gpioint_ack(data);
}

static int s5p_gpioint_set_type(struct irq_data *data, unsigned int type)
{
	struct s3c_gpio_chip *chip = irq_data_get_irq_handler_data(data);
	int group, offset, con_offset;
	unsigned int value;

	group = chip->group;
	offset = s5p_gpioint_get_offset(data);
	con_offset = REG_OFFSET(group);

	switch (type) {
	case IRQ_TYPE_EDGE_RISING:
		type = S5P_IRQ_TYPE_EDGE_RISING;
		break;
	case IRQ_TYPE_EDGE_FALLING:
		type = S5P_IRQ_TYPE_EDGE_FALLING;
		break;
	case IRQ_TYPE_EDGE_BOTH:
		type = S5P_IRQ_TYPE_EDGE_BOTH;
		break;
	case IRQ_TYPE_LEVEL_HIGH:
		type = S5P_IRQ_TYPE_LEVEL_HIGH;
		break;
	case IRQ_TYPE_LEVEL_LOW:
		type = S5P_IRQ_TYPE_LEVEL_LOW;
		break;
	case IRQ_TYPE_NONE:
	default:
		printk(KERN_WARNING "No irq type\n");
		return -EINVAL;
	}

	value = __raw_readl(GPIO_BASE(chip) + CON_OFFSET + con_offset);
	value &= ~(0x7 << (offset * 0x4));
	value |= (type << (offset * 0x4));
	__raw_writel(value, GPIO_BASE(chip) + CON_OFFSET + con_offset);

	return 0;
}

static struct irq_chip s5p_gpioint = {
	.name		= "s5p_gpioint",
	.irq_ack	= s5p_gpioint_ack,
	.irq_mask	= s5p_gpioint_mask,
	.irq_mask_ack	= s5p_gpioint_mask_ack,
	.irq_unmask	= s5p_gpioint_unmask,
	.irq_set_type	= s5p_gpioint_set_type,
};

static void s5p_gpioint_handler(unsigned int irq, struct irq_desc *desc)
{
	struct s5p_gpioint_bank *bank = irq_get_handler_data(irq);
	int group, pend_offset, mask_offset;
	unsigned int pend, mask;

	for (group = 0; group < bank->nr_groups; group++) {
		struct s3c_gpio_chip *chip = bank->chips[group];
		if (!chip)
			continue;

		pend_offset = REG_OFFSET(group);
		pend = __raw_readl(GPIO_BASE(chip) + PEND_OFFSET + pend_offset);
		if (!pend)
			continue;

		mask_offset = REG_OFFSET(group);
		mask = __raw_readl(GPIO_BASE(chip) + MASK_OFFSET + mask_offset);
		pend &= ~mask;

		while (pend) {
			int offset = fls(pend) - 1;
			int real_irq = chip->irq_base + offset;
			generic_handle_irq(real_irq);
			pend &= ~BIT(offset);
		}
	}
}

static __init int s5p_gpioint_add(struct s3c_gpio_chip *chip)
{
	static int used_gpioint_groups = 0;
	int irq, group = chip->group;
	int i;
	struct s5p_gpioint_bank *bank = NULL;

	if (used_gpioint_groups >= S5P_GPIOINT_GROUP_COUNT)
		return -ENOMEM;

	list_for_each_entry(bank, &banks, list) {
		if (group >= bank->start &&
		    group < bank->start + bank->nr_groups)
			break;
	}
	if (!bank)
		return -EINVAL;

	if (!bank->handler) {
		bank->chips = kzalloc(sizeof(struct s3c_gpio_chip *) *
				      bank->nr_groups, GFP_KERNEL);
		if (!bank->chips)
			return -ENOMEM;

		irq_set_chained_handler(bank->irq, s5p_gpioint_handler);
		irq_set_handler_data(bank->irq, bank);
		bank->handler = s5p_gpioint_handler;
		printk(KERN_INFO "Registered chained gpio int handler for interrupt %d.\n",
		       bank->irq);
	}

	/*
	 * chained GPIO irq has been successfully registered, allocate new gpio
	 * int group and assign irq nubmers
	 */

	chip->irq_base = S5P_GPIOINT_BASE +
			 used_gpioint_groups * S5P_GPIOINT_GROUP_SIZE;
	used_gpioint_groups++;

	bank->chips[group - bank->start] = chip;
	for (i = 0; i < chip->chip.ngpio; i++) {
		irq = chip->irq_base + i;
		irq_set_chip(irq, &s5p_gpioint);
		irq_set_handler_data(irq, chip);
		irq_set_handler(irq, handle_level_irq);
		set_irq_flags(irq, IRQF_VALID);
	}
	return 0;
}

int __init s5p_register_gpio_interrupt(int pin)
{
	struct s3c_gpio_chip *my_chip = s3c_gpiolib_getchip(pin);
	int offset, group;
	int ret;

	if (!my_chip)
		return -EINVAL;

	offset = pin - my_chip->chip.base;
	group = my_chip->group;

	/* check if the group has been already registered */
	if (my_chip->irq_base)
		return my_chip->irq_base + offset;

	/* register gpio group */
	ret = s5p_gpioint_add(my_chip);
	if (ret == 0) {
		my_chip->chip.to_irq = samsung_gpiolib_to_irq;
		printk(KERN_INFO "Registered interrupt support for gpio group %d.\n",
		       group);
		return my_chip->irq_base + offset;
	}
	return ret;
}

int __init s5p_register_gpioint_bank(int chain_irq, int start, int nr_groups)
{
	struct s5p_gpioint_bank *bank;

	bank = kzalloc(sizeof(*bank), GFP_KERNEL);
	if (!bank)
		return -ENOMEM;

	bank->start = start;
	bank->nr_groups = nr_groups;
	bank->irq = chain_irq;

	list_add_tail(&bank->list, &banks);
	return 0;
}
Commit	Line	Data
170a4617 MS	1	/* linux/arch/arm/plat-s5p/irq-gpioint.c
	2	*
	3	* Copyright (c) 2010 Samsung Electronics Co., Ltd.
	4	* Author: Kyungmin Park <kyungmin.park@samsung.com>
	5	* Author: Joonyoung Shim <jy0922.shim@samsung.com>
	6	* Author: Marek Szyprowski <m.szyprowski@samsung.com>
	7	*
	8	* This program is free software; you can redistribute it and/or modify it
	9	* under the terms of the GNU General Public License as published by the
	10	* Free Software Foundation; either version 2 of the License, or (at your
	11	* option) any later version.
	12	*
	13	*/
	14
	15	#include <linux/kernel.h>
	16	#include <linux/interrupt.h>
	17	#include <linux/irq.h>
	18	#include <linux/io.h>
	19	#include <linux/gpio.h>
a43efddc	20	#include <linux/slab.h>
170a4617 MS	21
	22	#include <mach/map.h>
	23	#include <plat/gpio-core.h>
	24	#include <plat/gpio-cfg.h>
	25
2de09262	26	#define GPIO_BASE(chip) (((unsigned long)(chip)->base) & 0xFFFFF000u)
170a4617	27
2de09262 MS	28	#define CON_OFFSET 0x700
	29	#define MASK_OFFSET 0x900
	30	#define PEND_OFFSET 0xA00
	31	#define REG_OFFSET(x) ((x) << 2)
170a4617	32
a43efddc MS	33	struct s5p_gpioint_bank {
	34	struct list_head list;
	35	int start;
	36	int nr_groups;
	37	int irq;
	38	struct s3c_gpio_chip **chips;
	39	void (handler)(unsigned int, struct irq_desc );
	40	};
	41
	42	LIST_HEAD(banks);
170a4617	43
bb0b2374	44	static int s5p_gpioint_get_offset(struct irq_data *data)
170a4617	45	{
6845664a	46	struct s3c_gpio_chip *chip = irq_data_get_irq_handler_data(data);
2de09262	47	return data->irq - chip->irq_base;
170a4617 MS	48	}
170a4617 MS	49
bb0b2374	50	static void s5p_gpioint_ack(struct irq_data *data)
170a4617	51	{
6845664a	52	struct s3c_gpio_chip *chip = irq_data_get_irq_handler_data(data);
170a4617 MS	53	int group, offset, pend_offset;
	54	unsigned int value;
	55
2de09262	56	group = chip->group;
bb0b2374	57	offset = s5p_gpioint_get_offset(data);
2de09262	58	pend_offset = REG_OFFSET(group);
170a4617	59
2de09262 MS	60	value = __raw_readl(GPIO_BASE(chip) + PEND_OFFSET + pend_offset);
	61	value \|= BIT(offset);
	62	__raw_writel(value, GPIO_BASE(chip) + PEND_OFFSET + pend_offset);
170a4617 MS	63	}
170a4617 MS	64
bb0b2374	65	static void s5p_gpioint_mask(struct irq_data *data)
170a4617	66	{
6845664a	67	struct s3c_gpio_chip *chip = irq_data_get_irq_handler_data(data);
170a4617 MS	68	int group, offset, mask_offset;
	69	unsigned int value;
	70
2de09262	71	group = chip->group;
bb0b2374	72	offset = s5p_gpioint_get_offset(data);
2de09262	73	mask_offset = REG_OFFSET(group);
170a4617	74
2de09262 MS	75	value = __raw_readl(GPIO_BASE(chip) + MASK_OFFSET + mask_offset);
	76	value \|= BIT(offset);
	77	__raw_writel(value, GPIO_BASE(chip) + MASK_OFFSET + mask_offset);
170a4617 MS	78	}
170a4617 MS	79
bb0b2374	80	static void s5p_gpioint_unmask(struct irq_data *data)
170a4617	81	{
6845664a	82	struct s3c_gpio_chip *chip = irq_data_get_irq_handler_data(data);
170a4617 MS	83	int group, offset, mask_offset;
	84	unsigned int value;
	85
2de09262	86	group = chip->group;
bb0b2374	87	offset = s5p_gpioint_get_offset(data);
2de09262	88	mask_offset = REG_OFFSET(group);
170a4617	89
2de09262 MS	90	value = __raw_readl(GPIO_BASE(chip) + MASK_OFFSET + mask_offset);
	91	value &= ~BIT(offset);
	92	__raw_writel(value, GPIO_BASE(chip) + MASK_OFFSET + mask_offset);
170a4617 MS	93	}
170a4617 MS	94
bb0b2374	95	static void s5p_gpioint_mask_ack(struct irq_data *data)
170a4617	96	{
bb0b2374 LB	97	s5p_gpioint_mask(data);
bb0b2374 LB	98	s5p_gpioint_ack(data);
170a4617 MS	99	}
170a4617 MS	100
bb0b2374	101	static int s5p_gpioint_set_type(struct irq_data *data, unsigned int type)
170a4617	102	{
6845664a	103	struct s3c_gpio_chip *chip = irq_data_get_irq_handler_data(data);
170a4617 MS	104	int group, offset, con_offset;
	105	unsigned int value;
	106
2de09262	107	group = chip->group;
bb0b2374	108	offset = s5p_gpioint_get_offset(data);
2de09262	109	con_offset = REG_OFFSET(group);
170a4617 MS	110
	111	switch (type) {
	112	case IRQ_TYPE_EDGE_RISING:
9adf5d22	113	type = S5P_IRQ_TYPE_EDGE_RISING;
170a4617 MS	114	break;
170a4617 MS	115	case IRQ_TYPE_EDGE_FALLING:
9adf5d22	116	type = S5P_IRQ_TYPE_EDGE_FALLING;
170a4617 MS	117	break;
170a4617 MS	118	case IRQ_TYPE_EDGE_BOTH:
9adf5d22	119	type = S5P_IRQ_TYPE_EDGE_BOTH;
170a4617 MS	120	break;
170a4617 MS	121	case IRQ_TYPE_LEVEL_HIGH:
9adf5d22	122	type = S5P_IRQ_TYPE_LEVEL_HIGH;
170a4617 MS	123	break;
170a4617 MS	124	case IRQ_TYPE_LEVEL_LOW:
9adf5d22	125	type = S5P_IRQ_TYPE_LEVEL_LOW;
170a4617 MS	126	break;
	127	case IRQ_TYPE_NONE:
	128	default:
	129	printk(KERN_WARNING "No irq type\n");
	130	return -EINVAL;
	131	}
	132
2de09262	133	value = __raw_readl(GPIO_BASE(chip) + CON_OFFSET + con_offset);
170a4617 MS	134	value &= ~(0x7 << (offset * 0x4));
170a4617 MS	135	value \|= (type << (offset * 0x4));
2de09262	136	__raw_writel(value, GPIO_BASE(chip) + CON_OFFSET + con_offset);
170a4617 MS	137
	138	return 0;
	139	}
	140
2de09262	141	static struct irq_chip s5p_gpioint = {
170a4617	142	.name = "s5p_gpioint",
bb0b2374 LB	143	.irq_ack = s5p_gpioint_ack,
	144	.irq_mask = s5p_gpioint_mask,
	145	.irq_mask_ack = s5p_gpioint_mask_ack,
	146	.irq_unmask = s5p_gpioint_unmask,
	147	.irq_set_type = s5p_gpioint_set_type,
170a4617 MS	148	};
	149
	150	static void s5p_gpioint_handler(unsigned int irq, struct irq_desc *desc)
	151	{
6845664a	152	struct s5p_gpioint_bank *bank = irq_get_handler_data(irq);
2de09262	153	int group, pend_offset, mask_offset;
170a4617 MS	154	unsigned int pend, mask;
170a4617 MS	155
a43efddc MS	156	for (group = 0; group < bank->nr_groups; group++) {
a43efddc MS	157	struct s3c_gpio_chip *chip = bank->chips[group];
2de09262 MS	158	if (!chip)
	159	continue;
	160
	161	pend_offset = REG_OFFSET(group);
	162	pend = __raw_readl(GPIO_BASE(chip) + PEND_OFFSET + pend_offset);
170a4617 MS	163	if (!pend)
	164	continue;
	165
2de09262 MS	166	mask_offset = REG_OFFSET(group);
2de09262 MS	167	mask = __raw_readl(GPIO_BASE(chip) + MASK_OFFSET + mask_offset);
170a4617 MS	168	pend &= ~mask;
170a4617 MS	169
2de09262 MS	170	while (pend) {
	171	int offset = fls(pend) - 1;
	172	int real_irq = chip->irq_base + offset;
	173	generic_handle_irq(real_irq);
	174	pend &= ~BIT(offset);
170a4617 MS	175	}
	176	}
	177	}
	178
	179	static __init int s5p_gpioint_add(struct s3c_gpio_chip *chip)
	180	{
	181	static int used_gpioint_groups = 0;
170a4617 MS	182	int irq, group = chip->group;
170a4617 MS	183	int i;
a43efddc	184	struct s5p_gpioint_bank *bank = NULL;
170a4617 MS	185
	186	if (used_gpioint_groups >= S5P_GPIOINT_GROUP_COUNT)
	187	return -ENOMEM;
	188
a43efddc MS	189	list_for_each_entry(bank, &banks, list) {
	190	if (group >= bank->start &&
	191	group < bank->start + bank->nr_groups)
	192	break;
	193	}
	194	if (!bank)
	195	return -EINVAL;
	196
	197	if (!bank->handler) {
	198	bank->chips = kzalloc(sizeof(struct s3c_gpio_chip )
	199	bank->nr_groups, GFP_KERNEL);
	200	if (!bank->chips)
	201	return -ENOMEM;
	202
6845664a TG	203	irq_set_chained_handler(bank->irq, s5p_gpioint_handler);
6845664a TG	204	irq_set_handler_data(bank->irq, bank);
a43efddc MS	205	bank->handler = s5p_gpioint_handler;
	206	printk(KERN_INFO "Registered chained gpio int handler for interrupt %d.\n",
	207	bank->irq);
	208	}
	209
	210	/*
25985edc	211	* chained GPIO irq has been successfully registered, allocate new gpio
a43efddc MS	212	* int group and assign irq nubmers
	213	*/
	214
170a4617 MS	215	chip->irq_base = S5P_GPIOINT_BASE +
	216	used_gpioint_groups * S5P_GPIOINT_GROUP_SIZE;
	217	used_gpioint_groups++;
	218
a43efddc	219	bank->chips[group - bank->start] = chip;
170a4617 MS	220	for (i = 0; i < chip->chip.ngpio; i++) {
170a4617 MS	221	irq = chip->irq_base + i;
6845664a TG	222	irq_set_chip(irq, &s5p_gpioint);
	223	irq_set_handler_data(irq, chip);
	224	irq_set_handler(irq, handle_level_irq);
170a4617 MS	225	set_irq_flags(irq, IRQF_VALID);
	226	}
	227	return 0;
	228	}
	229
	230	int __init s5p_register_gpio_interrupt(int pin)
	231	{
	232	struct s3c_gpio_chip *my_chip = s3c_gpiolib_getchip(pin);
	233	int offset, group;
	234	int ret;
	235
	236	if (!my_chip)
	237	return -EINVAL;
	238
	239	offset = pin - my_chip->chip.base;
	240	group = my_chip->group;
	241
	242	/* check if the group has been already registered */
	243	if (my_chip->irq_base)
	244	return my_chip->irq_base + offset;
	245
	246	/* register gpio group */
	247	ret = s5p_gpioint_add(my_chip);
	248	if (ret == 0) {
8ce14a22	249	my_chip->chip.to_irq = samsung_gpiolib_to_irq;
170a4617 MS	250	printk(KERN_INFO "Registered interrupt support for gpio group %d.\n",
	251	group);
	252	return my_chip->irq_base + offset;
	253	}
	254	return ret;
	255	}
a43efddc MS	256
	257	int __init s5p_register_gpioint_bank(int chain_irq, int start, int nr_groups)
	258	{
	259	struct s5p_gpioint_bank *bank;
	260
	261	bank = kzalloc(sizeof(*bank), GFP_KERNEL);
	262	if (!bank)
	263	return -ENOMEM;
	264
	265	bank->start = start;
	266	bank->nr_groups = nr_groups;
	267	bank->irq = chain_irq;
	268
	269	list_add_tail(&bank->list, &banks);
	270	return 0;
	271	}