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1 | /* linux/arch/arm/plat-s5p/irq-pm.c |
2 | * | |
3 | * Copyright (c) 2010 Samsung Electronics Co., Ltd. | |
4 | * http://www.samsung.com | |
5 | * | |
6 | * Based on arch/arm/plat-s3c24xx/irq-pm.c, | |
7 | * Copyright (c) 2003,2004 Simtec Electronics | |
8 | * Ben Dooks <ben@simtec.co.uk> | |
9 | * http://armlinux.simtec.co.uk/ | |
10 | * | |
11 | * This program is free software; you can redistribute it and/or modify | |
12 | * it under the terms of the GNU General Public License version 2 as | |
13 | * published by the Free Software Foundation. | |
14 | */ | |
15 | ||
16 | #include <linux/init.h> | |
17 | #include <linux/module.h> | |
18 | #include <linux/interrupt.h> | |
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19 | |
20 | #include <plat/cpu.h> | |
21 | #include <plat/irqs.h> | |
22 | #include <plat/pm.h> | |
23 | #include <mach/map.h> | |
24 | ||
25 | #include <mach/regs-gpio.h> | |
26 | #include <mach/regs-irq.h> | |
27 | ||
28 | /* state for IRQs over sleep */ | |
29 | ||
30 | /* default is to allow for EINT0..EINT31, and IRQ_RTC_TIC, IRQ_RTC_ALARM, | |
31 | * as wakeup sources | |
32 | * | |
33 | * set bit to 1 in allow bitfield to enable the wakeup settings on it | |
34 | */ | |
35 | ||
36 | unsigned long s3c_irqwake_intallow = 0x00000006L; | |
37 | unsigned long s3c_irqwake_eintallow = 0xffffffffL; | |
38 | ||
bb0b2374 | 39 | int s3c_irq_wake(struct irq_data *data, unsigned int state) |
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40 | { |
41 | unsigned long irqbit; | |
42 | ||
bb0b2374 | 43 | switch (data->irq) { |
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44 | case IRQ_RTC_TIC: |
45 | case IRQ_RTC_ALARM: | |
bb0b2374 | 46 | irqbit = 1 << (data->irq + 1 - IRQ_RTC_ALARM); |
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47 | if (!state) |
48 | s3c_irqwake_intmask |= irqbit; | |
49 | else | |
50 | s3c_irqwake_intmask &= ~irqbit; | |
51 | break; | |
52 | default: | |
53 | return -ENOENT; | |
54 | } | |
55 | return 0; | |
56 | } | |
57 | ||
58 | static struct sleep_save eint_save[] = { | |
59 | SAVE_ITEM(S5P_EINT_CON(0)), | |
60 | SAVE_ITEM(S5P_EINT_CON(1)), | |
61 | SAVE_ITEM(S5P_EINT_CON(2)), | |
62 | SAVE_ITEM(S5P_EINT_CON(3)), | |
63 | ||
64 | SAVE_ITEM(S5P_EINT_FLTCON(0)), | |
65 | SAVE_ITEM(S5P_EINT_FLTCON(1)), | |
66 | SAVE_ITEM(S5P_EINT_FLTCON(2)), | |
67 | SAVE_ITEM(S5P_EINT_FLTCON(3)), | |
68 | SAVE_ITEM(S5P_EINT_FLTCON(4)), | |
69 | SAVE_ITEM(S5P_EINT_FLTCON(5)), | |
70 | SAVE_ITEM(S5P_EINT_FLTCON(6)), | |
71 | SAVE_ITEM(S5P_EINT_FLTCON(7)), | |
72 | ||
73 | SAVE_ITEM(S5P_EINT_MASK(0)), | |
74 | SAVE_ITEM(S5P_EINT_MASK(1)), | |
75 | SAVE_ITEM(S5P_EINT_MASK(2)), | |
76 | SAVE_ITEM(S5P_EINT_MASK(3)), | |
77 | }; | |
78 | ||
bb072c3c | 79 | int s3c24xx_irq_suspend(void) |
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80 | { |
81 | s3c_pm_do_save(eint_save, ARRAY_SIZE(eint_save)); | |
82 | ||
83 | return 0; | |
84 | } | |
85 | ||
bb072c3c | 86 | void s3c24xx_irq_resume(void) |
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87 | { |
88 | s3c_pm_do_restore(eint_save, ARRAY_SIZE(eint_save)); | |
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89 | } |
90 |