Commit | Line | Data |
---|---|---|
3929e1e7 | 1 | /* arch/arm/plat-samsung/adc.c |
28ab44c5 BD |
2 | * |
3 | * Copyright (c) 2008 Simtec Electronics | |
4 | * http://armlinux.simtec.co.uk/ | |
5 | * Ben Dooks <ben@simtec.co.uk>, <ben-linux@fluff.org> | |
6 | * | |
3929e1e7 | 7 | * Samsung ADC device core |
28ab44c5 BD |
8 | * |
9 | * This program is free software; you can redistribute it and/or modify | |
10 | * it under the terms of the GNU General Public License as published by | |
11 | * the Free Software Foundation; either version 2 of the License. | |
12 | */ | |
13 | ||
14 | #include <linux/module.h> | |
15 | #include <linux/kernel.h> | |
16 | #include <linux/platform_device.h> | |
d43c36dc | 17 | #include <linux/sched.h> |
28ab44c5 | 18 | #include <linux/list.h> |
5a0e3ad6 | 19 | #include <linux/slab.h> |
28ab44c5 BD |
20 | #include <linux/err.h> |
21 | #include <linux/clk.h> | |
22 | #include <linux/interrupt.h> | |
23 | #include <linux/io.h> | |
f462904e | 24 | #include <linux/regulator/consumer.h> |
28ab44c5 BD |
25 | |
26 | #include <plat/regs-adc.h> | |
27 | #include <plat/adc.h> | |
28 | ||
29 | /* This driver is designed to control the usage of the ADC block between | |
30 | * the touchscreen and any other drivers that may need to use it, such as | |
31 | * the hwmon driver. | |
32 | * | |
33 | * Priority will be given to the touchscreen driver, but as this itself is | |
34 | * rate limited it should not starve other requests which are processed in | |
35 | * order that they are received. | |
36 | * | |
37 | * Each user registers to get a client block which uniquely identifies it | |
38 | * and stores information such as the necessary functions to callback when | |
39 | * action is required. | |
40 | */ | |
41 | ||
bcedfa98 | 42 | enum s3c_cpu_type { |
64df92ea | 43 | TYPE_ADCV1, /* S3C24XX */ |
6247cea2 | 44 | TYPE_ADCV11, /* S3C2443 */ |
35cc3cea | 45 | TYPE_ADCV12, /* S3C2416, S3C2450 */ |
64df92ea MH |
46 | TYPE_ADCV2, /* S3C64XX, S5P64X0, S5PC100 */ |
47 | TYPE_ADCV3, /* S5PV210, S5PC110, EXYNOS4210 */ | |
bcedfa98 MC |
48 | }; |
49 | ||
28ab44c5 BD |
50 | struct s3c_adc_client { |
51 | struct platform_device *pdev; | |
52 | struct list_head pend; | |
e170adcb | 53 | wait_queue_head_t *wait; |
28ab44c5 BD |
54 | |
55 | unsigned int nr_samples; | |
e170adcb | 56 | int result; |
28ab44c5 BD |
57 | unsigned char is_ts; |
58 | unsigned char channel; | |
59 | ||
e170adcb BD |
60 | void (*select_cb)(struct s3c_adc_client *c, unsigned selected); |
61 | void (*convert_cb)(struct s3c_adc_client *c, | |
62 | unsigned val1, unsigned val2, | |
3f7ea467 | 63 | unsigned *samples_left); |
28ab44c5 BD |
64 | }; |
65 | ||
66 | struct adc_device { | |
67 | struct platform_device *pdev; | |
68 | struct platform_device *owner; | |
69 | struct clk *clk; | |
70 | struct s3c_adc_client *cur; | |
71 | struct s3c_adc_client *ts_pend; | |
72 | void __iomem *regs; | |
1f1f584c | 73 | spinlock_t lock; |
28ab44c5 BD |
74 | |
75 | unsigned int prescale; | |
76 | ||
77 | int irq; | |
f462904e | 78 | struct regulator *vdd; |
28ab44c5 BD |
79 | }; |
80 | ||
81 | static struct adc_device *adc_dev; | |
82 | ||
1f1f584c | 83 | static LIST_HEAD(adc_pending); /* protected by adc_device.lock */ |
28ab44c5 BD |
84 | |
85 | #define adc_dbg(_adc, msg...) dev_dbg(&(_adc)->pdev->dev, msg) | |
86 | ||
87 | static inline void s3c_adc_convert(struct adc_device *adc) | |
88 | { | |
89 | unsigned con = readl(adc->regs + S3C2410_ADCCON); | |
90 | ||
91 | con |= S3C2410_ADCCON_ENABLE_START; | |
92 | writel(con, adc->regs + S3C2410_ADCCON); | |
93 | } | |
94 | ||
95 | static inline void s3c_adc_select(struct adc_device *adc, | |
96 | struct s3c_adc_client *client) | |
97 | { | |
98 | unsigned con = readl(adc->regs + S3C2410_ADCCON); | |
64df92ea | 99 | enum s3c_cpu_type cpu = platform_get_device_id(adc->pdev)->driver_data; |
28ab44c5 | 100 | |
e170adcb | 101 | client->select_cb(client, 1); |
28ab44c5 | 102 | |
df303e02 HS |
103 | if (cpu == TYPE_ADCV1 || cpu == TYPE_ADCV2) |
104 | con &= ~S3C2410_ADCCON_MUXMASK; | |
28ab44c5 BD |
105 | con &= ~S3C2410_ADCCON_STDBM; |
106 | con &= ~S3C2410_ADCCON_STARTMASK; | |
107 | ||
64df92ea MH |
108 | if (!client->is_ts) { |
109 | if (cpu == TYPE_ADCV3) | |
110 | writel(client->channel & 0xf, adc->regs + S5P_ADCMUX); | |
35cc3cea | 111 | else if (cpu == TYPE_ADCV11 || cpu == TYPE_ADCV12) |
6247cea2 HS |
112 | writel(client->channel & 0xf, |
113 | adc->regs + S3C2443_ADCMUX); | |
64df92ea MH |
114 | else |
115 | con |= S3C2410_ADCCON_SELMUX(client->channel); | |
116 | } | |
28ab44c5 BD |
117 | |
118 | writel(con, adc->regs + S3C2410_ADCCON); | |
119 | } | |
120 | ||
121 | static void s3c_adc_dbgshow(struct adc_device *adc) | |
122 | { | |
123 | adc_dbg(adc, "CON=%08x, TSC=%08x, DLY=%08x\n", | |
124 | readl(adc->regs + S3C2410_ADCCON), | |
125 | readl(adc->regs + S3C2410_ADCTSC), | |
126 | readl(adc->regs + S3C2410_ADCDLY)); | |
127 | } | |
128 | ||
f8c8ac81 | 129 | static void s3c_adc_try(struct adc_device *adc) |
28ab44c5 BD |
130 | { |
131 | struct s3c_adc_client *next = adc->ts_pend; | |
132 | ||
133 | if (!next && !list_empty(&adc_pending)) { | |
134 | next = list_first_entry(&adc_pending, | |
135 | struct s3c_adc_client, pend); | |
136 | list_del(&next->pend); | |
137 | } else | |
138 | adc->ts_pend = NULL; | |
139 | ||
140 | if (next) { | |
141 | adc_dbg(adc, "new client is %p\n", next); | |
142 | adc->cur = next; | |
143 | s3c_adc_select(adc, next); | |
144 | s3c_adc_convert(adc); | |
145 | s3c_adc_dbgshow(adc); | |
146 | } | |
147 | } | |
148 | ||
149 | int s3c_adc_start(struct s3c_adc_client *client, | |
150 | unsigned int channel, unsigned int nr_samples) | |
151 | { | |
152 | struct adc_device *adc = adc_dev; | |
153 | unsigned long flags; | |
154 | ||
155 | if (!adc) { | |
156 | printk(KERN_ERR "%s: failed to find adc\n", __func__); | |
157 | return -EINVAL; | |
158 | } | |
159 | ||
160 | if (client->is_ts && adc->ts_pend) | |
161 | return -EAGAIN; | |
162 | ||
1f1f584c | 163 | spin_lock_irqsave(&adc->lock, flags); |
28ab44c5 BD |
164 | |
165 | client->channel = channel; | |
166 | client->nr_samples = nr_samples; | |
167 | ||
168 | if (client->is_ts) | |
169 | adc->ts_pend = client; | |
170 | else | |
171 | list_add_tail(&client->pend, &adc_pending); | |
172 | ||
173 | if (!adc->cur) | |
174 | s3c_adc_try(adc); | |
1f1f584c BD |
175 | |
176 | spin_unlock_irqrestore(&adc->lock, flags); | |
28ab44c5 BD |
177 | |
178 | return 0; | |
179 | } | |
180 | EXPORT_SYMBOL_GPL(s3c_adc_start); | |
181 | ||
e170adcb BD |
182 | static void s3c_convert_done(struct s3c_adc_client *client, |
183 | unsigned v, unsigned u, unsigned *left) | |
184 | { | |
185 | client->result = v; | |
186 | wake_up(client->wait); | |
187 | } | |
188 | ||
189 | int s3c_adc_read(struct s3c_adc_client *client, unsigned int ch) | |
190 | { | |
191 | DECLARE_WAIT_QUEUE_HEAD_ONSTACK(wake); | |
192 | int ret; | |
193 | ||
194 | client->convert_cb = s3c_convert_done; | |
195 | client->wait = &wake; | |
196 | client->result = -1; | |
197 | ||
198 | ret = s3c_adc_start(client, ch, 1); | |
199 | if (ret < 0) | |
200 | goto err; | |
201 | ||
202 | ret = wait_event_timeout(wake, client->result >= 0, HZ / 2); | |
203 | if (client->result < 0) { | |
204 | ret = -ETIMEDOUT; | |
205 | goto err; | |
206 | } | |
207 | ||
208 | client->convert_cb = NULL; | |
209 | return client->result; | |
210 | ||
211 | err: | |
212 | return ret; | |
213 | } | |
d3bf3956 | 214 | EXPORT_SYMBOL_GPL(s3c_adc_read); |
e170adcb BD |
215 | |
216 | static void s3c_adc_default_select(struct s3c_adc_client *client, | |
217 | unsigned select) | |
28ab44c5 BD |
218 | { |
219 | } | |
220 | ||
221 | struct s3c_adc_client *s3c_adc_register(struct platform_device *pdev, | |
e170adcb BD |
222 | void (*select)(struct s3c_adc_client *client, |
223 | unsigned int selected), | |
224 | void (*conv)(struct s3c_adc_client *client, | |
225 | unsigned d0, unsigned d1, | |
3f7ea467 | 226 | unsigned *samples_left), |
28ab44c5 BD |
227 | unsigned int is_ts) |
228 | { | |
229 | struct s3c_adc_client *client; | |
230 | ||
231 | WARN_ON(!pdev); | |
28ab44c5 BD |
232 | |
233 | if (!select) | |
234 | select = s3c_adc_default_select; | |
235 | ||
e170adcb | 236 | if (!pdev) |
28ab44c5 BD |
237 | return ERR_PTR(-EINVAL); |
238 | ||
239 | client = kzalloc(sizeof(struct s3c_adc_client), GFP_KERNEL); | |
240 | if (!client) { | |
241 | dev_err(&pdev->dev, "no memory for adc client\n"); | |
242 | return ERR_PTR(-ENOMEM); | |
243 | } | |
244 | ||
245 | client->pdev = pdev; | |
246 | client->is_ts = is_ts; | |
247 | client->select_cb = select; | |
248 | client->convert_cb = conv; | |
249 | ||
250 | return client; | |
251 | } | |
252 | EXPORT_SYMBOL_GPL(s3c_adc_register); | |
253 | ||
254 | void s3c_adc_release(struct s3c_adc_client *client) | |
255 | { | |
1f1f584c BD |
256 | unsigned long flags; |
257 | ||
258 | spin_lock_irqsave(&adc_dev->lock, flags); | |
259 | ||
28ab44c5 | 260 | /* We should really check that nothing is in progress. */ |
0c3ee078 RL |
261 | if (adc_dev->cur == client) |
262 | adc_dev->cur = NULL; | |
263 | if (adc_dev->ts_pend == client) | |
264 | adc_dev->ts_pend = NULL; | |
265 | else { | |
266 | struct list_head *p, *n; | |
267 | struct s3c_adc_client *tmp; | |
268 | ||
269 | list_for_each_safe(p, n, &adc_pending) { | |
270 | tmp = list_entry(p, struct s3c_adc_client, pend); | |
271 | if (tmp == client) | |
272 | list_del(&tmp->pend); | |
273 | } | |
274 | } | |
275 | ||
276 | if (adc_dev->cur == NULL) | |
277 | s3c_adc_try(adc_dev); | |
1f1f584c BD |
278 | |
279 | spin_unlock_irqrestore(&adc_dev->lock, flags); | |
28ab44c5 BD |
280 | kfree(client); |
281 | } | |
282 | EXPORT_SYMBOL_GPL(s3c_adc_release); | |
283 | ||
284 | static irqreturn_t s3c_adc_irq(int irq, void *pw) | |
285 | { | |
286 | struct adc_device *adc = pw; | |
287 | struct s3c_adc_client *client = adc->cur; | |
91492b4a | 288 | enum s3c_cpu_type cpu = platform_get_device_id(adc->pdev)->driver_data; |
28ab44c5 BD |
289 | unsigned data0, data1; |
290 | ||
291 | if (!client) { | |
292 | dev_warn(&adc->pdev->dev, "%s: no adc pending\n", __func__); | |
bcedfa98 | 293 | goto exit; |
28ab44c5 BD |
294 | } |
295 | ||
296 | data0 = readl(adc->regs + S3C2410_ADCDAT0); | |
297 | data1 = readl(adc->regs + S3C2410_ADCDAT1); | |
298 | adc_dbg(adc, "read %d: 0x%04x, 0x%04x\n", client->nr_samples, data0, data1); | |
299 | ||
3f7ea467 | 300 | client->nr_samples--; |
e170adcb | 301 | |
6247cea2 HS |
302 | if (cpu == TYPE_ADCV1 || cpu == TYPE_ADCV11) { |
303 | data0 &= 0x3ff; | |
304 | data1 &= 0x3ff; | |
305 | } else { | |
35cc3cea | 306 | /* S3C2416/S3C64XX/S5P ADC resolution is 12-bit */ |
91492b4a MC |
307 | data0 &= 0xfff; |
308 | data1 &= 0xfff; | |
91492b4a MC |
309 | } |
310 | ||
e170adcb | 311 | if (client->convert_cb) |
91492b4a | 312 | (client->convert_cb)(client, data0, data1, &client->nr_samples); |
28ab44c5 | 313 | |
3f7ea467 | 314 | if (client->nr_samples > 0) { |
28ab44c5 BD |
315 | /* fire another conversion for this */ |
316 | ||
e170adcb | 317 | client->select_cb(client, 1); |
28ab44c5 BD |
318 | s3c_adc_convert(adc); |
319 | } else { | |
1f1f584c | 320 | spin_lock(&adc->lock); |
e170adcb | 321 | (client->select_cb)(client, 0); |
28ab44c5 BD |
322 | adc->cur = NULL; |
323 | ||
324 | s3c_adc_try(adc); | |
1f1f584c | 325 | spin_unlock(&adc->lock); |
28ab44c5 BD |
326 | } |
327 | ||
bcedfa98 | 328 | exit: |
6247cea2 | 329 | if (cpu == TYPE_ADCV2 || cpu == TYPE_ADCV3) { |
bcedfa98 MC |
330 | /* Clear ADC interrupt */ |
331 | writel(0, adc->regs + S3C64XX_ADCCLRINT); | |
332 | } | |
28ab44c5 BD |
333 | return IRQ_HANDLED; |
334 | } | |
335 | ||
336 | static int s3c_adc_probe(struct platform_device *pdev) | |
337 | { | |
338 | struct device *dev = &pdev->dev; | |
339 | struct adc_device *adc; | |
340 | struct resource *regs; | |
35cc3cea | 341 | enum s3c_cpu_type cpu = platform_get_device_id(pdev)->driver_data; |
28ab44c5 | 342 | int ret; |
91492b4a | 343 | unsigned tmp; |
28ab44c5 BD |
344 | |
345 | adc = kzalloc(sizeof(struct adc_device), GFP_KERNEL); | |
346 | if (adc == NULL) { | |
347 | dev_err(dev, "failed to allocate adc_device\n"); | |
348 | return -ENOMEM; | |
349 | } | |
350 | ||
1f1f584c BD |
351 | spin_lock_init(&adc->lock); |
352 | ||
28ab44c5 BD |
353 | adc->pdev = pdev; |
354 | adc->prescale = S3C2410_ADCCON_PRSCVL(49); | |
355 | ||
f462904e MH |
356 | adc->vdd = regulator_get(dev, "vdd"); |
357 | if (IS_ERR(adc->vdd)) { | |
358 | dev_err(dev, "operating without regulator \"vdd\" .\n"); | |
359 | ret = PTR_ERR(adc->vdd); | |
360 | goto err_alloc; | |
361 | } | |
362 | ||
28ab44c5 BD |
363 | adc->irq = platform_get_irq(pdev, 1); |
364 | if (adc->irq <= 0) { | |
365 | dev_err(dev, "failed to get adc irq\n"); | |
366 | ret = -ENOENT; | |
f462904e | 367 | goto err_reg; |
28ab44c5 BD |
368 | } |
369 | ||
370 | ret = request_irq(adc->irq, s3c_adc_irq, 0, dev_name(dev), adc); | |
371 | if (ret < 0) { | |
372 | dev_err(dev, "failed to attach adc irq\n"); | |
f462904e | 373 | goto err_reg; |
28ab44c5 BD |
374 | } |
375 | ||
376 | adc->clk = clk_get(dev, "adc"); | |
377 | if (IS_ERR(adc->clk)) { | |
378 | dev_err(dev, "failed to get adc clock\n"); | |
379 | ret = PTR_ERR(adc->clk); | |
380 | goto err_irq; | |
381 | } | |
382 | ||
383 | regs = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
384 | if (!regs) { | |
385 | dev_err(dev, "failed to find registers\n"); | |
386 | ret = -ENXIO; | |
387 | goto err_clk; | |
388 | } | |
389 | ||
390 | adc->regs = ioremap(regs->start, resource_size(regs)); | |
391 | if (!adc->regs) { | |
392 | dev_err(dev, "failed to map registers\n"); | |
393 | ret = -ENXIO; | |
394 | goto err_clk; | |
395 | } | |
396 | ||
f462904e MH |
397 | ret = regulator_enable(adc->vdd); |
398 | if (ret) | |
399 | goto err_ioremap; | |
400 | ||
28ab44c5 BD |
401 | clk_enable(adc->clk); |
402 | ||
91492b4a | 403 | tmp = adc->prescale | S3C2410_ADCCON_PRSCEN; |
35cc3cea HS |
404 | |
405 | /* Enable 12-bit ADC resolution */ | |
406 | if (cpu == TYPE_ADCV12) | |
407 | tmp |= S3C2416_ADCCON_RESSEL; | |
408 | if (cpu == TYPE_ADCV2 || cpu == TYPE_ADCV3) | |
91492b4a | 409 | tmp |= S3C64XX_ADCCON_RESSEL; |
35cc3cea | 410 | |
91492b4a | 411 | writel(tmp, adc->regs + S3C2410_ADCCON); |
28ab44c5 BD |
412 | |
413 | dev_info(dev, "attached adc driver\n"); | |
414 | ||
415 | platform_set_drvdata(pdev, adc); | |
416 | adc_dev = adc; | |
417 | ||
418 | return 0; | |
419 | ||
f462904e MH |
420 | err_ioremap: |
421 | iounmap(adc->regs); | |
28ab44c5 BD |
422 | err_clk: |
423 | clk_put(adc->clk); | |
424 | ||
425 | err_irq: | |
426 | free_irq(adc->irq, adc); | |
f462904e MH |
427 | err_reg: |
428 | regulator_put(adc->vdd); | |
28ab44c5 BD |
429 | err_alloc: |
430 | kfree(adc); | |
431 | return ret; | |
432 | } | |
433 | ||
ad4e22fa | 434 | static int __devexit s3c_adc_remove(struct platform_device *pdev) |
28ab44c5 BD |
435 | { |
436 | struct adc_device *adc = platform_get_drvdata(pdev); | |
437 | ||
438 | iounmap(adc->regs); | |
439 | free_irq(adc->irq, adc); | |
440 | clk_disable(adc->clk); | |
f462904e MH |
441 | regulator_disable(adc->vdd); |
442 | regulator_put(adc->vdd); | |
28ab44c5 BD |
443 | clk_put(adc->clk); |
444 | kfree(adc); | |
445 | ||
446 | return 0; | |
447 | } | |
448 | ||
449 | #ifdef CONFIG_PM | |
67dcaec8 | 450 | static int s3c_adc_suspend(struct device *dev) |
28ab44c5 | 451 | { |
67dcaec8 MH |
452 | struct platform_device *pdev = container_of(dev, |
453 | struct platform_device, dev); | |
28ab44c5 | 454 | struct adc_device *adc = platform_get_drvdata(pdev); |
1f1f584c | 455 | unsigned long flags; |
28ab44c5 BD |
456 | u32 con; |
457 | ||
1f1f584c BD |
458 | spin_lock_irqsave(&adc->lock, flags); |
459 | ||
28ab44c5 BD |
460 | con = readl(adc->regs + S3C2410_ADCCON); |
461 | con |= S3C2410_ADCCON_STDBM; | |
462 | writel(con, adc->regs + S3C2410_ADCCON); | |
463 | ||
a0af8b3c | 464 | disable_irq(adc->irq); |
1f1f584c | 465 | spin_unlock_irqrestore(&adc->lock, flags); |
28ab44c5 | 466 | clk_disable(adc->clk); |
f462904e | 467 | regulator_disable(adc->vdd); |
28ab44c5 BD |
468 | |
469 | return 0; | |
470 | } | |
471 | ||
67dcaec8 | 472 | static int s3c_adc_resume(struct device *dev) |
28ab44c5 | 473 | { |
67dcaec8 MH |
474 | struct platform_device *pdev = container_of(dev, |
475 | struct platform_device, dev); | |
28ab44c5 | 476 | struct adc_device *adc = platform_get_drvdata(pdev); |
35cc3cea | 477 | enum s3c_cpu_type cpu = platform_get_device_id(pdev)->driver_data; |
f462904e | 478 | int ret; |
67dcaec8 | 479 | unsigned long tmp; |
28ab44c5 | 480 | |
f462904e MH |
481 | ret = regulator_enable(adc->vdd); |
482 | if (ret) | |
483 | return ret; | |
28ab44c5 | 484 | clk_enable(adc->clk); |
a0af8b3c | 485 | enable_irq(adc->irq); |
28ab44c5 | 486 | |
67dcaec8 | 487 | tmp = adc->prescale | S3C2410_ADCCON_PRSCEN; |
35cc3cea | 488 | |
67dcaec8 | 489 | /* Enable 12-bit ADC resolution */ |
35cc3cea HS |
490 | if (cpu == TYPE_ADCV12) |
491 | tmp |= S3C2416_ADCCON_RESSEL; | |
492 | if (cpu == TYPE_ADCV2 || cpu == TYPE_ADCV3) | |
67dcaec8 | 493 | tmp |= S3C64XX_ADCCON_RESSEL; |
35cc3cea | 494 | |
67dcaec8 | 495 | writel(tmp, adc->regs + S3C2410_ADCCON); |
28ab44c5 BD |
496 | |
497 | return 0; | |
498 | } | |
499 | ||
500 | #else | |
501 | #define s3c_adc_suspend NULL | |
502 | #define s3c_adc_resume NULL | |
503 | #endif | |
504 | ||
bcedfa98 MC |
505 | static struct platform_device_id s3c_adc_driver_ids[] = { |
506 | { | |
507 | .name = "s3c24xx-adc", | |
64df92ea | 508 | .driver_data = TYPE_ADCV1, |
6247cea2 HS |
509 | }, { |
510 | .name = "s3c2443-adc", | |
511 | .driver_data = TYPE_ADCV11, | |
35cc3cea HS |
512 | }, { |
513 | .name = "s3c2416-adc", | |
514 | .driver_data = TYPE_ADCV12, | |
bcedfa98 MC |
515 | }, { |
516 | .name = "s3c64xx-adc", | |
64df92ea MH |
517 | .driver_data = TYPE_ADCV2, |
518 | }, { | |
519 | .name = "samsung-adc-v3", | |
520 | .driver_data = TYPE_ADCV3, | |
bcedfa98 MC |
521 | }, |
522 | { } | |
523 | }; | |
524 | MODULE_DEVICE_TABLE(platform, s3c_adc_driver_ids); | |
525 | ||
67dcaec8 MH |
526 | static const struct dev_pm_ops adc_pm_ops = { |
527 | .suspend = s3c_adc_suspend, | |
528 | .resume = s3c_adc_resume, | |
529 | }; | |
530 | ||
28ab44c5 | 531 | static struct platform_driver s3c_adc_driver = { |
bcedfa98 | 532 | .id_table = s3c_adc_driver_ids, |
28ab44c5 | 533 | .driver = { |
bcedfa98 | 534 | .name = "s3c-adc", |
28ab44c5 | 535 | .owner = THIS_MODULE, |
67dcaec8 | 536 | .pm = &adc_pm_ops, |
28ab44c5 BD |
537 | }, |
538 | .probe = s3c_adc_probe, | |
539 | .remove = __devexit_p(s3c_adc_remove), | |
28ab44c5 BD |
540 | }; |
541 | ||
542 | static int __init adc_init(void) | |
543 | { | |
544 | int ret; | |
545 | ||
546 | ret = platform_driver_register(&s3c_adc_driver); | |
547 | if (ret) | |
548 | printk(KERN_ERR "%s: failed to add adc driver\n", __func__); | |
549 | ||
550 | return ret; | |
551 | } | |
552 | ||
f462904e | 553 | module_init(adc_init); |