[deliverable/linux.git] / arch / arm / plat-samsung / clock.c

/* linux/arch/arm/plat-s3c24xx/clock.c
 *
 * Copyright 2004-2005 Simtec Electronics
 *	Ben Dooks <ben@simtec.co.uk>
 *
 * S3C24XX Core clock control support
 *
 * Based on, and code from linux/arch/arm/mach-versatile/clock.c
 **
 **  Copyright (C) 2004 ARM Limited.
 **  Written by Deep Blue Solutions Limited.
 *
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
*/

#include <linux/init.h>
#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/list.h>
#include <linux/errno.h>
#include <linux/err.h>
#include <linux/platform_device.h>
#include <linux/sysdev.h>
#include <linux/interrupt.h>
#include <linux/ioport.h>
#include <linux/clk.h>
#include <linux/spinlock.h>
#include <linux/io.h>
#if defined(CONFIG_DEBUG_FS)
#include <linux/debugfs.h>
#endif

#include <mach/hardware.h>
#include <asm/irq.h>

#include <plat/cpu-freq.h>

#include <plat/clock.h>
#include <plat/cpu.h>

#include <linux/serial_core.h>
#include <plat/regs-serial.h> /* for s3c24xx_uart_devs */

/* clock information */

static LIST_HEAD(clocks);

/* We originally used an mutex here, but some contexts (see resume)
 * are calling functions such as clk_set_parent() with IRQs disabled
 * causing an BUG to be triggered.
 */
DEFINE_SPINLOCK(clocks_lock);

/* Global watchdog clock used by arch_wtd_reset() callback */
struct clk *s3c2410_wdtclk;
static int __init s3c_wdt_reset_init(void)
{
	s3c2410_wdtclk = clk_get(NULL, "watchdog");
	if (IS_ERR(s3c2410_wdtclk))
		printk(KERN_WARNING "%s: warning: cannot get watchdog clock\n", __func__);
	return 0;
}
arch_initcall(s3c_wdt_reset_init);

/* enable and disable calls for use with the clk struct */

static int clk_null_enable(struct clk *clk, int enable)
{
	return 0;
}

int clk_enable(struct clk *clk)
{
	if (IS_ERR(clk) || clk == NULL)
		return -EINVAL;

	clk_enable(clk->parent);

	spin_lock(&clocks_lock);

	if ((clk->usage++) == 0)
		(clk->enable)(clk, 1);

	spin_unlock(&clocks_lock);
	return 0;
}

void clk_disable(struct clk *clk)
{
	if (IS_ERR(clk) || clk == NULL)
		return;

	spin_lock(&clocks_lock);

	if ((--clk->usage) == 0)
		(clk->enable)(clk, 0);

	spin_unlock(&clocks_lock);
	clk_disable(clk->parent);
}


unsigned long clk_get_rate(struct clk *clk)
{
	if (IS_ERR(clk))
		return 0;

	if (clk->rate != 0)
		return clk->rate;

	if (clk->ops != NULL && clk->ops->get_rate != NULL)
		return (clk->ops->get_rate)(clk);

	if (clk->parent != NULL)
		return clk_get_rate(clk->parent);

	return clk->rate;
}

long clk_round_rate(struct clk *clk, unsigned long rate)
{
	if (!IS_ERR(clk) && clk->ops && clk->ops->round_rate)
		return (clk->ops->round_rate)(clk, rate);

	return rate;
}

int clk_set_rate(struct clk *clk, unsigned long rate)
{
	int ret;

	if (IS_ERR(clk))
		return -EINVAL;

	/* We do not default just do a clk->rate = rate as
	 * the clock may have been made this way by choice.
	 */

	WARN_ON(clk->ops == NULL);
	WARN_ON(clk->ops && clk->ops->set_rate == NULL);

	if (clk->ops == NULL || clk->ops->set_rate == NULL)
		return -EINVAL;

	spin_lock(&clocks_lock);
	ret = (clk->ops->set_rate)(clk, rate);
	spin_unlock(&clocks_lock);

	return ret;
}

struct clk *clk_get_parent(struct clk *clk)
{
	return clk->parent;
}

int clk_set_parent(struct clk *clk, struct clk *parent)
{
	int ret = 0;

	if (IS_ERR(clk))
		return -EINVAL;

	spin_lock(&clocks_lock);

	if (clk->ops && clk->ops->set_parent)
		ret = (clk->ops->set_parent)(clk, parent);

	spin_unlock(&clocks_lock);

	return ret;
}

EXPORT_SYMBOL(clk_enable);
EXPORT_SYMBOL(clk_disable);
EXPORT_SYMBOL(clk_get_rate);
EXPORT_SYMBOL(clk_round_rate);
EXPORT_SYMBOL(clk_set_rate);
EXPORT_SYMBOL(clk_get_parent);
EXPORT_SYMBOL(clk_set_parent);

/* base clocks */

int clk_default_setrate(struct clk *clk, unsigned long rate)
{
	clk->rate = rate;
	return 0;
}

struct clk_ops clk_ops_def_setrate = {
	.set_rate	= clk_default_setrate,
};

struct clk clk_xtal = {
	.name		= "xtal",
	.rate		= 0,
	.parent		= NULL,
	.ctrlbit	= 0,
};

struct clk clk_ext = {
	.name		= "ext",
};

struct clk clk_epll = {
	.name		= "epll",
};

struct clk clk_mpll = {
	.name		= "mpll",
	.ops		= &clk_ops_def_setrate,
};

struct clk clk_upll = {
	.name		= "upll",
	.parent		= NULL,
	.ctrlbit	= 0,
};

struct clk clk_f = {
	.name		= "fclk",
	.rate		= 0,
	.parent		= &clk_mpll,
	.ctrlbit	= 0,
};

struct clk clk_h = {
	.name		= "hclk",
	.rate		= 0,
	.parent		= NULL,
	.ctrlbit	= 0,
	.ops		= &clk_ops_def_setrate,
};

struct clk clk_p = {
	.name		= "pclk",
	.rate		= 0,
	.parent		= NULL,
	.ctrlbit	= 0,
	.ops		= &clk_ops_def_setrate,
};

struct clk clk_usb_bus = {
	.name		= "usb-bus",
	.rate		= 0,
	.parent		= &clk_upll,
};


struct clk s3c24xx_uclk = {
	.name		= "uclk",
};

/* initialise the clock system */

/**
 * s3c24xx_register_clock() - register a clock
 * @clk: The clock to register
 *
 * Add the specified clock to the list of clocks known by the system.
 */
int s3c24xx_register_clock(struct clk *clk)
{
	if (clk->enable == NULL)
		clk->enable = clk_null_enable;

	/* fill up the clk_lookup structure and register it*/
	clk->lookup.dev_id = clk->devname;
	clk->lookup.con_id = clk->name;
	clk->lookup.clk = clk;
	clkdev_add(&clk->lookup);

	return 0;
}

/**
 * s3c24xx_register_clocks() - register an array of clock pointers
 * @clks: Pointer to an array of struct clk pointers
 * @nr_clks: The number of clocks in the @clks array.
 *
 * Call s3c24xx_register_clock() for all the clock pointers contained
 * in the @clks list. Returns the number of failures.
 */
int s3c24xx_register_clocks(struct clk **clks, int nr_clks)
{
	int fails = 0;

	for (; nr_clks > 0; nr_clks--, clks++) {
		if (s3c24xx_register_clock(*clks) < 0) {
			struct clk *clk = *clks;
			printk(KERN_ERR "%s: failed to register %p: %s\n",
			       __func__, clk, clk->name);
			fails++;
		}
	}

	return fails;
}

/**
 * s3c_register_clocks() - register an array of clocks
 * @clkp: Pointer to the first clock in the array.
 * @nr_clks: Number of clocks to register.
 *
 * Call s3c24xx_register_clock() on the @clkp array given, printing an
 * error if it fails to register the clock (unlikely).
 */
void __init s3c_register_clocks(struct clk *clkp, int nr_clks)
{
	int ret;

	for (; nr_clks > 0; nr_clks--, clkp++) {
		ret = s3c24xx_register_clock(clkp);

		if (ret < 0) {
			printk(KERN_ERR "Failed to register clock %s (%d)\n",
			       clkp->name, ret);
		}
	}
}

/**
 * s3c_disable_clocks() - disable an array of clocks
 * @clkp: Pointer to the first clock in the array.
 * @nr_clks: Number of clocks to register.
 *
 * for internal use only at initialisation time. disable the clocks in the
 * @clkp array.
 */

void __init s3c_disable_clocks(struct clk *clkp, int nr_clks)
{
	for (; nr_clks > 0; nr_clks--, clkp++)
		(clkp->enable)(clkp, 0);
}

/* initialise all the clocks */

int __init s3c24xx_register_baseclocks(unsigned long xtal)
{
	printk(KERN_INFO "S3C24XX Clocks, Copyright 2004 Simtec Electronics\n");

	clk_xtal.rate = xtal;

	/* register our clocks */

	if (s3c24xx_register_clock(&clk_xtal) < 0)
		printk(KERN_ERR "failed to register master xtal\n");

	if (s3c24xx_register_clock(&clk_mpll) < 0)
		printk(KERN_ERR "failed to register mpll clock\n");

	if (s3c24xx_register_clock(&clk_upll) < 0)
		printk(KERN_ERR "failed to register upll clock\n");

	if (s3c24xx_register_clock(&clk_f) < 0)
		printk(KERN_ERR "failed to register cpu fclk\n");

	if (s3c24xx_register_clock(&clk_h) < 0)
		printk(KERN_ERR "failed to register cpu hclk\n");

	if (s3c24xx_register_clock(&clk_p) < 0)
		printk(KERN_ERR "failed to register cpu pclk\n");

	return 0;
}

#if defined(CONFIG_PM_DEBUG) && defined(CONFIG_DEBUG_FS)
/* debugfs support to trace clock tree hierarchy and attributes */

static struct dentry *clk_debugfs_root;

static int clk_debugfs_register_one(struct clk *c)
{
	int err;
	struct dentry *d;
	struct clk *pa = c->parent;
	char s[255];
	char *p = s;

	p += sprintf(p, "%s", c->devname);

	d = debugfs_create_dir(s, pa ? pa->dent : clk_debugfs_root);
	if (!d)
		return -ENOMEM;

	c->dent = d;

	d = debugfs_create_u8("usecount", S_IRUGO, c->dent, (u8 *)&c->usage);
	if (!d) {
		err = -ENOMEM;
		goto err_out;
	}

	d = debugfs_create_u32("rate", S_IRUGO, c->dent, (u32 *)&c->rate);
	if (!d) {
		err = -ENOMEM;
		goto err_out;
	}
	return 0;

err_out:
	debugfs_remove_recursive(c->dent);
	return err;
}

static int clk_debugfs_register(struct clk *c)
{
	int err;
	struct clk *pa = c->parent;

	if (pa && !pa->dent) {
		err = clk_debugfs_register(pa);
		if (err)
			return err;
	}

	if (!c->dent) {
		err = clk_debugfs_register_one(c);
		if (err)
			return err;
	}
	return 0;
}

static int __init clk_debugfs_init(void)
{
	struct clk *c;
	struct dentry *d;
	int err;

	d = debugfs_create_dir("clock", NULL);
	if (!d)
		return -ENOMEM;
	clk_debugfs_root = d;

	list_for_each_entry(c, &clocks, list) {
		err = clk_debugfs_register(c);
		if (err)
			goto err_out;
	}
	return 0;

err_out:
	debugfs_remove_recursive(clk_debugfs_root);
	return err;
}
late_initcall(clk_debugfs_init);

#endif /* defined(CONFIG_PM_DEBUG) && defined(CONFIG_DEBUG_FS) */
Commit	Line	Data
adbefaa5 BD	1	/* linux/arch/arm/plat-s3c24xx/clock.c
adbefaa5 BD	2	*
50f430e3	3	* Copyright 2004-2005 Simtec Electronics
adbefaa5 BD	4	* Ben Dooks <ben@simtec.co.uk>
	5	*
	6	* S3C24XX Core clock control support
	7	*
	8	* Based on, and code from linux/arch/arm/mach-versatile/clock.c
	9	**
	10	** Copyright (C) 2004 ARM Limited.
	11	** Written by Deep Blue Solutions Limited.
	12	*
	13	*
	14	* This program is free software; you can redistribute it and/or modify
	15	* it under the terms of the GNU General Public License as published by
	16	* the Free Software Foundation; either version 2 of the License, or
	17	* (at your option) any later version.
	18	*
	19	* This program is distributed in the hope that it will be useful,
	20	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	21	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	22	* GNU General Public License for more details.
	23	*
	24	* You should have received a copy of the GNU General Public License
	25	* along with this program; if not, write to the Free Software
	26	* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
	27	*/
	28
	29	#include <linux/init.h>
	30	#include <linux/module.h>
	31	#include <linux/kernel.h>
	32	#include <linux/list.h>
	33	#include <linux/errno.h>
	34	#include <linux/err.h>
	35	#include <linux/platform_device.h>
	36	#include <linux/sysdev.h>
	37	#include <linux/interrupt.h>
	38	#include <linux/ioport.h>
	39	#include <linux/clk.h>
	40	#include <linux/spinlock.h>
adbefaa5	41	#include <linux/io.h>
436c3878 ADK	42	#if defined(CONFIG_DEBUG_FS)
	43	#include <linux/debugfs.h>
	44	#endif
adbefaa5 BD	45
	46	#include <mach/hardware.h>
	47	#include <asm/irq.h>
	48
	49	#include <plat/cpu-freq.h>
	50
	51	#include <plat/clock.h>
	52	#include <plat/cpu.h>
	53
7cf4b482 MS	54	#include <linux/serial_core.h>
	55	#include <plat/regs-serial.h> /* for s3c24xx_uart_devs */
	56
adbefaa5 BD	57	/* clock information */
	58
	59	static LIST_HEAD(clocks);
	60
	61	/* We originally used an mutex here, but some contexts (see resume)
	62	* are calling functions such as clk_set_parent() with IRQs disabled
	63	* causing an BUG to be triggered.
	64	*/
	65	DEFINE_SPINLOCK(clocks_lock);
	66
caf27307 MS	67	/* Global watchdog clock used by arch_wtd_reset() callback */
	68	struct clk *s3c2410_wdtclk;
	69	static int __init s3c_wdt_reset_init(void)
	70	{
	71	s3c2410_wdtclk = clk_get(NULL, "watchdog");
	72	if (IS_ERR(s3c2410_wdtclk))
	73	printk(KERN_WARNING "%s: warning: cannot get watchdog clock\n", __func__);
	74	return 0;
	75	}
	76	arch_initcall(s3c_wdt_reset_init);
	77
adbefaa5 BD	78	/* enable and disable calls for use with the clk struct */
	79
	80	static int clk_null_enable(struct clk *clk, int enable)
	81	{
	82	return 0;
	83	}
	84
adbefaa5 BD	85	int clk_enable(struct clk *clk)
	86	{
	87	if (IS_ERR(clk) \|\| clk == NULL)
	88	return -EINVAL;
	89
	90	clk_enable(clk->parent);
	91
	92	spin_lock(&clocks_lock);
	93
	94	if ((clk->usage++) == 0)
	95	(clk->enable)(clk, 1);
	96
	97	spin_unlock(&clocks_lock);
	98	return 0;
	99	}
	100
	101	void clk_disable(struct clk *clk)
	102	{
	103	if (IS_ERR(clk) \|\| clk == NULL)
	104	return;
	105
	106	spin_lock(&clocks_lock);
	107
	108	if ((--clk->usage) == 0)
	109	(clk->enable)(clk, 0);
	110
	111	spin_unlock(&clocks_lock);
	112	clk_disable(clk->parent);
	113	}
	114
	115
	116	unsigned long clk_get_rate(struct clk *clk)
	117	{
	118	if (IS_ERR(clk))
	119	return 0;
	120
	121	if (clk->rate != 0)
	122	return clk->rate;
	123
b3bf41be BD	124	if (clk->ops != NULL && clk->ops->get_rate != NULL)
b3bf41be BD	125	return (clk->ops->get_rate)(clk);
adbefaa5 BD	126
	127	if (clk->parent != NULL)
	128	return clk_get_rate(clk->parent);
	129
	130	return clk->rate;
	131	}
	132
	133	long clk_round_rate(struct clk *clk, unsigned long rate)
	134	{
b3bf41be BD	135	if (!IS_ERR(clk) && clk->ops && clk->ops->round_rate)
b3bf41be BD	136	return (clk->ops->round_rate)(clk, rate);
adbefaa5 BD	137
	138	return rate;
	139	}
	140
	141	int clk_set_rate(struct clk *clk, unsigned long rate)
	142	{
	143	int ret;
	144
	145	if (IS_ERR(clk))
	146	return -EINVAL;
	147
	148	/* We do not default just do a clk->rate = rate as
	149	* the clock may have been made this way by choice.
	150	*/
	151
b3bf41be BD	152	WARN_ON(clk->ops == NULL);
b3bf41be BD	153	WARN_ON(clk->ops && clk->ops->set_rate == NULL);
adbefaa5	154
b3bf41be	155	if (clk->ops == NULL \|\| clk->ops->set_rate == NULL)
adbefaa5 BD	156	return -EINVAL;
	157
	158	spin_lock(&clocks_lock);
b3bf41be	159	ret = (clk->ops->set_rate)(clk, rate);
adbefaa5 BD	160	spin_unlock(&clocks_lock);
	161
	162	return ret;
	163	}
	164
	165	struct clk clk_get_parent(struct clk clk)
	166	{
	167	return clk->parent;
	168	}
	169
	170	int clk_set_parent(struct clk clk, struct clk parent)
	171	{
	172	int ret = 0;
	173
	174	if (IS_ERR(clk))
	175	return -EINVAL;
	176
	177	spin_lock(&clocks_lock);
	178
b3bf41be BD	179	if (clk->ops && clk->ops->set_parent)
b3bf41be BD	180	ret = (clk->ops->set_parent)(clk, parent);
adbefaa5 BD	181
	182	spin_unlock(&clocks_lock);
	183
	184	return ret;
	185	}
	186
adbefaa5 BD	187	EXPORT_SYMBOL(clk_enable);
	188	EXPORT_SYMBOL(clk_disable);
	189	EXPORT_SYMBOL(clk_get_rate);
	190	EXPORT_SYMBOL(clk_round_rate);
	191	EXPORT_SYMBOL(clk_set_rate);
	192	EXPORT_SYMBOL(clk_get_parent);
	193	EXPORT_SYMBOL(clk_set_parent);
	194
	195	/* base clocks */
	196
ed276849	197	int clk_default_setrate(struct clk *clk, unsigned long rate)
adbefaa5 BD	198	{
	199	clk->rate = rate;
	200	return 0;
	201	}
	202
ed276849	203	struct clk_ops clk_ops_def_setrate = {
b3bf41be BD	204	.set_rate = clk_default_setrate,
	205	};
	206
adbefaa5 BD	207	struct clk clk_xtal = {
adbefaa5 BD	208	.name = "xtal",
adbefaa5 BD	209	.rate = 0,
	210	.parent = NULL,
	211	.ctrlbit = 0,
	212	};
	213
4b31d8b2 BD	214	struct clk clk_ext = {
4b31d8b2 BD	215	.name = "ext",
4b31d8b2 BD	216	};
	217
	218	struct clk clk_epll = {
	219	.name = "epll",
4b31d8b2 BD	220	};
4b31d8b2 BD	221
adbefaa5 BD	222	struct clk clk_mpll = {
adbefaa5 BD	223	.name = "mpll",
b3bf41be	224	.ops = &clk_ops_def_setrate,
adbefaa5 BD	225	};
	226
	227	struct clk clk_upll = {
	228	.name = "upll",
adbefaa5 BD	229	.parent = NULL,
	230	.ctrlbit = 0,
	231	};
	232
	233	struct clk clk_f = {
	234	.name = "fclk",
adbefaa5 BD	235	.rate = 0,
	236	.parent = &clk_mpll,
	237	.ctrlbit = 0,
adbefaa5 BD	238	};
	239
	240	struct clk clk_h = {
	241	.name = "hclk",
adbefaa5 BD	242	.rate = 0,
	243	.parent = NULL,
	244	.ctrlbit = 0,
b3bf41be	245	.ops = &clk_ops_def_setrate,
adbefaa5 BD	246	};
	247
	248	struct clk clk_p = {
	249	.name = "pclk",
adbefaa5 BD	250	.rate = 0,
	251	.parent = NULL,
	252	.ctrlbit = 0,
b3bf41be	253	.ops = &clk_ops_def_setrate,
adbefaa5 BD	254	};
	255
	256	struct clk clk_usb_bus = {
	257	.name = "usb-bus",
adbefaa5 BD	258	.rate = 0,
	259	.parent = &clk_upll,
	260	};
	261
	262
adbefaa5 BD	263	struct clk s3c24xx_uclk = {
adbefaa5 BD	264	.name = "uclk",
adbefaa5 BD	265	};
	266
	267	/* initialise the clock system */
	268
8428d47a BD	269	/**
	270	* s3c24xx_register_clock() - register a clock
	271	* @clk: The clock to register
	272	*
	273	* Add the specified clock to the list of clocks known by the system.
	274	*/
adbefaa5 BD	275	int s3c24xx_register_clock(struct clk *clk)
adbefaa5 BD	276	{
adbefaa5 BD	277	if (clk->enable == NULL)
	278	clk->enable = clk_null_enable;
	279
f86c6660 TA	280	/* fill up the clk_lookup structure and register it*/
	281	clk->lookup.dev_id = clk->devname;
	282	clk->lookup.con_id = clk->name;
	283	clk->lookup.clk = clk;
	284	clkdev_add(&clk->lookup);
adbefaa5 BD	285
	286	return 0;
	287	}
	288
8428d47a BD	289	/**
	290	* s3c24xx_register_clocks() - register an array of clock pointers
	291	* @clks: Pointer to an array of struct clk pointers
	292	* @nr_clks: The number of clocks in the @clks array.
	293	*
	294	* Call s3c24xx_register_clock() for all the clock pointers contained
	295	* in the @clks list. Returns the number of failures.
	296	*/
adbefaa5 BD	297	int s3c24xx_register_clocks(struct clk **clks, int nr_clks)
	298	{
	299	int fails = 0;
	300
	301	for (; nr_clks > 0; nr_clks--, clks++) {
50ee2d35 BD	302	if (s3c24xx_register_clock(*clks) < 0) {
	303	struct clk clk = clks;
	304	printk(KERN_ERR "%s: failed to register %p: %s\n",
	305	__func__, clk, clk->name);
adbefaa5	306	fails++;
50ee2d35	307	}
adbefaa5 BD	308	}
	309
	310	return fails;
	311	}
	312
1d9f13c4 BD	313	/**
	314	* s3c_register_clocks() - register an array of clocks
	315	* @clkp: Pointer to the first clock in the array.
	316	* @nr_clks: Number of clocks to register.
	317	*
	318	* Call s3c24xx_register_clock() on the @clkp array given, printing an
	319	* error if it fails to register the clock (unlikely).
	320	*/
ab5d97db	321	void __init s3c_register_clocks(struct clk *clkp, int nr_clks)
1d9f13c4 BD	322	{
	323	int ret;
	324
	325	for (; nr_clks > 0; nr_clks--, clkp++) {
	326	ret = s3c24xx_register_clock(clkp);
	327
	328	if (ret < 0) {
	329	printk(KERN_ERR "Failed to register clock %s (%d)\n",
	330	clkp->name, ret);
	331	}
	332	}
	333	}
	334
4e04691b BD	335	/**
	336	* s3c_disable_clocks() - disable an array of clocks
	337	* @clkp: Pointer to the first clock in the array.
	338	* @nr_clks: Number of clocks to register.
	339	*
	340	* for internal use only at initialisation time. disable the clocks in the
	341	* @clkp array.
	342	*/
	343
	344	void __init s3c_disable_clocks(struct clk *clkp, int nr_clks)
	345	{
	346	for (; nr_clks > 0; nr_clks--, clkp++)
	347	(clkp->enable)(clkp, 0);
	348	}
	349
421f91d2	350	/* initialise all the clocks */
adbefaa5 BD	351
	352	int __init s3c24xx_register_baseclocks(unsigned long xtal)
	353	{
50f430e3	354	printk(KERN_INFO "S3C24XX Clocks, Copyright 2004 Simtec Electronics\n");
adbefaa5 BD	355
	356	clk_xtal.rate = xtal;
	357
	358	/* register our clocks */
	359
	360	if (s3c24xx_register_clock(&clk_xtal) < 0)
	361	printk(KERN_ERR "failed to register master xtal\n");
	362
	363	if (s3c24xx_register_clock(&clk_mpll) < 0)
	364	printk(KERN_ERR "failed to register mpll clock\n");
	365
	366	if (s3c24xx_register_clock(&clk_upll) < 0)
	367	printk(KERN_ERR "failed to register upll clock\n");
	368
	369	if (s3c24xx_register_clock(&clk_f) < 0)
	370	printk(KERN_ERR "failed to register cpu fclk\n");
	371
	372	if (s3c24xx_register_clock(&clk_h) < 0)
	373	printk(KERN_ERR "failed to register cpu hclk\n");
	374
	375	if (s3c24xx_register_clock(&clk_p) < 0)
	376	printk(KERN_ERR "failed to register cpu pclk\n");
	377
	378	return 0;
	379	}
	380
436c3878 ADK	381	#if defined(CONFIG_PM_DEBUG) && defined(CONFIG_DEBUG_FS)
	382	/* debugfs support to trace clock tree hierarchy and attributes */
	383
	384	static struct dentry *clk_debugfs_root;
	385
	386	static int clk_debugfs_register_one(struct clk *c)
	387	{
	388	int err;
12520c43	389	struct dentry *d;
436c3878 ADK	390	struct clk *pa = c->parent;
	391	char s[255];
	392	char *p = s;
	393
f86c6660	394	p += sprintf(p, "%s", c->devname);
436c3878 ADK	395
	396	d = debugfs_create_dir(s, pa ? pa->dent : clk_debugfs_root);
	397	if (!d)
	398	return -ENOMEM;
	399
	400	c->dent = d;
	401
	402	d = debugfs_create_u8("usecount", S_IRUGO, c->dent, (u8 *)&c->usage);
	403	if (!d) {
	404	err = -ENOMEM;
	405	goto err_out;
	406	}
	407
	408	d = debugfs_create_u32("rate", S_IRUGO, c->dent, (u32 *)&c->rate);
	409	if (!d) {
	410	err = -ENOMEM;
	411	goto err_out;
	412	}
	413	return 0;
	414
	415	err_out:
12520c43	416	debugfs_remove_recursive(c->dent);
436c3878 ADK	417	return err;
	418	}
	419
	420	static int clk_debugfs_register(struct clk *c)
	421	{
	422	int err;
	423	struct clk *pa = c->parent;
	424
	425	if (pa && !pa->dent) {
	426	err = clk_debugfs_register(pa);
	427	if (err)
	428	return err;
	429	}
	430
	431	if (!c->dent) {
	432	err = clk_debugfs_register_one(c);
	433	if (err)
	434	return err;
	435	}
	436	return 0;
	437	}
	438
	439	static int __init clk_debugfs_init(void)
	440	{
	441	struct clk *c;
	442	struct dentry *d;
	443	int err;
	444
	445	d = debugfs_create_dir("clock", NULL);
	446	if (!d)
	447	return -ENOMEM;
	448	clk_debugfs_root = d;
	449
	450	list_for_each_entry(c, &clocks, list) {
	451	err = clk_debugfs_register(c);
	452	if (err)
	453	goto err_out;
	454	}
	455	return 0;
	456
	457	err_out:
	458	debugfs_remove_recursive(clk_debugfs_root);
	459	return err;
	460	}
	461	late_initcall(clk_debugfs_init);
	462
	463	#endif /* defined(CONFIG_PM_DEBUG) && defined(CONFIG_DEBUG_FS) */