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adbefaa5 BD |
1 | /* linux/arch/arm/plat-s3c24xx/clock.c |
2 | * | |
50f430e3 | 3 | * Copyright 2004-2005 Simtec Electronics |
adbefaa5 BD |
4 | * Ben Dooks <ben@simtec.co.uk> |
5 | * | |
6 | * S3C24XX Core clock control support | |
7 | * | |
8 | * Based on, and code from linux/arch/arm/mach-versatile/clock.c | |
9 | ** | |
10 | ** Copyright (C) 2004 ARM Limited. | |
11 | ** Written by Deep Blue Solutions Limited. | |
12 | * | |
13 | * | |
14 | * This program is free software; you can redistribute it and/or modify | |
15 | * it under the terms of the GNU General Public License as published by | |
16 | * the Free Software Foundation; either version 2 of the License, or | |
17 | * (at your option) any later version. | |
18 | * | |
19 | * This program is distributed in the hope that it will be useful, | |
20 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
21 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
22 | * GNU General Public License for more details. | |
23 | * | |
24 | * You should have received a copy of the GNU General Public License | |
25 | * along with this program; if not, write to the Free Software | |
26 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
27 | */ | |
28 | ||
29 | #include <linux/init.h> | |
30 | #include <linux/module.h> | |
31 | #include <linux/kernel.h> | |
32 | #include <linux/list.h> | |
33 | #include <linux/errno.h> | |
34 | #include <linux/err.h> | |
35 | #include <linux/platform_device.h> | |
edbaa603 | 36 | #include <linux/device.h> |
adbefaa5 BD |
37 | #include <linux/interrupt.h> |
38 | #include <linux/ioport.h> | |
39 | #include <linux/clk.h> | |
40 | #include <linux/spinlock.h> | |
adbefaa5 | 41 | #include <linux/io.h> |
436c3878 ADK |
42 | #if defined(CONFIG_DEBUG_FS) |
43 | #include <linux/debugfs.h> | |
44 | #endif | |
adbefaa5 BD |
45 | |
46 | #include <mach/hardware.h> | |
47 | #include <asm/irq.h> | |
48 | ||
49 | #include <plat/cpu-freq.h> | |
50 | ||
51 | #include <plat/clock.h> | |
52 | #include <plat/cpu.h> | |
53 | ||
7cf4b482 MS |
54 | #include <linux/serial_core.h> |
55 | #include <plat/regs-serial.h> /* for s3c24xx_uart_devs */ | |
56 | ||
adbefaa5 BD |
57 | /* clock information */ |
58 | ||
59 | static LIST_HEAD(clocks); | |
60 | ||
61 | /* We originally used an mutex here, but some contexts (see resume) | |
62 | * are calling functions such as clk_set_parent() with IRQs disabled | |
63 | * causing an BUG to be triggered. | |
64 | */ | |
65 | DEFINE_SPINLOCK(clocks_lock); | |
66 | ||
caf27307 MS |
67 | /* Global watchdog clock used by arch_wtd_reset() callback */ |
68 | struct clk *s3c2410_wdtclk; | |
69 | static int __init s3c_wdt_reset_init(void) | |
70 | { | |
71 | s3c2410_wdtclk = clk_get(NULL, "watchdog"); | |
72 | if (IS_ERR(s3c2410_wdtclk)) | |
73 | printk(KERN_WARNING "%s: warning: cannot get watchdog clock\n", __func__); | |
74 | return 0; | |
75 | } | |
76 | arch_initcall(s3c_wdt_reset_init); | |
77 | ||
adbefaa5 BD |
78 | /* enable and disable calls for use with the clk struct */ |
79 | ||
80 | static int clk_null_enable(struct clk *clk, int enable) | |
81 | { | |
82 | return 0; | |
83 | } | |
84 | ||
adbefaa5 BD |
85 | int clk_enable(struct clk *clk) |
86 | { | |
0cdf3aff MB |
87 | unsigned long flags; |
88 | ||
adbefaa5 BD |
89 | if (IS_ERR(clk) || clk == NULL) |
90 | return -EINVAL; | |
91 | ||
92 | clk_enable(clk->parent); | |
93 | ||
0cdf3aff | 94 | spin_lock_irqsave(&clocks_lock, flags); |
adbefaa5 BD |
95 | |
96 | if ((clk->usage++) == 0) | |
97 | (clk->enable)(clk, 1); | |
98 | ||
0cdf3aff | 99 | spin_unlock_irqrestore(&clocks_lock, flags); |
adbefaa5 BD |
100 | return 0; |
101 | } | |
102 | ||
103 | void clk_disable(struct clk *clk) | |
104 | { | |
0cdf3aff MB |
105 | unsigned long flags; |
106 | ||
adbefaa5 BD |
107 | if (IS_ERR(clk) || clk == NULL) |
108 | return; | |
109 | ||
0cdf3aff | 110 | spin_lock_irqsave(&clocks_lock, flags); |
adbefaa5 BD |
111 | |
112 | if ((--clk->usage) == 0) | |
113 | (clk->enable)(clk, 0); | |
114 | ||
0cdf3aff | 115 | spin_unlock_irqrestore(&clocks_lock, flags); |
adbefaa5 BD |
116 | clk_disable(clk->parent); |
117 | } | |
118 | ||
119 | ||
120 | unsigned long clk_get_rate(struct clk *clk) | |
121 | { | |
13acc291 | 122 | if (IS_ERR_OR_NULL(clk)) |
adbefaa5 BD |
123 | return 0; |
124 | ||
125 | if (clk->rate != 0) | |
126 | return clk->rate; | |
127 | ||
b3bf41be BD |
128 | if (clk->ops != NULL && clk->ops->get_rate != NULL) |
129 | return (clk->ops->get_rate)(clk); | |
adbefaa5 BD |
130 | |
131 | if (clk->parent != NULL) | |
132 | return clk_get_rate(clk->parent); | |
133 | ||
134 | return clk->rate; | |
135 | } | |
136 | ||
137 | long clk_round_rate(struct clk *clk, unsigned long rate) | |
138 | { | |
13acc291 | 139 | if (!IS_ERR_OR_NULL(clk) && clk->ops && clk->ops->round_rate) |
b3bf41be | 140 | return (clk->ops->round_rate)(clk, rate); |
adbefaa5 BD |
141 | |
142 | return rate; | |
143 | } | |
144 | ||
145 | int clk_set_rate(struct clk *clk, unsigned long rate) | |
146 | { | |
d6838a62 | 147 | unsigned long flags; |
adbefaa5 BD |
148 | int ret; |
149 | ||
13acc291 | 150 | if (IS_ERR_OR_NULL(clk)) |
adbefaa5 BD |
151 | return -EINVAL; |
152 | ||
153 | /* We do not default just do a clk->rate = rate as | |
154 | * the clock may have been made this way by choice. | |
155 | */ | |
156 | ||
b3bf41be BD |
157 | WARN_ON(clk->ops == NULL); |
158 | WARN_ON(clk->ops && clk->ops->set_rate == NULL); | |
adbefaa5 | 159 | |
b3bf41be | 160 | if (clk->ops == NULL || clk->ops->set_rate == NULL) |
adbefaa5 BD |
161 | return -EINVAL; |
162 | ||
d6838a62 | 163 | spin_lock_irqsave(&clocks_lock, flags); |
b3bf41be | 164 | ret = (clk->ops->set_rate)(clk, rate); |
d6838a62 | 165 | spin_unlock_irqrestore(&clocks_lock, flags); |
adbefaa5 BD |
166 | |
167 | return ret; | |
168 | } | |
169 | ||
170 | struct clk *clk_get_parent(struct clk *clk) | |
171 | { | |
172 | return clk->parent; | |
173 | } | |
174 | ||
175 | int clk_set_parent(struct clk *clk, struct clk *parent) | |
176 | { | |
dbc5e1e8 | 177 | unsigned long flags; |
adbefaa5 BD |
178 | int ret = 0; |
179 | ||
13acc291 | 180 | if (IS_ERR_OR_NULL(clk) || IS_ERR_OR_NULL(parent)) |
adbefaa5 BD |
181 | return -EINVAL; |
182 | ||
dbc5e1e8 | 183 | spin_lock_irqsave(&clocks_lock, flags); |
adbefaa5 | 184 | |
b3bf41be BD |
185 | if (clk->ops && clk->ops->set_parent) |
186 | ret = (clk->ops->set_parent)(clk, parent); | |
adbefaa5 | 187 | |
dbc5e1e8 | 188 | spin_unlock_irqrestore(&clocks_lock, flags); |
adbefaa5 BD |
189 | |
190 | return ret; | |
191 | } | |
192 | ||
adbefaa5 BD |
193 | EXPORT_SYMBOL(clk_enable); |
194 | EXPORT_SYMBOL(clk_disable); | |
195 | EXPORT_SYMBOL(clk_get_rate); | |
196 | EXPORT_SYMBOL(clk_round_rate); | |
197 | EXPORT_SYMBOL(clk_set_rate); | |
198 | EXPORT_SYMBOL(clk_get_parent); | |
199 | EXPORT_SYMBOL(clk_set_parent); | |
200 | ||
201 | /* base clocks */ | |
202 | ||
ed276849 | 203 | int clk_default_setrate(struct clk *clk, unsigned long rate) |
adbefaa5 BD |
204 | { |
205 | clk->rate = rate; | |
206 | return 0; | |
207 | } | |
208 | ||
ed276849 | 209 | struct clk_ops clk_ops_def_setrate = { |
b3bf41be BD |
210 | .set_rate = clk_default_setrate, |
211 | }; | |
212 | ||
adbefaa5 BD |
213 | struct clk clk_xtal = { |
214 | .name = "xtal", | |
adbefaa5 BD |
215 | .rate = 0, |
216 | .parent = NULL, | |
217 | .ctrlbit = 0, | |
218 | }; | |
219 | ||
4b31d8b2 BD |
220 | struct clk clk_ext = { |
221 | .name = "ext", | |
4b31d8b2 BD |
222 | }; |
223 | ||
224 | struct clk clk_epll = { | |
225 | .name = "epll", | |
4b31d8b2 BD |
226 | }; |
227 | ||
adbefaa5 BD |
228 | struct clk clk_mpll = { |
229 | .name = "mpll", | |
b3bf41be | 230 | .ops = &clk_ops_def_setrate, |
adbefaa5 BD |
231 | }; |
232 | ||
233 | struct clk clk_upll = { | |
234 | .name = "upll", | |
adbefaa5 BD |
235 | .parent = NULL, |
236 | .ctrlbit = 0, | |
237 | }; | |
238 | ||
239 | struct clk clk_f = { | |
240 | .name = "fclk", | |
adbefaa5 BD |
241 | .rate = 0, |
242 | .parent = &clk_mpll, | |
243 | .ctrlbit = 0, | |
adbefaa5 BD |
244 | }; |
245 | ||
246 | struct clk clk_h = { | |
247 | .name = "hclk", | |
adbefaa5 BD |
248 | .rate = 0, |
249 | .parent = NULL, | |
250 | .ctrlbit = 0, | |
b3bf41be | 251 | .ops = &clk_ops_def_setrate, |
adbefaa5 BD |
252 | }; |
253 | ||
254 | struct clk clk_p = { | |
255 | .name = "pclk", | |
adbefaa5 BD |
256 | .rate = 0, |
257 | .parent = NULL, | |
258 | .ctrlbit = 0, | |
b3bf41be | 259 | .ops = &clk_ops_def_setrate, |
adbefaa5 BD |
260 | }; |
261 | ||
262 | struct clk clk_usb_bus = { | |
263 | .name = "usb-bus", | |
adbefaa5 BD |
264 | .rate = 0, |
265 | .parent = &clk_upll, | |
266 | }; | |
267 | ||
268 | ||
adbefaa5 BD |
269 | struct clk s3c24xx_uclk = { |
270 | .name = "uclk", | |
adbefaa5 BD |
271 | }; |
272 | ||
273 | /* initialise the clock system */ | |
274 | ||
8428d47a BD |
275 | /** |
276 | * s3c24xx_register_clock() - register a clock | |
277 | * @clk: The clock to register | |
278 | * | |
279 | * Add the specified clock to the list of clocks known by the system. | |
280 | */ | |
adbefaa5 BD |
281 | int s3c24xx_register_clock(struct clk *clk) |
282 | { | |
adbefaa5 BD |
283 | if (clk->enable == NULL) |
284 | clk->enable = clk_null_enable; | |
285 | ||
f86c6660 TA |
286 | /* fill up the clk_lookup structure and register it*/ |
287 | clk->lookup.dev_id = clk->devname; | |
288 | clk->lookup.con_id = clk->name; | |
289 | clk->lookup.clk = clk; | |
290 | clkdev_add(&clk->lookup); | |
adbefaa5 BD |
291 | |
292 | return 0; | |
293 | } | |
294 | ||
8428d47a BD |
295 | /** |
296 | * s3c24xx_register_clocks() - register an array of clock pointers | |
297 | * @clks: Pointer to an array of struct clk pointers | |
298 | * @nr_clks: The number of clocks in the @clks array. | |
299 | * | |
300 | * Call s3c24xx_register_clock() for all the clock pointers contained | |
301 | * in the @clks list. Returns the number of failures. | |
302 | */ | |
adbefaa5 BD |
303 | int s3c24xx_register_clocks(struct clk **clks, int nr_clks) |
304 | { | |
305 | int fails = 0; | |
306 | ||
307 | for (; nr_clks > 0; nr_clks--, clks++) { | |
50ee2d35 BD |
308 | if (s3c24xx_register_clock(*clks) < 0) { |
309 | struct clk *clk = *clks; | |
310 | printk(KERN_ERR "%s: failed to register %p: %s\n", | |
311 | __func__, clk, clk->name); | |
adbefaa5 | 312 | fails++; |
50ee2d35 | 313 | } |
adbefaa5 BD |
314 | } |
315 | ||
316 | return fails; | |
317 | } | |
318 | ||
1d9f13c4 BD |
319 | /** |
320 | * s3c_register_clocks() - register an array of clocks | |
321 | * @clkp: Pointer to the first clock in the array. | |
322 | * @nr_clks: Number of clocks to register. | |
323 | * | |
324 | * Call s3c24xx_register_clock() on the @clkp array given, printing an | |
325 | * error if it fails to register the clock (unlikely). | |
326 | */ | |
ab5d97db | 327 | void __init s3c_register_clocks(struct clk *clkp, int nr_clks) |
1d9f13c4 BD |
328 | { |
329 | int ret; | |
330 | ||
331 | for (; nr_clks > 0; nr_clks--, clkp++) { | |
332 | ret = s3c24xx_register_clock(clkp); | |
333 | ||
334 | if (ret < 0) { | |
335 | printk(KERN_ERR "Failed to register clock %s (%d)\n", | |
336 | clkp->name, ret); | |
337 | } | |
338 | } | |
339 | } | |
340 | ||
4e04691b BD |
341 | /** |
342 | * s3c_disable_clocks() - disable an array of clocks | |
343 | * @clkp: Pointer to the first clock in the array. | |
344 | * @nr_clks: Number of clocks to register. | |
345 | * | |
346 | * for internal use only at initialisation time. disable the clocks in the | |
347 | * @clkp array. | |
348 | */ | |
349 | ||
350 | void __init s3c_disable_clocks(struct clk *clkp, int nr_clks) | |
351 | { | |
352 | for (; nr_clks > 0; nr_clks--, clkp++) | |
353 | (clkp->enable)(clkp, 0); | |
354 | } | |
355 | ||
421f91d2 | 356 | /* initialise all the clocks */ |
adbefaa5 BD |
357 | |
358 | int __init s3c24xx_register_baseclocks(unsigned long xtal) | |
359 | { | |
50f430e3 | 360 | printk(KERN_INFO "S3C24XX Clocks, Copyright 2004 Simtec Electronics\n"); |
adbefaa5 BD |
361 | |
362 | clk_xtal.rate = xtal; | |
363 | ||
364 | /* register our clocks */ | |
365 | ||
366 | if (s3c24xx_register_clock(&clk_xtal) < 0) | |
367 | printk(KERN_ERR "failed to register master xtal\n"); | |
368 | ||
369 | if (s3c24xx_register_clock(&clk_mpll) < 0) | |
370 | printk(KERN_ERR "failed to register mpll clock\n"); | |
371 | ||
372 | if (s3c24xx_register_clock(&clk_upll) < 0) | |
373 | printk(KERN_ERR "failed to register upll clock\n"); | |
374 | ||
375 | if (s3c24xx_register_clock(&clk_f) < 0) | |
376 | printk(KERN_ERR "failed to register cpu fclk\n"); | |
377 | ||
378 | if (s3c24xx_register_clock(&clk_h) < 0) | |
379 | printk(KERN_ERR "failed to register cpu hclk\n"); | |
380 | ||
381 | if (s3c24xx_register_clock(&clk_p) < 0) | |
382 | printk(KERN_ERR "failed to register cpu pclk\n"); | |
383 | ||
384 | return 0; | |
385 | } | |
386 | ||
436c3878 ADK |
387 | #if defined(CONFIG_PM_DEBUG) && defined(CONFIG_DEBUG_FS) |
388 | /* debugfs support to trace clock tree hierarchy and attributes */ | |
389 | ||
390 | static struct dentry *clk_debugfs_root; | |
391 | ||
52569e2f CC |
392 | static void clock_tree_show_one(struct seq_file *s, struct clk *c, int level) |
393 | { | |
394 | struct clk *child; | |
395 | const char *state; | |
396 | char buf[255] = { 0 }; | |
397 | int n = 0; | |
398 | ||
399 | if (c->name) | |
400 | n = snprintf(buf, sizeof(buf) - 1, "%s", c->name); | |
401 | ||
402 | if (c->devname) | |
403 | n += snprintf(buf + n, sizeof(buf) - 1 - n, ":%s", c->devname); | |
404 | ||
405 | state = (c->usage > 0) ? "on" : "off"; | |
406 | ||
407 | seq_printf(s, "%*s%-*s %-6s %-3d %-10lu\n", | |
408 | level * 3 + 1, "", | |
409 | 50 - level * 3, buf, | |
410 | state, c->usage, clk_get_rate(c)); | |
411 | ||
412 | list_for_each_entry(child, &clocks, list) { | |
413 | if (child->parent != c) | |
414 | continue; | |
415 | ||
416 | clock_tree_show_one(s, child, level + 1); | |
417 | } | |
418 | } | |
419 | ||
420 | static int clock_tree_show(struct seq_file *s, void *data) | |
421 | { | |
422 | struct clk *c; | |
423 | unsigned long flags; | |
424 | ||
425 | seq_printf(s, " clock state ref rate\n"); | |
426 | seq_printf(s, "----------------------------------------------------\n"); | |
427 | ||
428 | spin_lock_irqsave(&clocks_lock, flags); | |
429 | ||
430 | list_for_each_entry(c, &clocks, list) | |
431 | if (c->parent == NULL) | |
432 | clock_tree_show_one(s, c, 0); | |
433 | ||
434 | spin_unlock_irqrestore(&clocks_lock, flags); | |
435 | return 0; | |
436 | } | |
437 | ||
438 | static int clock_tree_open(struct inode *inode, struct file *file) | |
439 | { | |
440 | return single_open(file, clock_tree_show, inode->i_private); | |
441 | } | |
442 | ||
443 | static const struct file_operations clock_tree_fops = { | |
444 | .open = clock_tree_open, | |
445 | .read = seq_read, | |
446 | .llseek = seq_lseek, | |
447 | .release = single_release, | |
448 | }; | |
449 | ||
61927135 CC |
450 | static int clock_rate_show(void *data, u64 *val) |
451 | { | |
452 | struct clk *c = data; | |
453 | *val = clk_get_rate(c); | |
454 | return 0; | |
455 | } | |
456 | DEFINE_SIMPLE_ATTRIBUTE(clock_rate_fops, clock_rate_show, NULL, "%llu\n"); | |
457 | ||
436c3878 ADK |
458 | static int clk_debugfs_register_one(struct clk *c) |
459 | { | |
460 | int err; | |
12520c43 | 461 | struct dentry *d; |
436c3878 ADK |
462 | struct clk *pa = c->parent; |
463 | char s[255]; | |
464 | char *p = s; | |
465 | ||
f86c6660 | 466 | p += sprintf(p, "%s", c->devname); |
436c3878 ADK |
467 | |
468 | d = debugfs_create_dir(s, pa ? pa->dent : clk_debugfs_root); | |
469 | if (!d) | |
470 | return -ENOMEM; | |
471 | ||
472 | c->dent = d; | |
473 | ||
474 | d = debugfs_create_u8("usecount", S_IRUGO, c->dent, (u8 *)&c->usage); | |
475 | if (!d) { | |
476 | err = -ENOMEM; | |
477 | goto err_out; | |
478 | } | |
479 | ||
61927135 | 480 | d = debugfs_create_file("rate", S_IRUGO, c->dent, c, &clock_rate_fops); |
436c3878 ADK |
481 | if (!d) { |
482 | err = -ENOMEM; | |
483 | goto err_out; | |
484 | } | |
485 | return 0; | |
486 | ||
487 | err_out: | |
12520c43 | 488 | debugfs_remove_recursive(c->dent); |
436c3878 ADK |
489 | return err; |
490 | } | |
491 | ||
492 | static int clk_debugfs_register(struct clk *c) | |
493 | { | |
494 | int err; | |
495 | struct clk *pa = c->parent; | |
496 | ||
497 | if (pa && !pa->dent) { | |
498 | err = clk_debugfs_register(pa); | |
499 | if (err) | |
500 | return err; | |
501 | } | |
502 | ||
503 | if (!c->dent) { | |
504 | err = clk_debugfs_register_one(c); | |
505 | if (err) | |
506 | return err; | |
507 | } | |
508 | return 0; | |
509 | } | |
510 | ||
511 | static int __init clk_debugfs_init(void) | |
512 | { | |
513 | struct clk *c; | |
514 | struct dentry *d; | |
52569e2f | 515 | int err = -ENOMEM; |
436c3878 ADK |
516 | |
517 | d = debugfs_create_dir("clock", NULL); | |
518 | if (!d) | |
519 | return -ENOMEM; | |
520 | clk_debugfs_root = d; | |
521 | ||
52569e2f CC |
522 | d = debugfs_create_file("clock_tree", S_IRUGO, clk_debugfs_root, NULL, |
523 | &clock_tree_fops); | |
524 | if (!d) | |
525 | goto err_out; | |
526 | ||
436c3878 ADK |
527 | list_for_each_entry(c, &clocks, list) { |
528 | err = clk_debugfs_register(c); | |
529 | if (err) | |
530 | goto err_out; | |
531 | } | |
532 | return 0; | |
533 | ||
534 | err_out: | |
535 | debugfs_remove_recursive(clk_debugfs_root); | |
536 | return err; | |
537 | } | |
538 | late_initcall(clk_debugfs_init); | |
539 | ||
540 | #endif /* defined(CONFIG_PM_DEBUG) && defined(CONFIG_DEBUG_FS) */ |