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adbefaa5 BD |
1 | /* linux/arch/arm/plat-s3c24xx/clock.c |
2 | * | |
50f430e3 | 3 | * Copyright 2004-2005 Simtec Electronics |
adbefaa5 BD |
4 | * Ben Dooks <ben@simtec.co.uk> |
5 | * | |
6 | * S3C24XX Core clock control support | |
7 | * | |
8 | * Based on, and code from linux/arch/arm/mach-versatile/clock.c | |
9 | ** | |
10 | ** Copyright (C) 2004 ARM Limited. | |
11 | ** Written by Deep Blue Solutions Limited. | |
12 | * | |
13 | * | |
14 | * This program is free software; you can redistribute it and/or modify | |
15 | * it under the terms of the GNU General Public License as published by | |
16 | * the Free Software Foundation; either version 2 of the License, or | |
17 | * (at your option) any later version. | |
18 | * | |
19 | * This program is distributed in the hope that it will be useful, | |
20 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
21 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
22 | * GNU General Public License for more details. | |
23 | * | |
24 | * You should have received a copy of the GNU General Public License | |
25 | * along with this program; if not, write to the Free Software | |
26 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
27 | */ | |
28 | ||
29 | #include <linux/init.h> | |
30 | #include <linux/module.h> | |
31 | #include <linux/kernel.h> | |
32 | #include <linux/list.h> | |
33 | #include <linux/errno.h> | |
34 | #include <linux/err.h> | |
35 | #include <linux/platform_device.h> | |
edbaa603 | 36 | #include <linux/device.h> |
adbefaa5 BD |
37 | #include <linux/interrupt.h> |
38 | #include <linux/ioport.h> | |
39 | #include <linux/clk.h> | |
40 | #include <linux/spinlock.h> | |
adbefaa5 | 41 | #include <linux/io.h> |
436c3878 ADK |
42 | #if defined(CONFIG_DEBUG_FS) |
43 | #include <linux/debugfs.h> | |
44 | #endif | |
adbefaa5 BD |
45 | |
46 | #include <mach/hardware.h> | |
47 | #include <asm/irq.h> | |
48 | ||
49 | #include <plat/cpu-freq.h> | |
50 | ||
51 | #include <plat/clock.h> | |
52 | #include <plat/cpu.h> | |
53 | ||
7cf4b482 MS |
54 | #include <linux/serial_core.h> |
55 | #include <plat/regs-serial.h> /* for s3c24xx_uart_devs */ | |
56 | ||
adbefaa5 BD |
57 | /* clock information */ |
58 | ||
59 | static LIST_HEAD(clocks); | |
60 | ||
61 | /* We originally used an mutex here, but some contexts (see resume) | |
62 | * are calling functions such as clk_set_parent() with IRQs disabled | |
63 | * causing an BUG to be triggered. | |
64 | */ | |
65 | DEFINE_SPINLOCK(clocks_lock); | |
66 | ||
caf27307 MS |
67 | /* Global watchdog clock used by arch_wtd_reset() callback */ |
68 | struct clk *s3c2410_wdtclk; | |
69 | static int __init s3c_wdt_reset_init(void) | |
70 | { | |
71 | s3c2410_wdtclk = clk_get(NULL, "watchdog"); | |
72 | if (IS_ERR(s3c2410_wdtclk)) | |
73 | printk(KERN_WARNING "%s: warning: cannot get watchdog clock\n", __func__); | |
74 | return 0; | |
75 | } | |
76 | arch_initcall(s3c_wdt_reset_init); | |
77 | ||
adbefaa5 BD |
78 | /* enable and disable calls for use with the clk struct */ |
79 | ||
80 | static int clk_null_enable(struct clk *clk, int enable) | |
81 | { | |
82 | return 0; | |
83 | } | |
84 | ||
adbefaa5 BD |
85 | int clk_enable(struct clk *clk) |
86 | { | |
0cdf3aff MB |
87 | unsigned long flags; |
88 | ||
adbefaa5 BD |
89 | if (IS_ERR(clk) || clk == NULL) |
90 | return -EINVAL; | |
91 | ||
92 | clk_enable(clk->parent); | |
93 | ||
0cdf3aff | 94 | spin_lock_irqsave(&clocks_lock, flags); |
adbefaa5 BD |
95 | |
96 | if ((clk->usage++) == 0) | |
97 | (clk->enable)(clk, 1); | |
98 | ||
0cdf3aff | 99 | spin_unlock_irqrestore(&clocks_lock, flags); |
adbefaa5 BD |
100 | return 0; |
101 | } | |
102 | ||
103 | void clk_disable(struct clk *clk) | |
104 | { | |
0cdf3aff MB |
105 | unsigned long flags; |
106 | ||
adbefaa5 BD |
107 | if (IS_ERR(clk) || clk == NULL) |
108 | return; | |
109 | ||
0cdf3aff | 110 | spin_lock_irqsave(&clocks_lock, flags); |
adbefaa5 BD |
111 | |
112 | if ((--clk->usage) == 0) | |
113 | (clk->enable)(clk, 0); | |
114 | ||
0cdf3aff | 115 | spin_unlock_irqrestore(&clocks_lock, flags); |
adbefaa5 BD |
116 | clk_disable(clk->parent); |
117 | } | |
118 | ||
119 | ||
120 | unsigned long clk_get_rate(struct clk *clk) | |
121 | { | |
122 | if (IS_ERR(clk)) | |
123 | return 0; | |
124 | ||
125 | if (clk->rate != 0) | |
126 | return clk->rate; | |
127 | ||
b3bf41be BD |
128 | if (clk->ops != NULL && clk->ops->get_rate != NULL) |
129 | return (clk->ops->get_rate)(clk); | |
adbefaa5 BD |
130 | |
131 | if (clk->parent != NULL) | |
132 | return clk_get_rate(clk->parent); | |
133 | ||
134 | return clk->rate; | |
135 | } | |
136 | ||
137 | long clk_round_rate(struct clk *clk, unsigned long rate) | |
138 | { | |
b3bf41be BD |
139 | if (!IS_ERR(clk) && clk->ops && clk->ops->round_rate) |
140 | return (clk->ops->round_rate)(clk, rate); | |
adbefaa5 BD |
141 | |
142 | return rate; | |
143 | } | |
144 | ||
145 | int clk_set_rate(struct clk *clk, unsigned long rate) | |
146 | { | |
147 | int ret; | |
148 | ||
149 | if (IS_ERR(clk)) | |
150 | return -EINVAL; | |
151 | ||
152 | /* We do not default just do a clk->rate = rate as | |
153 | * the clock may have been made this way by choice. | |
154 | */ | |
155 | ||
b3bf41be BD |
156 | WARN_ON(clk->ops == NULL); |
157 | WARN_ON(clk->ops && clk->ops->set_rate == NULL); | |
adbefaa5 | 158 | |
b3bf41be | 159 | if (clk->ops == NULL || clk->ops->set_rate == NULL) |
adbefaa5 BD |
160 | return -EINVAL; |
161 | ||
162 | spin_lock(&clocks_lock); | |
b3bf41be | 163 | ret = (clk->ops->set_rate)(clk, rate); |
adbefaa5 BD |
164 | spin_unlock(&clocks_lock); |
165 | ||
166 | return ret; | |
167 | } | |
168 | ||
169 | struct clk *clk_get_parent(struct clk *clk) | |
170 | { | |
171 | return clk->parent; | |
172 | } | |
173 | ||
174 | int clk_set_parent(struct clk *clk, struct clk *parent) | |
175 | { | |
176 | int ret = 0; | |
177 | ||
178 | if (IS_ERR(clk)) | |
179 | return -EINVAL; | |
180 | ||
181 | spin_lock(&clocks_lock); | |
182 | ||
b3bf41be BD |
183 | if (clk->ops && clk->ops->set_parent) |
184 | ret = (clk->ops->set_parent)(clk, parent); | |
adbefaa5 BD |
185 | |
186 | spin_unlock(&clocks_lock); | |
187 | ||
188 | return ret; | |
189 | } | |
190 | ||
adbefaa5 BD |
191 | EXPORT_SYMBOL(clk_enable); |
192 | EXPORT_SYMBOL(clk_disable); | |
193 | EXPORT_SYMBOL(clk_get_rate); | |
194 | EXPORT_SYMBOL(clk_round_rate); | |
195 | EXPORT_SYMBOL(clk_set_rate); | |
196 | EXPORT_SYMBOL(clk_get_parent); | |
197 | EXPORT_SYMBOL(clk_set_parent); | |
198 | ||
199 | /* base clocks */ | |
200 | ||
ed276849 | 201 | int clk_default_setrate(struct clk *clk, unsigned long rate) |
adbefaa5 BD |
202 | { |
203 | clk->rate = rate; | |
204 | return 0; | |
205 | } | |
206 | ||
ed276849 | 207 | struct clk_ops clk_ops_def_setrate = { |
b3bf41be BD |
208 | .set_rate = clk_default_setrate, |
209 | }; | |
210 | ||
adbefaa5 BD |
211 | struct clk clk_xtal = { |
212 | .name = "xtal", | |
adbefaa5 BD |
213 | .rate = 0, |
214 | .parent = NULL, | |
215 | .ctrlbit = 0, | |
216 | }; | |
217 | ||
4b31d8b2 BD |
218 | struct clk clk_ext = { |
219 | .name = "ext", | |
4b31d8b2 BD |
220 | }; |
221 | ||
222 | struct clk clk_epll = { | |
223 | .name = "epll", | |
4b31d8b2 BD |
224 | }; |
225 | ||
adbefaa5 BD |
226 | struct clk clk_mpll = { |
227 | .name = "mpll", | |
b3bf41be | 228 | .ops = &clk_ops_def_setrate, |
adbefaa5 BD |
229 | }; |
230 | ||
231 | struct clk clk_upll = { | |
232 | .name = "upll", | |
adbefaa5 BD |
233 | .parent = NULL, |
234 | .ctrlbit = 0, | |
235 | }; | |
236 | ||
237 | struct clk clk_f = { | |
238 | .name = "fclk", | |
adbefaa5 BD |
239 | .rate = 0, |
240 | .parent = &clk_mpll, | |
241 | .ctrlbit = 0, | |
adbefaa5 BD |
242 | }; |
243 | ||
244 | struct clk clk_h = { | |
245 | .name = "hclk", | |
adbefaa5 BD |
246 | .rate = 0, |
247 | .parent = NULL, | |
248 | .ctrlbit = 0, | |
b3bf41be | 249 | .ops = &clk_ops_def_setrate, |
adbefaa5 BD |
250 | }; |
251 | ||
252 | struct clk clk_p = { | |
253 | .name = "pclk", | |
adbefaa5 BD |
254 | .rate = 0, |
255 | .parent = NULL, | |
256 | .ctrlbit = 0, | |
b3bf41be | 257 | .ops = &clk_ops_def_setrate, |
adbefaa5 BD |
258 | }; |
259 | ||
260 | struct clk clk_usb_bus = { | |
261 | .name = "usb-bus", | |
adbefaa5 BD |
262 | .rate = 0, |
263 | .parent = &clk_upll, | |
264 | }; | |
265 | ||
266 | ||
adbefaa5 BD |
267 | struct clk s3c24xx_uclk = { |
268 | .name = "uclk", | |
adbefaa5 BD |
269 | }; |
270 | ||
271 | /* initialise the clock system */ | |
272 | ||
8428d47a BD |
273 | /** |
274 | * s3c24xx_register_clock() - register a clock | |
275 | * @clk: The clock to register | |
276 | * | |
277 | * Add the specified clock to the list of clocks known by the system. | |
278 | */ | |
adbefaa5 BD |
279 | int s3c24xx_register_clock(struct clk *clk) |
280 | { | |
adbefaa5 BD |
281 | if (clk->enable == NULL) |
282 | clk->enable = clk_null_enable; | |
283 | ||
f86c6660 TA |
284 | /* fill up the clk_lookup structure and register it*/ |
285 | clk->lookup.dev_id = clk->devname; | |
286 | clk->lookup.con_id = clk->name; | |
287 | clk->lookup.clk = clk; | |
288 | clkdev_add(&clk->lookup); | |
adbefaa5 BD |
289 | |
290 | return 0; | |
291 | } | |
292 | ||
8428d47a BD |
293 | /** |
294 | * s3c24xx_register_clocks() - register an array of clock pointers | |
295 | * @clks: Pointer to an array of struct clk pointers | |
296 | * @nr_clks: The number of clocks in the @clks array. | |
297 | * | |
298 | * Call s3c24xx_register_clock() for all the clock pointers contained | |
299 | * in the @clks list. Returns the number of failures. | |
300 | */ | |
adbefaa5 BD |
301 | int s3c24xx_register_clocks(struct clk **clks, int nr_clks) |
302 | { | |
303 | int fails = 0; | |
304 | ||
305 | for (; nr_clks > 0; nr_clks--, clks++) { | |
50ee2d35 BD |
306 | if (s3c24xx_register_clock(*clks) < 0) { |
307 | struct clk *clk = *clks; | |
308 | printk(KERN_ERR "%s: failed to register %p: %s\n", | |
309 | __func__, clk, clk->name); | |
adbefaa5 | 310 | fails++; |
50ee2d35 | 311 | } |
adbefaa5 BD |
312 | } |
313 | ||
314 | return fails; | |
315 | } | |
316 | ||
1d9f13c4 BD |
317 | /** |
318 | * s3c_register_clocks() - register an array of clocks | |
319 | * @clkp: Pointer to the first clock in the array. | |
320 | * @nr_clks: Number of clocks to register. | |
321 | * | |
322 | * Call s3c24xx_register_clock() on the @clkp array given, printing an | |
323 | * error if it fails to register the clock (unlikely). | |
324 | */ | |
ab5d97db | 325 | void __init s3c_register_clocks(struct clk *clkp, int nr_clks) |
1d9f13c4 BD |
326 | { |
327 | int ret; | |
328 | ||
329 | for (; nr_clks > 0; nr_clks--, clkp++) { | |
330 | ret = s3c24xx_register_clock(clkp); | |
331 | ||
332 | if (ret < 0) { | |
333 | printk(KERN_ERR "Failed to register clock %s (%d)\n", | |
334 | clkp->name, ret); | |
335 | } | |
336 | } | |
337 | } | |
338 | ||
4e04691b BD |
339 | /** |
340 | * s3c_disable_clocks() - disable an array of clocks | |
341 | * @clkp: Pointer to the first clock in the array. | |
342 | * @nr_clks: Number of clocks to register. | |
343 | * | |
344 | * for internal use only at initialisation time. disable the clocks in the | |
345 | * @clkp array. | |
346 | */ | |
347 | ||
348 | void __init s3c_disable_clocks(struct clk *clkp, int nr_clks) | |
349 | { | |
350 | for (; nr_clks > 0; nr_clks--, clkp++) | |
351 | (clkp->enable)(clkp, 0); | |
352 | } | |
353 | ||
421f91d2 | 354 | /* initialise all the clocks */ |
adbefaa5 BD |
355 | |
356 | int __init s3c24xx_register_baseclocks(unsigned long xtal) | |
357 | { | |
50f430e3 | 358 | printk(KERN_INFO "S3C24XX Clocks, Copyright 2004 Simtec Electronics\n"); |
adbefaa5 BD |
359 | |
360 | clk_xtal.rate = xtal; | |
361 | ||
362 | /* register our clocks */ | |
363 | ||
364 | if (s3c24xx_register_clock(&clk_xtal) < 0) | |
365 | printk(KERN_ERR "failed to register master xtal\n"); | |
366 | ||
367 | if (s3c24xx_register_clock(&clk_mpll) < 0) | |
368 | printk(KERN_ERR "failed to register mpll clock\n"); | |
369 | ||
370 | if (s3c24xx_register_clock(&clk_upll) < 0) | |
371 | printk(KERN_ERR "failed to register upll clock\n"); | |
372 | ||
373 | if (s3c24xx_register_clock(&clk_f) < 0) | |
374 | printk(KERN_ERR "failed to register cpu fclk\n"); | |
375 | ||
376 | if (s3c24xx_register_clock(&clk_h) < 0) | |
377 | printk(KERN_ERR "failed to register cpu hclk\n"); | |
378 | ||
379 | if (s3c24xx_register_clock(&clk_p) < 0) | |
380 | printk(KERN_ERR "failed to register cpu pclk\n"); | |
381 | ||
382 | return 0; | |
383 | } | |
384 | ||
436c3878 ADK |
385 | #if defined(CONFIG_PM_DEBUG) && defined(CONFIG_DEBUG_FS) |
386 | /* debugfs support to trace clock tree hierarchy and attributes */ | |
387 | ||
388 | static struct dentry *clk_debugfs_root; | |
389 | ||
390 | static int clk_debugfs_register_one(struct clk *c) | |
391 | { | |
392 | int err; | |
12520c43 | 393 | struct dentry *d; |
436c3878 ADK |
394 | struct clk *pa = c->parent; |
395 | char s[255]; | |
396 | char *p = s; | |
397 | ||
f86c6660 | 398 | p += sprintf(p, "%s", c->devname); |
436c3878 ADK |
399 | |
400 | d = debugfs_create_dir(s, pa ? pa->dent : clk_debugfs_root); | |
401 | if (!d) | |
402 | return -ENOMEM; | |
403 | ||
404 | c->dent = d; | |
405 | ||
406 | d = debugfs_create_u8("usecount", S_IRUGO, c->dent, (u8 *)&c->usage); | |
407 | if (!d) { | |
408 | err = -ENOMEM; | |
409 | goto err_out; | |
410 | } | |
411 | ||
412 | d = debugfs_create_u32("rate", S_IRUGO, c->dent, (u32 *)&c->rate); | |
413 | if (!d) { | |
414 | err = -ENOMEM; | |
415 | goto err_out; | |
416 | } | |
417 | return 0; | |
418 | ||
419 | err_out: | |
12520c43 | 420 | debugfs_remove_recursive(c->dent); |
436c3878 ADK |
421 | return err; |
422 | } | |
423 | ||
424 | static int clk_debugfs_register(struct clk *c) | |
425 | { | |
426 | int err; | |
427 | struct clk *pa = c->parent; | |
428 | ||
429 | if (pa && !pa->dent) { | |
430 | err = clk_debugfs_register(pa); | |
431 | if (err) | |
432 | return err; | |
433 | } | |
434 | ||
435 | if (!c->dent) { | |
436 | err = clk_debugfs_register_one(c); | |
437 | if (err) | |
438 | return err; | |
439 | } | |
440 | return 0; | |
441 | } | |
442 | ||
443 | static int __init clk_debugfs_init(void) | |
444 | { | |
445 | struct clk *c; | |
446 | struct dentry *d; | |
447 | int err; | |
448 | ||
449 | d = debugfs_create_dir("clock", NULL); | |
450 | if (!d) | |
451 | return -ENOMEM; | |
452 | clk_debugfs_root = d; | |
453 | ||
454 | list_for_each_entry(c, &clocks, list) { | |
455 | err = clk_debugfs_register(c); | |
456 | if (err) | |
457 | goto err_out; | |
458 | } | |
459 | return 0; | |
460 | ||
461 | err_out: | |
462 | debugfs_remove_recursive(clk_debugfs_root); | |
463 | return err; | |
464 | } | |
465 | late_initcall(clk_debugfs_init); | |
466 | ||
467 | #endif /* defined(CONFIG_PM_DEBUG) && defined(CONFIG_DEBUG_FS) */ |