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adbefaa5 BD |
1 | /* linux/arch/arm/plat-s3c24xx/clock.c |
2 | * | |
50f430e3 | 3 | * Copyright 2004-2005 Simtec Electronics |
adbefaa5 BD |
4 | * Ben Dooks <ben@simtec.co.uk> |
5 | * | |
6 | * S3C24XX Core clock control support | |
7 | * | |
8 | * Based on, and code from linux/arch/arm/mach-versatile/clock.c | |
9 | ** | |
10 | ** Copyright (C) 2004 ARM Limited. | |
11 | ** Written by Deep Blue Solutions Limited. | |
12 | * | |
13 | * | |
14 | * This program is free software; you can redistribute it and/or modify | |
15 | * it under the terms of the GNU General Public License as published by | |
16 | * the Free Software Foundation; either version 2 of the License, or | |
17 | * (at your option) any later version. | |
18 | * | |
19 | * This program is distributed in the hope that it will be useful, | |
20 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
21 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
22 | * GNU General Public License for more details. | |
23 | * | |
24 | * You should have received a copy of the GNU General Public License | |
25 | * along with this program; if not, write to the Free Software | |
26 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
27 | */ | |
28 | ||
29 | #include <linux/init.h> | |
30 | #include <linux/module.h> | |
31 | #include <linux/kernel.h> | |
32 | #include <linux/list.h> | |
33 | #include <linux/errno.h> | |
34 | #include <linux/err.h> | |
35 | #include <linux/platform_device.h> | |
edbaa603 | 36 | #include <linux/device.h> |
adbefaa5 BD |
37 | #include <linux/interrupt.h> |
38 | #include <linux/ioport.h> | |
39 | #include <linux/clk.h> | |
40 | #include <linux/spinlock.h> | |
adbefaa5 | 41 | #include <linux/io.h> |
436c3878 ADK |
42 | #if defined(CONFIG_DEBUG_FS) |
43 | #include <linux/debugfs.h> | |
44 | #endif | |
adbefaa5 | 45 | |
adbefaa5 BD |
46 | #include <asm/irq.h> |
47 | ||
48 | #include <plat/cpu-freq.h> | |
49 | ||
50 | #include <plat/clock.h> | |
51 | #include <plat/cpu.h> | |
52 | ||
7cf4b482 | 53 | #include <linux/serial_core.h> |
334a1c70 | 54 | #include <linux/serial_s3c.h> /* for s3c24xx_uart_devs */ |
7cf4b482 | 55 | |
adbefaa5 BD |
56 | /* clock information */ |
57 | ||
58 | static LIST_HEAD(clocks); | |
59 | ||
60 | /* We originally used an mutex here, but some contexts (see resume) | |
61 | * are calling functions such as clk_set_parent() with IRQs disabled | |
62 | * causing an BUG to be triggered. | |
63 | */ | |
64 | DEFINE_SPINLOCK(clocks_lock); | |
65 | ||
caf27307 MS |
66 | /* Global watchdog clock used by arch_wtd_reset() callback */ |
67 | struct clk *s3c2410_wdtclk; | |
68 | static int __init s3c_wdt_reset_init(void) | |
69 | { | |
70 | s3c2410_wdtclk = clk_get(NULL, "watchdog"); | |
71 | if (IS_ERR(s3c2410_wdtclk)) | |
72 | printk(KERN_WARNING "%s: warning: cannot get watchdog clock\n", __func__); | |
73 | return 0; | |
74 | } | |
75 | arch_initcall(s3c_wdt_reset_init); | |
76 | ||
adbefaa5 BD |
77 | /* enable and disable calls for use with the clk struct */ |
78 | ||
79 | static int clk_null_enable(struct clk *clk, int enable) | |
80 | { | |
81 | return 0; | |
82 | } | |
83 | ||
adbefaa5 BD |
84 | int clk_enable(struct clk *clk) |
85 | { | |
0cdf3aff MB |
86 | unsigned long flags; |
87 | ||
adbefaa5 BD |
88 | if (IS_ERR(clk) || clk == NULL) |
89 | return -EINVAL; | |
90 | ||
91 | clk_enable(clk->parent); | |
92 | ||
0cdf3aff | 93 | spin_lock_irqsave(&clocks_lock, flags); |
adbefaa5 BD |
94 | |
95 | if ((clk->usage++) == 0) | |
96 | (clk->enable)(clk, 1); | |
97 | ||
0cdf3aff | 98 | spin_unlock_irqrestore(&clocks_lock, flags); |
adbefaa5 BD |
99 | return 0; |
100 | } | |
101 | ||
102 | void clk_disable(struct clk *clk) | |
103 | { | |
0cdf3aff MB |
104 | unsigned long flags; |
105 | ||
adbefaa5 BD |
106 | if (IS_ERR(clk) || clk == NULL) |
107 | return; | |
108 | ||
0cdf3aff | 109 | spin_lock_irqsave(&clocks_lock, flags); |
adbefaa5 BD |
110 | |
111 | if ((--clk->usage) == 0) | |
112 | (clk->enable)(clk, 0); | |
113 | ||
0cdf3aff | 114 | spin_unlock_irqrestore(&clocks_lock, flags); |
adbefaa5 BD |
115 | clk_disable(clk->parent); |
116 | } | |
117 | ||
118 | ||
119 | unsigned long clk_get_rate(struct clk *clk) | |
120 | { | |
13acc291 | 121 | if (IS_ERR_OR_NULL(clk)) |
adbefaa5 BD |
122 | return 0; |
123 | ||
124 | if (clk->rate != 0) | |
125 | return clk->rate; | |
126 | ||
b3bf41be BD |
127 | if (clk->ops != NULL && clk->ops->get_rate != NULL) |
128 | return (clk->ops->get_rate)(clk); | |
adbefaa5 BD |
129 | |
130 | if (clk->parent != NULL) | |
131 | return clk_get_rate(clk->parent); | |
132 | ||
133 | return clk->rate; | |
134 | } | |
135 | ||
136 | long clk_round_rate(struct clk *clk, unsigned long rate) | |
137 | { | |
13acc291 | 138 | if (!IS_ERR_OR_NULL(clk) && clk->ops && clk->ops->round_rate) |
b3bf41be | 139 | return (clk->ops->round_rate)(clk, rate); |
adbefaa5 BD |
140 | |
141 | return rate; | |
142 | } | |
143 | ||
144 | int clk_set_rate(struct clk *clk, unsigned long rate) | |
145 | { | |
d6838a62 | 146 | unsigned long flags; |
adbefaa5 BD |
147 | int ret; |
148 | ||
13acc291 | 149 | if (IS_ERR_OR_NULL(clk)) |
adbefaa5 BD |
150 | return -EINVAL; |
151 | ||
152 | /* We do not default just do a clk->rate = rate as | |
153 | * the clock may have been made this way by choice. | |
154 | */ | |
155 | ||
b3bf41be BD |
156 | WARN_ON(clk->ops == NULL); |
157 | WARN_ON(clk->ops && clk->ops->set_rate == NULL); | |
adbefaa5 | 158 | |
b3bf41be | 159 | if (clk->ops == NULL || clk->ops->set_rate == NULL) |
adbefaa5 BD |
160 | return -EINVAL; |
161 | ||
d6838a62 | 162 | spin_lock_irqsave(&clocks_lock, flags); |
b3bf41be | 163 | ret = (clk->ops->set_rate)(clk, rate); |
d6838a62 | 164 | spin_unlock_irqrestore(&clocks_lock, flags); |
adbefaa5 BD |
165 | |
166 | return ret; | |
167 | } | |
168 | ||
169 | struct clk *clk_get_parent(struct clk *clk) | |
170 | { | |
171 | return clk->parent; | |
172 | } | |
173 | ||
174 | int clk_set_parent(struct clk *clk, struct clk *parent) | |
175 | { | |
dbc5e1e8 | 176 | unsigned long flags; |
adbefaa5 BD |
177 | int ret = 0; |
178 | ||
13acc291 | 179 | if (IS_ERR_OR_NULL(clk) || IS_ERR_OR_NULL(parent)) |
adbefaa5 BD |
180 | return -EINVAL; |
181 | ||
dbc5e1e8 | 182 | spin_lock_irqsave(&clocks_lock, flags); |
adbefaa5 | 183 | |
b3bf41be BD |
184 | if (clk->ops && clk->ops->set_parent) |
185 | ret = (clk->ops->set_parent)(clk, parent); | |
adbefaa5 | 186 | |
dbc5e1e8 | 187 | spin_unlock_irqrestore(&clocks_lock, flags); |
adbefaa5 BD |
188 | |
189 | return ret; | |
190 | } | |
191 | ||
adbefaa5 BD |
192 | EXPORT_SYMBOL(clk_enable); |
193 | EXPORT_SYMBOL(clk_disable); | |
194 | EXPORT_SYMBOL(clk_get_rate); | |
195 | EXPORT_SYMBOL(clk_round_rate); | |
196 | EXPORT_SYMBOL(clk_set_rate); | |
197 | EXPORT_SYMBOL(clk_get_parent); | |
198 | EXPORT_SYMBOL(clk_set_parent); | |
199 | ||
200 | /* base clocks */ | |
201 | ||
ed276849 | 202 | int clk_default_setrate(struct clk *clk, unsigned long rate) |
adbefaa5 BD |
203 | { |
204 | clk->rate = rate; | |
205 | return 0; | |
206 | } | |
207 | ||
ed276849 | 208 | struct clk_ops clk_ops_def_setrate = { |
b3bf41be BD |
209 | .set_rate = clk_default_setrate, |
210 | }; | |
211 | ||
adbefaa5 BD |
212 | struct clk clk_xtal = { |
213 | .name = "xtal", | |
adbefaa5 BD |
214 | .rate = 0, |
215 | .parent = NULL, | |
216 | .ctrlbit = 0, | |
217 | }; | |
218 | ||
4b31d8b2 BD |
219 | struct clk clk_ext = { |
220 | .name = "ext", | |
4b31d8b2 BD |
221 | }; |
222 | ||
223 | struct clk clk_epll = { | |
224 | .name = "epll", | |
4b31d8b2 BD |
225 | }; |
226 | ||
adbefaa5 BD |
227 | struct clk clk_mpll = { |
228 | .name = "mpll", | |
b3bf41be | 229 | .ops = &clk_ops_def_setrate, |
adbefaa5 BD |
230 | }; |
231 | ||
232 | struct clk clk_upll = { | |
233 | .name = "upll", | |
adbefaa5 BD |
234 | .parent = NULL, |
235 | .ctrlbit = 0, | |
236 | }; | |
237 | ||
238 | struct clk clk_f = { | |
239 | .name = "fclk", | |
adbefaa5 BD |
240 | .rate = 0, |
241 | .parent = &clk_mpll, | |
242 | .ctrlbit = 0, | |
adbefaa5 BD |
243 | }; |
244 | ||
245 | struct clk clk_h = { | |
246 | .name = "hclk", | |
adbefaa5 BD |
247 | .rate = 0, |
248 | .parent = NULL, | |
249 | .ctrlbit = 0, | |
b3bf41be | 250 | .ops = &clk_ops_def_setrate, |
adbefaa5 BD |
251 | }; |
252 | ||
253 | struct clk clk_p = { | |
254 | .name = "pclk", | |
adbefaa5 BD |
255 | .rate = 0, |
256 | .parent = NULL, | |
257 | .ctrlbit = 0, | |
b3bf41be | 258 | .ops = &clk_ops_def_setrate, |
adbefaa5 BD |
259 | }; |
260 | ||
261 | struct clk clk_usb_bus = { | |
262 | .name = "usb-bus", | |
adbefaa5 BD |
263 | .rate = 0, |
264 | .parent = &clk_upll, | |
265 | }; | |
266 | ||
267 | ||
adbefaa5 BD |
268 | struct clk s3c24xx_uclk = { |
269 | .name = "uclk", | |
adbefaa5 BD |
270 | }; |
271 | ||
272 | /* initialise the clock system */ | |
273 | ||
8428d47a BD |
274 | /** |
275 | * s3c24xx_register_clock() - register a clock | |
276 | * @clk: The clock to register | |
277 | * | |
278 | * Add the specified clock to the list of clocks known by the system. | |
279 | */ | |
adbefaa5 BD |
280 | int s3c24xx_register_clock(struct clk *clk) |
281 | { | |
adbefaa5 BD |
282 | if (clk->enable == NULL) |
283 | clk->enable = clk_null_enable; | |
284 | ||
f86c6660 TA |
285 | /* fill up the clk_lookup structure and register it*/ |
286 | clk->lookup.dev_id = clk->devname; | |
287 | clk->lookup.con_id = clk->name; | |
288 | clk->lookup.clk = clk; | |
289 | clkdev_add(&clk->lookup); | |
adbefaa5 BD |
290 | |
291 | return 0; | |
292 | } | |
293 | ||
8428d47a BD |
294 | /** |
295 | * s3c24xx_register_clocks() - register an array of clock pointers | |
296 | * @clks: Pointer to an array of struct clk pointers | |
297 | * @nr_clks: The number of clocks in the @clks array. | |
298 | * | |
299 | * Call s3c24xx_register_clock() for all the clock pointers contained | |
300 | * in the @clks list. Returns the number of failures. | |
301 | */ | |
adbefaa5 BD |
302 | int s3c24xx_register_clocks(struct clk **clks, int nr_clks) |
303 | { | |
304 | int fails = 0; | |
305 | ||
306 | for (; nr_clks > 0; nr_clks--, clks++) { | |
50ee2d35 BD |
307 | if (s3c24xx_register_clock(*clks) < 0) { |
308 | struct clk *clk = *clks; | |
309 | printk(KERN_ERR "%s: failed to register %p: %s\n", | |
310 | __func__, clk, clk->name); | |
adbefaa5 | 311 | fails++; |
50ee2d35 | 312 | } |
adbefaa5 BD |
313 | } |
314 | ||
315 | return fails; | |
316 | } | |
317 | ||
1d9f13c4 BD |
318 | /** |
319 | * s3c_register_clocks() - register an array of clocks | |
320 | * @clkp: Pointer to the first clock in the array. | |
321 | * @nr_clks: Number of clocks to register. | |
322 | * | |
323 | * Call s3c24xx_register_clock() on the @clkp array given, printing an | |
324 | * error if it fails to register the clock (unlikely). | |
325 | */ | |
ab5d97db | 326 | void __init s3c_register_clocks(struct clk *clkp, int nr_clks) |
1d9f13c4 BD |
327 | { |
328 | int ret; | |
329 | ||
330 | for (; nr_clks > 0; nr_clks--, clkp++) { | |
331 | ret = s3c24xx_register_clock(clkp); | |
332 | ||
333 | if (ret < 0) { | |
334 | printk(KERN_ERR "Failed to register clock %s (%d)\n", | |
335 | clkp->name, ret); | |
336 | } | |
337 | } | |
338 | } | |
339 | ||
4e04691b BD |
340 | /** |
341 | * s3c_disable_clocks() - disable an array of clocks | |
342 | * @clkp: Pointer to the first clock in the array. | |
343 | * @nr_clks: Number of clocks to register. | |
344 | * | |
345 | * for internal use only at initialisation time. disable the clocks in the | |
346 | * @clkp array. | |
347 | */ | |
348 | ||
349 | void __init s3c_disable_clocks(struct clk *clkp, int nr_clks) | |
350 | { | |
351 | for (; nr_clks > 0; nr_clks--, clkp++) | |
352 | (clkp->enable)(clkp, 0); | |
353 | } | |
354 | ||
421f91d2 | 355 | /* initialise all the clocks */ |
adbefaa5 BD |
356 | |
357 | int __init s3c24xx_register_baseclocks(unsigned long xtal) | |
358 | { | |
50f430e3 | 359 | printk(KERN_INFO "S3C24XX Clocks, Copyright 2004 Simtec Electronics\n"); |
adbefaa5 BD |
360 | |
361 | clk_xtal.rate = xtal; | |
362 | ||
363 | /* register our clocks */ | |
364 | ||
365 | if (s3c24xx_register_clock(&clk_xtal) < 0) | |
366 | printk(KERN_ERR "failed to register master xtal\n"); | |
367 | ||
368 | if (s3c24xx_register_clock(&clk_mpll) < 0) | |
369 | printk(KERN_ERR "failed to register mpll clock\n"); | |
370 | ||
371 | if (s3c24xx_register_clock(&clk_upll) < 0) | |
372 | printk(KERN_ERR "failed to register upll clock\n"); | |
373 | ||
374 | if (s3c24xx_register_clock(&clk_f) < 0) | |
375 | printk(KERN_ERR "failed to register cpu fclk\n"); | |
376 | ||
377 | if (s3c24xx_register_clock(&clk_h) < 0) | |
378 | printk(KERN_ERR "failed to register cpu hclk\n"); | |
379 | ||
380 | if (s3c24xx_register_clock(&clk_p) < 0) | |
381 | printk(KERN_ERR "failed to register cpu pclk\n"); | |
382 | ||
383 | return 0; | |
384 | } | |
385 | ||
436c3878 ADK |
386 | #if defined(CONFIG_PM_DEBUG) && defined(CONFIG_DEBUG_FS) |
387 | /* debugfs support to trace clock tree hierarchy and attributes */ | |
388 | ||
389 | static struct dentry *clk_debugfs_root; | |
390 | ||
52569e2f CC |
391 | static void clock_tree_show_one(struct seq_file *s, struct clk *c, int level) |
392 | { | |
393 | struct clk *child; | |
394 | const char *state; | |
395 | char buf[255] = { 0 }; | |
396 | int n = 0; | |
397 | ||
398 | if (c->name) | |
399 | n = snprintf(buf, sizeof(buf) - 1, "%s", c->name); | |
400 | ||
401 | if (c->devname) | |
402 | n += snprintf(buf + n, sizeof(buf) - 1 - n, ":%s", c->devname); | |
403 | ||
404 | state = (c->usage > 0) ? "on" : "off"; | |
405 | ||
406 | seq_printf(s, "%*s%-*s %-6s %-3d %-10lu\n", | |
407 | level * 3 + 1, "", | |
408 | 50 - level * 3, buf, | |
409 | state, c->usage, clk_get_rate(c)); | |
410 | ||
411 | list_for_each_entry(child, &clocks, list) { | |
412 | if (child->parent != c) | |
413 | continue; | |
414 | ||
415 | clock_tree_show_one(s, child, level + 1); | |
416 | } | |
417 | } | |
418 | ||
419 | static int clock_tree_show(struct seq_file *s, void *data) | |
420 | { | |
421 | struct clk *c; | |
422 | unsigned long flags; | |
423 | ||
424 | seq_printf(s, " clock state ref rate\n"); | |
425 | seq_printf(s, "----------------------------------------------------\n"); | |
426 | ||
427 | spin_lock_irqsave(&clocks_lock, flags); | |
428 | ||
429 | list_for_each_entry(c, &clocks, list) | |
430 | if (c->parent == NULL) | |
431 | clock_tree_show_one(s, c, 0); | |
432 | ||
433 | spin_unlock_irqrestore(&clocks_lock, flags); | |
434 | return 0; | |
435 | } | |
436 | ||
437 | static int clock_tree_open(struct inode *inode, struct file *file) | |
438 | { | |
439 | return single_open(file, clock_tree_show, inode->i_private); | |
440 | } | |
441 | ||
442 | static const struct file_operations clock_tree_fops = { | |
443 | .open = clock_tree_open, | |
444 | .read = seq_read, | |
445 | .llseek = seq_lseek, | |
446 | .release = single_release, | |
447 | }; | |
448 | ||
61927135 CC |
449 | static int clock_rate_show(void *data, u64 *val) |
450 | { | |
451 | struct clk *c = data; | |
452 | *val = clk_get_rate(c); | |
453 | return 0; | |
454 | } | |
455 | DEFINE_SIMPLE_ATTRIBUTE(clock_rate_fops, clock_rate_show, NULL, "%llu\n"); | |
456 | ||
436c3878 ADK |
457 | static int clk_debugfs_register_one(struct clk *c) |
458 | { | |
459 | int err; | |
12520c43 | 460 | struct dentry *d; |
436c3878 ADK |
461 | struct clk *pa = c->parent; |
462 | char s[255]; | |
463 | char *p = s; | |
464 | ||
f86c6660 | 465 | p += sprintf(p, "%s", c->devname); |
436c3878 ADK |
466 | |
467 | d = debugfs_create_dir(s, pa ? pa->dent : clk_debugfs_root); | |
468 | if (!d) | |
469 | return -ENOMEM; | |
470 | ||
471 | c->dent = d; | |
472 | ||
473 | d = debugfs_create_u8("usecount", S_IRUGO, c->dent, (u8 *)&c->usage); | |
474 | if (!d) { | |
475 | err = -ENOMEM; | |
476 | goto err_out; | |
477 | } | |
478 | ||
61927135 | 479 | d = debugfs_create_file("rate", S_IRUGO, c->dent, c, &clock_rate_fops); |
436c3878 ADK |
480 | if (!d) { |
481 | err = -ENOMEM; | |
482 | goto err_out; | |
483 | } | |
484 | return 0; | |
485 | ||
486 | err_out: | |
12520c43 | 487 | debugfs_remove_recursive(c->dent); |
436c3878 ADK |
488 | return err; |
489 | } | |
490 | ||
491 | static int clk_debugfs_register(struct clk *c) | |
492 | { | |
493 | int err; | |
494 | struct clk *pa = c->parent; | |
495 | ||
496 | if (pa && !pa->dent) { | |
497 | err = clk_debugfs_register(pa); | |
498 | if (err) | |
499 | return err; | |
500 | } | |
501 | ||
502 | if (!c->dent) { | |
503 | err = clk_debugfs_register_one(c); | |
504 | if (err) | |
505 | return err; | |
506 | } | |
507 | return 0; | |
508 | } | |
509 | ||
510 | static int __init clk_debugfs_init(void) | |
511 | { | |
512 | struct clk *c; | |
513 | struct dentry *d; | |
52569e2f | 514 | int err = -ENOMEM; |
436c3878 ADK |
515 | |
516 | d = debugfs_create_dir("clock", NULL); | |
517 | if (!d) | |
518 | return -ENOMEM; | |
519 | clk_debugfs_root = d; | |
520 | ||
52569e2f CC |
521 | d = debugfs_create_file("clock_tree", S_IRUGO, clk_debugfs_root, NULL, |
522 | &clock_tree_fops); | |
523 | if (!d) | |
524 | goto err_out; | |
525 | ||
436c3878 ADK |
526 | list_for_each_entry(c, &clocks, list) { |
527 | err = clk_debugfs_register(c); | |
528 | if (err) | |
529 | goto err_out; | |
530 | } | |
531 | return 0; | |
532 | ||
533 | err_out: | |
534 | debugfs_remove_recursive(clk_debugfs_root); | |
535 | return err; | |
536 | } | |
537 | late_initcall(clk_debugfs_init); | |
538 | ||
539 | #endif /* defined(CONFIG_PM_DEBUG) && defined(CONFIG_DEBUG_FS) */ |