projects / deliverable / linux.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
Merge tag 'power-exynos' of git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux...
[deliverable/linux.git] / arch / arm / plat-samsung / include / plat / clock.h
CommitLineData
a503059c 1/* linux/arch/arm/plat-s3c/include/plat/clock.h
1da177e4
LT		 2 *
3 * Copyright (c) 2004-2005 Simtec Electronics
4 * http://www.simtec.co.uk/products/SWLINUX/
5 * Written by Ben Dooks, <ben@simtec.co.uk>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10*/
11
3a0ec259
KK		 12#ifndef __ASM_PLAT_CLOCK_H
13#define __ASM_PLAT_CLOCK_H __FILE__
14
c3391e36 15#include <linux/spinlock.h>
f86c6660 16#include <linux/clkdev.h>
c3391e36 17
b3bf41be
BD		 18struct clk;
19
20/**
21 * struct clk_ops - standard clock operations
22 * @set_rate: set the clock rate, see clk_set_rate().
23 * @get_rate: get the clock rate, see clk_get_rate().
24 * @round_rate: round a given clock rate, see clk_round_rate().
25 * @set_parent: set the clock's parent, see clk_set_parent().
26 *
27 * Group the common clock implementations together so that we
25985edc 28 * don't have to keep setting the same fields again. We leave
b3bf41be
BD		 29 * enable in struct clk.
30 *
31 * Adding an extra layer of indirection into the process should
32 * not be a problem as it is unlikely these operations are going
33 * to need to be called quickly.
34 */
35struct clk_ops {
36 int (*set_rate)(struct clk *c, unsigned long rate);
37 unsigned long (*get_rate)(struct clk *c);
38 unsigned long (*round_rate)(struct clk *c, unsigned long rate);
39 int (*set_parent)(struct clk *c, struct clk *parent);
40};
41
1da177e4
LT		 42struct clk {
43 struct list_head list;
44 struct module *owner;
45 struct clk *parent;
46 const char *name;
f86c6660 47 const char *devname;
1da177e4 48 int id;
2a513ce7 49 int usage;
1da177e4
LT		 50 unsigned long rate;
51 unsigned long ctrlbit;
d3468daa 52
b3bf41be 53 struct clk_ops *ops;
1da177e4 54 int (*enable)(struct clk *, int enable);
f86c6660 55 struct clk_lookup lookup;
436c3878
ADK		 56#if defined(CONFIG_PM_DEBUG) && defined(CONFIG_DEBUG_FS)
57 struct dentry *dent; /* For visible tree hierarchy */
58#endif
1da177e4
LT		 59};
60
61/* other clocks which may be registered by board support */
62
63extern struct clk s3c24xx_dclk0;
64extern struct clk s3c24xx_dclk1;
65extern struct clk s3c24xx_clkout0;
66extern struct clk s3c24xx_clkout1;
67extern struct clk s3c24xx_uclk;
68
36c64af4
BD		 69extern struct clk clk_usb_bus;
70
99c13853
BD		 71/* core clock support */
72
73extern struct clk clk_f;
74extern struct clk clk_h;
75extern struct clk clk_p;
513846f8 76extern struct clk clk_mpll;
99c13853 77extern struct clk clk_upll;
4b31d8b2 78extern struct clk clk_epll;
513846f8 79extern struct clk clk_xtal;
4b31d8b2
BD		 80extern struct clk clk_ext;
81
4083da3d
HS		 82/* S3C2443/S3C2416 specific clocks */
83extern struct clksrc_clk clk_epllref;
84extern struct clksrc_clk clk_esysclk;
85
d817468c
SN		 86/* S3C24XX UART clocks */
87extern struct clk s3c24xx_clk_uart0;
88extern struct clk s3c24xx_clk_uart1;
89extern struct clk s3c24xx_clk_uart2;
90
4b31d8b2 91/* S3C64XX specific clocks */
a03f7daf 92extern struct clk clk_h2;
4b31d8b2
BD		 93extern struct clk clk_27m;
94extern struct clk clk_48m;
05e021f0 95extern struct clk clk_xusbxti;
99c13853 96
ed276849
KK		 97extern int clk_default_setrate(struct clk *clk, unsigned long rate);
98extern struct clk_ops clk_ops_def_setrate;
99
1da177e4
LT		 100/* exports for arch/arm/mach-s3c2410
101 *
102 * Please DO NOT use these outside of arch/arm/mach-s3c2410
103*/
104
c3391e36 105extern spinlock_t clocks_lock;
36c64af4 106
99c13853
BD		 107extern int s3c2410_clkcon_enable(struct clk *clk, int enable);
108
1da177e4 109extern int s3c24xx_register_clock(struct clk *clk);
ce89c206 110extern int s3c24xx_register_clocks(struct clk **clk, int nr_clks);
1da177e4 111
1d9f13c4 112extern void s3c_register_clocks(struct clk *clk, int nr_clks);
4e04691b 113extern void s3c_disable_clocks(struct clk *clkp, int nr_clks);
1d9f13c4 114
e425382e
BD		 115extern int s3c24xx_register_baseclocks(unsigned long xtal);
116
1a0e8a52 117extern void s5p_register_clocks(unsigned long xtal_freq);
4b31d8b2 118
e425382e
BD		 119extern void s3c24xx_setup_clocks(unsigned long fclk,
120 unsigned long hclk,
121 unsigned long pclk);
122
123extern void s3c2410_setup_clocks(void);
124extern void s3c2412_setup_clocks(void);
125extern void s3c244x_setup_clocks(void);
e425382e 126
507164d2
HS		 127/* S3C2410 specific clock functions */
128
129extern int s3c2410_baseclk_add(void);
130
4083da3d
HS		 131/* S3C2443/S3C2416 specific clock functions */
132
133typedef unsigned int (*pll_fn)(unsigned int reg, unsigned int base);
134
135extern void s3c2443_common_setup_clocks(pll_fn get_mpll);
136extern void s3c2443_common_init_clocks(int xtal, pll_fn get_mpll,
137 unsigned int *divs, int nr_divs,
138 int divmask);
139
140extern int s3c2443_clkcon_enable_h(struct clk *clk, int enable);
141extern int s3c2443_clkcon_enable_p(struct clk *clk, int enable);
142extern int s3c2443_clkcon_enable_s(struct clk *clk, int enable);
143
cf18acf0
BD		 144/* S3C64XX specific functions and clocks */
145
146extern int s3c64xx_sclk_ctrl(struct clk *clk, int enable);
9d325f23 147
caf27307
MS		 148/* Global watchdog clock used by arch_wtd_reset() callback */
149
150extern struct clk *s3c2410_wdtclk;
3a0ec259
KK		 151
152#endif /* __ASM_PLAT_CLOCK_H */
Linux kernel - Deliverables
This page took 0.862141 seconds and 5 git commands to generate.