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a503059c | 1 | /* linux/arch/arm/plat-s3c/include/plat/clock.h |
1da177e4 LT |
2 | * |
3 | * Copyright (c) 2004-2005 Simtec Electronics | |
4 | * http://www.simtec.co.uk/products/SWLINUX/ | |
5 | * Written by Ben Dooks, <ben@simtec.co.uk> | |
6 | * | |
7 | * This program is free software; you can redistribute it and/or modify | |
8 | * it under the terms of the GNU General Public License version 2 as | |
9 | * published by the Free Software Foundation. | |
10 | */ | |
11 | ||
c3391e36 | 12 | #include <linux/spinlock.h> |
f86c6660 | 13 | #include <linux/clkdev.h> |
c3391e36 | 14 | |
b3bf41be BD |
15 | struct clk; |
16 | ||
17 | /** | |
18 | * struct clk_ops - standard clock operations | |
19 | * @set_rate: set the clock rate, see clk_set_rate(). | |
20 | * @get_rate: get the clock rate, see clk_get_rate(). | |
21 | * @round_rate: round a given clock rate, see clk_round_rate(). | |
22 | * @set_parent: set the clock's parent, see clk_set_parent(). | |
23 | * | |
24 | * Group the common clock implementations together so that we | |
25985edc | 25 | * don't have to keep setting the same fields again. We leave |
b3bf41be BD |
26 | * enable in struct clk. |
27 | * | |
28 | * Adding an extra layer of indirection into the process should | |
29 | * not be a problem as it is unlikely these operations are going | |
30 | * to need to be called quickly. | |
31 | */ | |
32 | struct clk_ops { | |
33 | int (*set_rate)(struct clk *c, unsigned long rate); | |
34 | unsigned long (*get_rate)(struct clk *c); | |
35 | unsigned long (*round_rate)(struct clk *c, unsigned long rate); | |
36 | int (*set_parent)(struct clk *c, struct clk *parent); | |
37 | }; | |
38 | ||
1da177e4 LT |
39 | struct clk { |
40 | struct list_head list; | |
41 | struct module *owner; | |
42 | struct clk *parent; | |
43 | const char *name; | |
f86c6660 | 44 | const char *devname; |
1da177e4 | 45 | int id; |
2a513ce7 | 46 | int usage; |
1da177e4 LT |
47 | unsigned long rate; |
48 | unsigned long ctrlbit; | |
d3468daa | 49 | |
b3bf41be | 50 | struct clk_ops *ops; |
1da177e4 | 51 | int (*enable)(struct clk *, int enable); |
f86c6660 | 52 | struct clk_lookup lookup; |
436c3878 ADK |
53 | #if defined(CONFIG_PM_DEBUG) && defined(CONFIG_DEBUG_FS) |
54 | struct dentry *dent; /* For visible tree hierarchy */ | |
55 | #endif | |
1da177e4 LT |
56 | }; |
57 | ||
58 | /* other clocks which may be registered by board support */ | |
59 | ||
60 | extern struct clk s3c24xx_dclk0; | |
61 | extern struct clk s3c24xx_dclk1; | |
62 | extern struct clk s3c24xx_clkout0; | |
63 | extern struct clk s3c24xx_clkout1; | |
64 | extern struct clk s3c24xx_uclk; | |
65 | ||
36c64af4 BD |
66 | extern struct clk clk_usb_bus; |
67 | ||
99c13853 BD |
68 | /* core clock support */ |
69 | ||
70 | extern struct clk clk_f; | |
71 | extern struct clk clk_h; | |
72 | extern struct clk clk_p; | |
513846f8 | 73 | extern struct clk clk_mpll; |
99c13853 | 74 | extern struct clk clk_upll; |
4b31d8b2 | 75 | extern struct clk clk_epll; |
513846f8 | 76 | extern struct clk clk_xtal; |
4b31d8b2 BD |
77 | extern struct clk clk_ext; |
78 | ||
79 | /* S3C64XX specific clocks */ | |
a03f7daf | 80 | extern struct clk clk_h2; |
4b31d8b2 BD |
81 | extern struct clk clk_27m; |
82 | extern struct clk clk_48m; | |
05e021f0 | 83 | extern struct clk clk_xusbxti; |
99c13853 | 84 | |
ed276849 KK |
85 | extern int clk_default_setrate(struct clk *clk, unsigned long rate); |
86 | extern struct clk_ops clk_ops_def_setrate; | |
87 | ||
1da177e4 LT |
88 | /* exports for arch/arm/mach-s3c2410 |
89 | * | |
90 | * Please DO NOT use these outside of arch/arm/mach-s3c2410 | |
91 | */ | |
92 | ||
c3391e36 | 93 | extern spinlock_t clocks_lock; |
36c64af4 | 94 | |
99c13853 BD |
95 | extern int s3c2410_clkcon_enable(struct clk *clk, int enable); |
96 | ||
1da177e4 | 97 | extern int s3c24xx_register_clock(struct clk *clk); |
ce89c206 | 98 | extern int s3c24xx_register_clocks(struct clk **clk, int nr_clks); |
1da177e4 | 99 | |
1d9f13c4 | 100 | extern void s3c_register_clocks(struct clk *clk, int nr_clks); |
4e04691b | 101 | extern void s3c_disable_clocks(struct clk *clkp, int nr_clks); |
1d9f13c4 | 102 | |
e425382e BD |
103 | extern int s3c24xx_register_baseclocks(unsigned long xtal); |
104 | ||
1a0e8a52 | 105 | extern void s5p_register_clocks(unsigned long xtal_freq); |
4b31d8b2 | 106 | |
e425382e BD |
107 | extern void s3c24xx_setup_clocks(unsigned long fclk, |
108 | unsigned long hclk, | |
109 | unsigned long pclk); | |
110 | ||
111 | extern void s3c2410_setup_clocks(void); | |
112 | extern void s3c2412_setup_clocks(void); | |
113 | extern void s3c244x_setup_clocks(void); | |
114 | extern void s3c2443_setup_clocks(void); | |
115 | ||
cf18acf0 BD |
116 | /* S3C64XX specific functions and clocks */ |
117 | ||
118 | extern int s3c64xx_sclk_ctrl(struct clk *clk, int enable); | |
9d325f23 BD |
119 | |
120 | /* Init for pwm clock code */ | |
121 | ||
122 | extern void s3c_pwmclk_init(void); | |
123 |