[deliverable/linux.git] / arch / arm / plat-samsung / include / plat / cpu-freq-core.h

/* arch/arm/plat-samsung/include/plat/cpu-freq-core.h
 *
 * Copyright (c) 2006-2009 Simtec Electronics
 *	http://armlinux.simtec.co.uk/
 *	Ben Dooks <ben@simtec.co.uk>
 *
 * S3C CPU frequency scaling support - core support
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
*/

#include <plat/cpu-freq.h>

struct seq_file;

#define MAX_BANKS (8)
#define S3C2412_MAX_IO	(8)

/**
 * struct s3c2410_iobank_timing - IO bank timings for S3C2410 style timings
 * @bankcon: The cached version of settings in this structure.
 * @tacp:
 * @tacs: Time from address valid to nCS asserted.
 * @tcos: Time from nCS asserted to nOE or nWE asserted.
 * @tacc: Time that nOE or nWE is asserted.
 * @tcoh: Time nCS is held after nOE or nWE are released.
 * @tcah: Time address is held for after
 * @nwait_en: Whether nWAIT is enabled for this bank.
 *
 * This structure represents the IO timings for a S3C2410 style IO bank
 * used by the CPU frequency support if it needs to change the settings
 * of the IO.
 */
struct s3c2410_iobank_timing {
	unsigned long	bankcon;
	unsigned int	tacp;
	unsigned int	tacs;
	unsigned int	tcos;
	unsigned int	tacc;
	unsigned int	tcoh;		/* nCS hold afrer nOE/nWE */
	unsigned int	tcah;		/* Address hold after nCS */
	unsigned char	nwait_en;	/* nWait enabled for bank. */
};

/**
 * struct s3c2412_iobank_timing - io timings for PL092 (S3C2412) style IO
 * @idcy: The idle cycle time between transactions.
 * @wstrd: nCS release to end of read cycle.
 * @wstwr: nCS release to end of write cycle.
 * @wstoen: nCS assertion to nOE assertion time.
 * @wstwen: nCS assertion to nWE assertion time.
 * @wstbrd: Burst ready delay.
 * @smbidcyr: Register cache for smbidcyr value.
 * @smbwstrd: Register cache for smbwstrd value.
 * @smbwstwr: Register cache for smbwstwr value.
 * @smbwstoen: Register cache for smbwstoen value.
 * @smbwstwen: Register cache for smbwstwen value.
 * @smbwstbrd: Register cache for smbwstbrd value.
 *
 * Timing information for a IO bank on an S3C2412 or similar system which
 * uses a PL093 block.
 */
struct s3c2412_iobank_timing {
	unsigned int	idcy;
	unsigned int	wstrd;
	unsigned int	wstwr;
	unsigned int	wstoen;
	unsigned int	wstwen;
	unsigned int	wstbrd;

	/* register cache */
	unsigned char	smbidcyr;
	unsigned char	smbwstrd;
	unsigned char	smbwstwr;
	unsigned char	smbwstoen;
	unsigned char	smbwstwen;
	unsigned char	smbwstbrd;
};

union s3c_iobank {
	struct s3c2410_iobank_timing	*io_2410;
	struct s3c2412_iobank_timing	*io_2412;
};

/**
 * struct s3c_iotimings - Chip IO timings holder
 * @bank: The timings for each IO bank.
 */
struct s3c_iotimings {
	union s3c_iobank	bank[MAX_BANKS];
};

/**
 * struct s3c_plltab - PLL table information.
 * @vals: List of PLL values.
 * @size: Size of the PLL table @vals.
 */
struct s3c_plltab {
	struct s3c_pllval	*vals;
	int			 size;
};

/**
 * struct s3c_cpufreq_config - current cpu frequency configuration
 * @freq: The current settings for the core clocks.
 * @max: Maxium settings, derived from core, board and user settings.
 * @pll: The PLL table entry for the current PLL settings.
 * @divs: The divisor settings for the core clocks.
 * @info: The current core driver information.
 * @board: The information for the board we are running on.
 * @lock_pll: Set if the PLL settings cannot be changed.
 *
 * This is for the core drivers that need to know information about
 * the current settings and values. It should not be needed by any
 * device drivers.
*/
struct s3c_cpufreq_config {
	struct s3c_freq		freq;
	struct s3c_freq		max;
	struct clk		*mpll;
	struct cpufreq_frequency_table pll;
	struct s3c_clkdivs	divs;
	struct s3c_cpufreq_info *info;	/* for core, not drivers */
	struct s3c_cpufreq_board *board;

	unsigned int	lock_pll:1;
};

/**
 * struct s3c_cpufreq_info - Information for the CPU frequency driver.
 * @name: The name of this implementation.
 * @max: The maximum frequencies for the system.
 * @latency: Transition latency to give to cpufreq.
 * @locktime_m: The lock-time in uS for the MPLL.
 * @locktime_u: The lock-time in uS for the UPLL.
 * @locttime_bits: The number of bits each LOCKTIME field.
 * @need_pll: Set if this driver needs to change the PLL values to achieve
 *	any frequency changes. This is really only need by devices like the
 *	S3C2410 where there is no or limited divider between the PLL and the
 *	ARMCLK.
 * @resume_clocks: Update the clocks on resume.
 * @get_iotiming: Get the current IO timing data, mainly for use at start.
 * @set_iotiming: Update the IO timings from the cached copies calculated
 *	from the @calc_iotiming entry when changing the frequency.
 * @calc_iotiming: Calculate and update the cached copies of the IO timings
 *	from the newly calculated frequencies.
 * @calc_freqtable: Calculate (fill in) the given frequency table from the
 *	current frequency configuration. If the table passed in is NULL,
 *	then the return is the number of elements to be filled for allocation
 *	of the table.
 * @set_refresh: Set the memory refresh configuration.
 * @set_fvco: Set the PLL frequencies.
 * @set_divs: Update the clock divisors.
 * @calc_divs: Calculate the clock divisors.
 */
struct s3c_cpufreq_info {
	const char		*name;
	struct s3c_freq		max;

	unsigned int		latency;

	unsigned int		locktime_m;
	unsigned int		locktime_u;
	unsigned char		locktime_bits;

	unsigned int		need_pll:1;

	/* driver routines */

	void		(*resume_clocks)(void);

	int		(*get_iotiming)(struct s3c_cpufreq_config *cfg,
					struct s3c_iotimings *timings);

	void		(*set_iotiming)(struct s3c_cpufreq_config *cfg,
					struct s3c_iotimings *timings);

	int		(*calc_iotiming)(struct s3c_cpufreq_config *cfg,
					 struct s3c_iotimings *timings);

	int		(*calc_freqtable)(struct s3c_cpufreq_config *cfg,
					  struct cpufreq_frequency_table *t,
					  size_t table_size);

	void		(*debug_io_show)(struct seq_file *seq,
					 struct s3c_cpufreq_config *cfg,
					 union s3c_iobank *iob);

	void		(*set_refresh)(struct s3c_cpufreq_config *cfg);
	void		(*set_fvco)(struct s3c_cpufreq_config *cfg);
	void		(*set_divs)(struct s3c_cpufreq_config *cfg);
	int		(*calc_divs)(struct s3c_cpufreq_config *cfg);
};

extern int s3c_cpufreq_register(struct s3c_cpufreq_info *info);

extern int s3c_plltab_register(struct cpufreq_frequency_table *plls,
			       unsigned int plls_no);

/* exports and utilities for debugfs */
extern struct s3c_cpufreq_config *s3c_cpufreq_getconfig(void);
extern struct s3c_iotimings *s3c_cpufreq_getiotimings(void);

#ifdef CONFIG_ARM_S3C24XX_CPUFREQ_DEBUGFS
#define s3c_cpufreq_debugfs_call(x) x
#else
#define s3c_cpufreq_debugfs_call(x) NULL
#endif

/* Useful utility functions. */

extern struct clk *s3c_cpufreq_clk_get(struct device *, const char *);

/* S3C2410 and compatible exported functions */

extern void s3c2410_cpufreq_setrefresh(struct s3c_cpufreq_config *cfg);
extern void s3c2410_set_fvco(struct s3c_cpufreq_config *cfg);

#ifdef CONFIG_S3C2410_IOTIMING
extern void s3c2410_iotiming_debugfs(struct seq_file *seq,
				     struct s3c_cpufreq_config *cfg,
				     union s3c_iobank *iob);

extern int s3c2410_iotiming_calc(struct s3c_cpufreq_config *cfg,
				 struct s3c_iotimings *iot);

extern int s3c2410_iotiming_get(struct s3c_cpufreq_config *cfg,
				struct s3c_iotimings *timings);

extern void s3c2410_iotiming_set(struct s3c_cpufreq_config *cfg,
				 struct s3c_iotimings *iot);
#else
#define s3c2410_iotiming_debugfs NULL
#define s3c2410_iotiming_calc NULL
#define s3c2410_iotiming_get NULL
#define s3c2410_iotiming_set NULL
#endif /* CONFIG_S3C2410_IOTIMING */

/* S3C2412 compatible routines */

#ifdef CONFIG_S3C2412_IOTIMING
extern void s3c2412_iotiming_debugfs(struct seq_file *seq,
				     struct s3c_cpufreq_config *cfg,
				     union s3c_iobank *iob);

extern int s3c2412_iotiming_get(struct s3c_cpufreq_config *cfg,
				struct s3c_iotimings *timings);

extern int s3c2412_iotiming_calc(struct s3c_cpufreq_config *cfg,
				 struct s3c_iotimings *iot);

extern void s3c2412_iotiming_set(struct s3c_cpufreq_config *cfg,
				 struct s3c_iotimings *iot);
#else
#define s3c2412_iotiming_debugfs NULL
#define s3c2412_iotiming_calc NULL
#define s3c2412_iotiming_get NULL
#define s3c2412_iotiming_set NULL
#endif /* CONFIG_S3C2412_IOTIMING */

#ifdef CONFIG_ARM_S3C24XX_CPUFREQ_DEBUG
#define s3c_freq_dbg(x...) printk(KERN_INFO x)
#else
#define s3c_freq_dbg(x...) do { if (0) printk(x); } while (0)
#endif /* CONFIG_ARM_S3C24XX_CPUFREQ_DEBUG */

#ifdef CONFIG_ARM_S3C24XX_CPUFREQ_IODEBUG
#define s3c_freq_iodbg(x...) printk(KERN_INFO x)
#else
#define s3c_freq_iodbg(x...) do { if (0) printk(x); } while (0)
#endif /* CONFIG_ARM_S3C24XX_CPUFREQ_IODEBUG */

static inline int s3c_cpufreq_addfreq(struct cpufreq_frequency_table *table,
				      int index, size_t table_size,
				      unsigned int freq)
{
	if (index < 0)
		return index;

	if (table) {
		if (index >= table_size)
			return -ENOMEM;

		s3c_freq_dbg("%s: { %d = %u kHz }\n",
			     __func__, index, freq);

		table[index].driver_data = index;
		table[index].frequency = freq;
	}

	return index + 1;
}
Commit	Line	Data
dc98e414	1	/* arch/arm/plat-samsung/include/plat/cpu-freq-core.h
2e4ea6e8	2	*
ccae941e	3	* Copyright (c) 2006-2009 Simtec Electronics
2e4ea6e8 BD	4	* http://armlinux.simtec.co.uk/
	5	* Ben Dooks <ben@simtec.co.uk>
	6	*
	7	* S3C CPU frequency scaling support - core support
	8	*
	9	* This program is free software; you can redistribute it and/or modify
	10	* it under the terms of the GNU General Public License version 2 as
	11	* published by the Free Software Foundation.
	12	*/
	13
	14	#include <plat/cpu-freq.h>
	15
e6d197a6 BD	16	struct seq_file;
e6d197a6 BD	17
2e4ea6e8 BD	18	#define MAX_BANKS (8)
	19	#define S3C2412_MAX_IO (8)
	20
	21	/**
	22	* struct s3c2410_iobank_timing - IO bank timings for S3C2410 style timings
	23	* @bankcon: The cached version of settings in this structure.
	24	* @tacp:
	25	* @tacs: Time from address valid to nCS asserted.
	26	* @tcos: Time from nCS asserted to nOE or nWE asserted.
	27	* @tacc: Time that nOE or nWE is asserted.
	28	* @tcoh: Time nCS is held after nOE or nWE are released.
	29	* @tcah: Time address is held for after
	30	* @nwait_en: Whether nWAIT is enabled for this bank.
	31	*
	32	* This structure represents the IO timings for a S3C2410 style IO bank
	33	* used by the CPU frequency support if it needs to change the settings
	34	* of the IO.
	35	*/
	36	struct s3c2410_iobank_timing {
	37	unsigned long bankcon;
	38	unsigned int tacp;
	39	unsigned int tacs;
	40	unsigned int tcos;
	41	unsigned int tacc;
	42	unsigned int tcoh; /* nCS hold afrer nOE/nWE */
	43	unsigned int tcah; /* Address hold after nCS */
	44	unsigned char nwait_en; /* nWait enabled for bank. */
	45	};
	46
140780ab BD	47	/**
	48	* struct s3c2412_iobank_timing - io timings for PL092 (S3C2412) style IO
	49	* @idcy: The idle cycle time between transactions.
	50	* @wstrd: nCS release to end of read cycle.
	51	* @wstwr: nCS release to end of write cycle.
	52	* @wstoen: nCS assertion to nOE assertion time.
	53	* @wstwen: nCS assertion to nWE assertion time.
	54	* @wstbrd: Burst ready delay.
	55	* @smbidcyr: Register cache for smbidcyr value.
	56	* @smbwstrd: Register cache for smbwstrd value.
	57	* @smbwstwr: Register cache for smbwstwr value.
	58	* @smbwstoen: Register cache for smbwstoen value.
	59	* @smbwstwen: Register cache for smbwstwen value.
	60	* @smbwstbrd: Register cache for smbwstbrd value.
	61	*
	62	* Timing information for a IO bank on an S3C2412 or similar system which
	63	* uses a PL093 block.
	64	*/
	65	struct s3c2412_iobank_timing {
	66	unsigned int idcy;
	67	unsigned int wstrd;
	68	unsigned int wstwr;
	69	unsigned int wstoen;
	70	unsigned int wstwen;
	71	unsigned int wstbrd;
	72
	73	/* register cache */
	74	unsigned char smbidcyr;
	75	unsigned char smbwstrd;
	76	unsigned char smbwstwr;
	77	unsigned char smbwstoen;
	78	unsigned char smbwstwen;
	79	unsigned char smbwstbrd;
	80	};
	81
2e4ea6e8	82	union s3c_iobank {
140780ab BD	83	struct s3c2410_iobank_timing *io_2410;
140780ab BD	84	struct s3c2412_iobank_timing *io_2412;
2e4ea6e8 BD	85	};
	86
	87	/**
	88	* struct s3c_iotimings - Chip IO timings holder
	89	* @bank: The timings for each IO bank.
	90	*/
	91	struct s3c_iotimings {
	92	union s3c_iobank bank[MAX_BANKS];
	93	};
	94
	95	/**
	96	* struct s3c_plltab - PLL table information.
	97	* @vals: List of PLL values.
	98	* @size: Size of the PLL table @vals.
	99	*/
	100	struct s3c_plltab {
	101	struct s3c_pllval *vals;
	102	int size;
	103	};
	104
d6fc87d3 BD	105	/**
	106	* struct s3c_cpufreq_config - current cpu frequency configuration
	107	* @freq: The current settings for the core clocks.
	108	* @max: Maxium settings, derived from core, board and user settings.
	109	* @pll: The PLL table entry for the current PLL settings.
	110	* @divs: The divisor settings for the core clocks.
	111	* @info: The current core driver information.
	112	* @board: The information for the board we are running on.
	113	* @lock_pll: Set if the PLL settings cannot be changed.
	114	*
	115	* This is for the core drivers that need to know information about
	116	* the current settings and values. It should not be needed by any
	117	* device drivers.
	118	*/
	119	struct s3c_cpufreq_config {
	120	struct s3c_freq freq;
	121	struct s3c_freq max;
d8b53257	122	struct clk *mpll;
d6fc87d3 BD	123	struct cpufreq_frequency_table pll;
	124	struct s3c_clkdivs divs;
	125	struct s3c_cpufreq_info info; / for core, not drivers */
	126	struct s3c_cpufreq_board *board;
	127
	128	unsigned int lock_pll:1;
	129	};
	130
2e4ea6e8 BD	131	/**
	132	* struct s3c_cpufreq_info - Information for the CPU frequency driver.
	133	* @name: The name of this implementation.
	134	* @max: The maximum frequencies for the system.
	135	* @latency: Transition latency to give to cpufreq.
	136	* @locktime_m: The lock-time in uS for the MPLL.
	137	* @locktime_u: The lock-time in uS for the UPLL.
	138	* @locttime_bits: The number of bits each LOCKTIME field.
3ad2f3fb	139	* @need_pll: Set if this driver needs to change the PLL values to achieve
2e4ea6e8 BD	140	* any frequency changes. This is really only need by devices like the
	141	* S3C2410 where there is no or limited divider between the PLL and the
	142	* ARMCLK.
	143	* @resume_clocks: Update the clocks on resume.
	144	* @get_iotiming: Get the current IO timing data, mainly for use at start.
	145	* @set_iotiming: Update the IO timings from the cached copies calculated
	146	* from the @calc_iotiming entry when changing the frequency.
	147	* @calc_iotiming: Calculate and update the cached copies of the IO timings
	148	* from the newly calculated frequencies.
	149	* @calc_freqtable: Calculate (fill in) the given frequency table from the
	150	* current frequency configuration. If the table passed in is NULL,
	151	* then the return is the number of elements to be filled for allocation
	152	* of the table.
	153	* @set_refresh: Set the memory refresh configuration.
	154	* @set_fvco: Set the PLL frequencies.
	155	* @set_divs: Update the clock divisors.
	156	* @calc_divs: Calculate the clock divisors.
	157	*/
	158	struct s3c_cpufreq_info {
	159	const char *name;
	160	struct s3c_freq max;
	161
	162	unsigned int latency;
	163
	164	unsigned int locktime_m;
	165	unsigned int locktime_u;
	166	unsigned char locktime_bits;
	167
	168	unsigned int need_pll:1;
	169
	170	/* driver routines */
	171
	172	void (*resume_clocks)(void);
	173
	174	int (get_iotiming)(struct s3c_cpufreq_config cfg,
	175	struct s3c_iotimings *timings);
	176
	177	void (set_iotiming)(struct s3c_cpufreq_config cfg,
	178	struct s3c_iotimings *timings);
	179
	180	int (calc_iotiming)(struct s3c_cpufreq_config cfg,
	181	struct s3c_iotimings *timings);
	182
	183	int (calc_freqtable)(struct s3c_cpufreq_config cfg,
	184	struct cpufreq_frequency_table *t,
	185	size_t table_size);
	186
e6d197a6 BD	187	void (debug_io_show)(struct seq_file seq,
	188	struct s3c_cpufreq_config *cfg,
	189	union s3c_iobank *iob);
	190
2e4ea6e8 BD	191	void (set_refresh)(struct s3c_cpufreq_config cfg);
	192	void (set_fvco)(struct s3c_cpufreq_config cfg);
	193	void (set_divs)(struct s3c_cpufreq_config cfg);
	194	int (calc_divs)(struct s3c_cpufreq_config cfg);
	195	};
	196
	197	extern int s3c_cpufreq_register(struct s3c_cpufreq_info *info);
	198
dc98e414 KK	199	extern int s3c_plltab_register(struct cpufreq_frequency_table *plls,
dc98e414 KK	200	unsigned int plls_no);
2e4ea6e8	201
e6d197a6 BD	202	/* exports and utilities for debugfs */
	203	extern struct s3c_cpufreq_config *s3c_cpufreq_getconfig(void);
	204	extern struct s3c_iotimings *s3c_cpufreq_getiotimings(void);
	205
f023f8dd	206	#ifdef CONFIG_ARM_S3C24XX_CPUFREQ_DEBUGFS
e6d197a6 BD	207	#define s3c_cpufreq_debugfs_call(x) x
	208	#else
	209	#define s3c_cpufreq_debugfs_call(x) NULL
	210	#endif
	211
2e4ea6e8 BD	212	/* Useful utility functions. */
	213
	214	extern struct clk s3c_cpufreq_clk_get(struct device , const char *);
	215
	216	/* S3C2410 and compatible exported functions */
	217
	218	extern void s3c2410_cpufreq_setrefresh(struct s3c_cpufreq_config *cfg);
2e31de65	219	extern void s3c2410_set_fvco(struct s3c_cpufreq_config *cfg);
2e4ea6e8	220
2e31de65	221	#ifdef CONFIG_S3C2410_IOTIMING
baaf939d DK	222	extern void s3c2410_iotiming_debugfs(struct seq_file *seq,
	223	struct s3c_cpufreq_config *cfg,
	224	union s3c_iobank *iob);
	225
2e4ea6e8 BD	226	extern int s3c2410_iotiming_calc(struct s3c_cpufreq_config *cfg,
	227	struct s3c_iotimings *iot);
	228
	229	extern int s3c2410_iotiming_get(struct s3c_cpufreq_config *cfg,
	230	struct s3c_iotimings *timings);
	231
	232	extern void s3c2410_iotiming_set(struct s3c_cpufreq_config *cfg,
	233	struct s3c_iotimings *iot);
2e31de65	234	#else
baaf939d	235	#define s3c2410_iotiming_debugfs NULL
2e31de65 BD	236	#define s3c2410_iotiming_calc NULL
	237	#define s3c2410_iotiming_get NULL
	238	#define s3c2410_iotiming_set NULL
	239	#endif /* CONFIG_S3C2410_IOTIMING */
2e4ea6e8	240
140780ab BD	241	/* S3C2412 compatible routines */
140780ab BD	242
baaf939d DK	243	#ifdef CONFIG_S3C2412_IOTIMING
	244	extern void s3c2412_iotiming_debugfs(struct seq_file *seq,
	245	struct s3c_cpufreq_config *cfg,
	246	union s3c_iobank *iob);
140780ab BD	247
	248	extern int s3c2412_iotiming_get(struct s3c_cpufreq_config *cfg,
	249	struct s3c_iotimings *timings);
	250
	251	extern int s3c2412_iotiming_calc(struct s3c_cpufreq_config *cfg,
	252	struct s3c_iotimings *iot);
	253
	254	extern void s3c2412_iotiming_set(struct s3c_cpufreq_config *cfg,
	255	struct s3c_iotimings *iot);
baaf939d DK	256	#else
	257	#define s3c2412_iotiming_debugfs NULL
	258	#define s3c2412_iotiming_calc NULL
	259	#define s3c2412_iotiming_get NULL
	260	#define s3c2412_iotiming_set NULL
	261	#endif /* CONFIG_S3C2412_IOTIMING */
140780ab	262
f023f8dd	263	#ifdef CONFIG_ARM_S3C24XX_CPUFREQ_DEBUG
2e4ea6e8 BD	264	#define s3c_freq_dbg(x...) printk(KERN_INFO x)
	265	#else
	266	#define s3c_freq_dbg(x...) do { if (0) printk(x); } while (0)
f023f8dd	267	#endif /* CONFIG_ARM_S3C24XX_CPUFREQ_DEBUG */
2e4ea6e8	268
f023f8dd	269	#ifdef CONFIG_ARM_S3C24XX_CPUFREQ_IODEBUG
2e4ea6e8 BD	270	#define s3c_freq_iodbg(x...) printk(KERN_INFO x)
	271	#else
	272	#define s3c_freq_iodbg(x...) do { if (0) printk(x); } while (0)
f023f8dd	273	#endif /* CONFIG_ARM_S3C24XX_CPUFREQ_IODEBUG */
2e4ea6e8 BD	274
	275	static inline int s3c_cpufreq_addfreq(struct cpufreq_frequency_table *table,
	276	int index, size_t table_size,
	277	unsigned int freq)
	278	{
	279	if (index < 0)
	280	return index;
	281
	282	if (table) {
	283	if (index >= table_size)
	284	return -ENOMEM;
	285
	286	s3c_freq_dbg("%s: { %d = %u kHz }\n",
	287	__func__, index, freq);
	288
50701588	289	table[index].driver_data = index;
2e4ea6e8 BD	290	table[index].frequency = freq;
	291	}
	292
	293	return index + 1;
	294	}