projects / deliverable / linux.git / blame
| Commit | Line | Data |
|---|---|---|
| e90a0f3c | 1 | /* linux/arch/arm/plat-samsung/include/plat/irqs.h |
| b7db51be KK |
2 | * |
| 3 | * Copyright (c) 2009 Samsung Electronics Co., Ltd. | |
| 4 | * http://www.samsung.com/ | |
| 5 | * | |
| 6 | * S5P Common IRQ support | |
| 7 | * | |
| 8 | * This program is free software; you can redistribute it and/or modify | |
| 9 | * it under the terms of the GNU General Public License version 2 as | |
| 10 | * published by the Free Software Foundation. | |
| 11 | */ | |
| 12 | ||
| e90a0f3c KK |
13 | #ifndef __PLAT_SAMSUNG_IRQS_H |
| 14 | #define __PLAT_SAMSUNG_IRQS_H __FILE__ | |
| b7db51be KK |
15 | |
| 16 | /* we keep the first set of CPU IRQs out of the range of | |
| 17 | * the ISA space, so that the PC104 has them to itself | |
| 18 | * and we don't end up having to do horrible things to the | |
| 19 | * standard ISA drivers.... | |
| 20 | * | |
| 21 | * note, since we're using the VICs, our start must be a | |
| 22 | * mulitple of 32 to allow the common code to work | |
| 23 | */ | |
| 24 | ||
| 25 | #define S5P_IRQ_OFFSET (32) | |
| 26 | ||
| 27 | #define S5P_IRQ(x) ((x) + S5P_IRQ_OFFSET) | |
| 28 | ||
| 29 | #define S5P_VIC0_BASE S5P_IRQ(0) | |
| 30 | #define S5P_VIC1_BASE S5P_IRQ(32) | |
| d9f18a98 | 31 | #define S5P_VIC2_BASE S5P_IRQ(64) |
| 2c798557 | 32 | #define S5P_VIC3_BASE S5P_IRQ(96) |
| b7db51be | 33 | |
| 81317960 KK |
34 | #define VIC_BASE(x) (S5P_VIC0_BASE + ((x)*32)) |
| 35 | ||
| b7db51be KK |
36 | #define IRQ_VIC0_BASE S5P_VIC0_BASE |
| 37 | #define IRQ_VIC1_BASE S5P_VIC1_BASE | |
| d9f18a98 | 38 | #define IRQ_VIC2_BASE S5P_VIC2_BASE |
| b7db51be | 39 | |
| b7db51be KK |
40 | /* VIC based IRQs */ |
| 41 | ||
| 42 | #define S5P_IRQ_VIC0(x) (S5P_VIC0_BASE + (x)) | |
| 43 | #define S5P_IRQ_VIC1(x) (S5P_VIC1_BASE + (x)) | |
| d9f18a98 | 44 | #define S5P_IRQ_VIC2(x) (S5P_VIC2_BASE + (x)) |
| 2c798557 | 45 | #define S5P_IRQ_VIC3(x) (S5P_VIC3_BASE + (x)) |
| b7db51be | 46 | |
| 5fae4058 PB |
47 | #define IRQ_EINT(x) ((x) < 16 ? ((x) + S5P_EINT_BASE1) \ |
| 48 | : ((x) - 16 + S5P_EINT_BASE2)) | |
| 49 | ||
| 50 | #define EINT_OFFSET(irq) ((irq) < S5P_EINT_BASE2 ? \ | |
| 51 | ((irq) - S5P_EINT_BASE1) : \ | |
| 52 | ((irq) + 16 - S5P_EINT_BASE2)) | |
| 53 | ||
| dc6c0ca3 KK |
54 | #define IRQ_EINT_BIT(x) EINT_OFFSET(x) |
| 55 | ||
| 170a4617 MS |
56 | /* Typically only a few gpio chips require gpio interrupt support. |
| 57 | To avoid memory waste irq descriptors are allocated only for | |
| 58 | S5P_GPIOINT_GROUP_COUNT chips, each with total number of | |
| 59 | S5P_GPIOINT_GROUP_SIZE pins/irqs. Each GPIOINT group can be assiged | |
| 60 | to any gpio chip with the s5p_register_gpio_interrupt() function */ | |
| 61 | #define S5P_GPIOINT_GROUP_COUNT 4 | |
| 62 | #define S5P_GPIOINT_GROUP_SIZE 8 | |
| 63 | #define S5P_GPIOINT_COUNT (S5P_GPIOINT_GROUP_COUNT * S5P_GPIOINT_GROUP_SIZE) | |
| 64 | ||
| 9adf5d22 MS |
65 | /* IRQ types common for all s5p platforms */ |
| 66 | #define S5P_IRQ_TYPE_LEVEL_LOW (0x00) | |
| 67 | #define S5P_IRQ_TYPE_LEVEL_HIGH (0x01) | |
| 68 | #define S5P_IRQ_TYPE_EDGE_FALLING (0x02) | |
| 69 | #define S5P_IRQ_TYPE_EDGE_RISING (0x03) | |
| 70 | #define S5P_IRQ_TYPE_EDGE_BOTH (0x04) | |
| 71 | ||
| e90a0f3c | 72 | #endif /* __PLAT_SAMSUNG_IRQS_H */ |