projects / deliverable / linux.git / blame
| Commit | Line | Data |
|---|---|---|
| e90a0f3c | 1 | /* linux/arch/arm/plat-samsung/include/plat/s5p-clock.h |
| 1a0e8a52 | 2 | * |
| 3109e550 KK |
3 | * Copyright (c) 2009-2010 Samsung Electronics Co., Ltd. |
| 4 | * http://www.samsung.com | |
| 1a0e8a52 KK |
5 | * |
| 6 | * Header file for s5p clock support | |
| 7 | * | |
| 8 | * This program is free software; you can redistribute it and/or modify | |
| 9 | * it under the terms of the GNU General Public License version 2 as | |
| 10 | * published by the Free Software Foundation. | |
| 11 | */ | |
| 12 | ||
| 13 | #ifndef __ASM_PLAT_S5P_CLOCK_H | |
| 14 | #define __ASM_PLAT_S5P_CLOCK_H __FILE__ | |
| 15 | ||
| 16 | #include <linux/clk.h> | |
| 17 | ||
| 18 | #define GET_DIV(clk, field) ((((clk) & field##_MASK) >> field##_SHIFT) + 1) | |
| 19 | ||
| 20 | #define clk_fin_apll clk_ext_xtal_mux | |
| 87b3c6ef KK |
21 | #define clk_fin_bpll clk_ext_xtal_mux |
| 22 | #define clk_fin_cpll clk_ext_xtal_mux | |
| 1a0e8a52 KK |
23 | #define clk_fin_mpll clk_ext_xtal_mux |
| 24 | #define clk_fin_epll clk_ext_xtal_mux | |
| 3109e550 | 25 | #define clk_fin_dpll clk_ext_xtal_mux |
| 0c1945d3 | 26 | #define clk_fin_vpll clk_ext_xtal_mux |
| a443a637 | 27 | #define clk_fin_hpll clk_ext_xtal_mux |
| 1a0e8a52 KK |
28 | |
| 29 | extern struct clk clk_ext_xtal_mux; | |
| f001d5b2 | 30 | extern struct clk clk_xusbxti; |
| 1a0e8a52 | 31 | extern struct clk clk_48m; |
| a443a637 | 32 | extern struct clk s5p_clk_27m; |
| 1a0e8a52 | 33 | extern struct clk clk_fout_apll; |
| 87b3c6ef | 34 | extern struct clk clk_fout_bpll; |
| 57b317f9 | 35 | extern struct clk clk_fout_bpll_div2; |
| 87b3c6ef | 36 | extern struct clk clk_fout_cpll; |
| 1a0e8a52 | 37 | extern struct clk clk_fout_mpll; |
| 57b317f9 | 38 | extern struct clk clk_fout_mpll_div2; |
| 1a0e8a52 | 39 | extern struct clk clk_fout_epll; |
| 3109e550 | 40 | extern struct clk clk_fout_dpll; |
| f445dbd5 | 41 | extern struct clk clk_fout_vpll; |
| 1a0e8a52 | 42 | extern struct clk clk_arm; |
| 0c1945d3 | 43 | extern struct clk clk_vpll; |
| 1a0e8a52 KK |
44 | |
| 45 | extern struct clksrc_sources clk_src_apll; | |
| 87b3c6ef | 46 | extern struct clksrc_sources clk_src_bpll; |
| 57b317f9 | 47 | extern struct clksrc_sources clk_src_bpll_fout; |
| 87b3c6ef | 48 | extern struct clksrc_sources clk_src_cpll; |
| 1a0e8a52 | 49 | extern struct clksrc_sources clk_src_mpll; |
| 57b317f9 | 50 | extern struct clksrc_sources clk_src_mpll_fout; |
| 1a0e8a52 | 51 | extern struct clksrc_sources clk_src_epll; |
| 3109e550 | 52 | extern struct clksrc_sources clk_src_dpll; |
| 1a0e8a52 | 53 | |
| 1a0e8a52 KK |
54 | extern int s5p_gatectrl(void __iomem *reg, struct clk *clk, int enable); |
| 55 | ||
| d4b34c6c SY |
56 | /* Common EPLL operations for S5P platform */ |
| 57 | extern int s5p_epll_enable(struct clk *clk, int enable); | |
| 58 | extern unsigned long s5p_epll_get_rate(struct clk *clk); | |
| 59 | ||
| b8529ec1 | 60 | /* SPDIF clk operations common for S5PV210/C110 and Exynos4 */ |
| 65f5eaa2 NKC |
61 | extern int s5p_spdif_set_rate(struct clk *clk, unsigned long rate); |
| 62 | extern unsigned long s5p_spdif_get_rate(struct clk *clk); | |
| 63 | ||
| 64 | extern struct clk_ops s5p_sclk_spdif_ops; | |
| 1a0e8a52 | 65 | #endif /* __ASM_PLAT_S5P_CLOCK_H */ |