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3db3ae5e KK |
1 | /* linux/arch/arm/plat-samsung/include/plat/sdhci.h |
2 | * | |
3 | * Copyright (c) 2011 Samsung Electronics Co., Ltd. | |
4 | * http://www.samsung.com | |
5cc7fd88 BD |
5 | * |
6 | * Copyright 2008 Openmoko, Inc. | |
7 | * Copyright 2008 Simtec Electronics | |
8 | * http://armlinux.simtec.co.uk/ | |
9 | * Ben Dooks <ben@simtec.co.uk> | |
10 | * | |
11 | * S3C Platform - SDHCI (HSMMC) platform data definitions | |
12 | * | |
13 | * This program is free software; you can redistribute it and/or modify | |
14 | * it under the terms of the GNU General Public License version 2 as | |
15 | * published by the Free Software Foundation. | |
16 | */ | |
17 | ||
18 | #ifndef __PLAT_S3C_SDHCI_H | |
19 | #define __PLAT_S3C_SDHCI_H __FILE__ | |
20 | ||
21 | struct platform_device; | |
22 | struct mmc_host; | |
23 | struct mmc_card; | |
24 | struct mmc_ios; | |
25 | ||
19206b17 MS |
26 | enum cd_types { |
27 | S3C_SDHCI_CD_INTERNAL, /* use mmc internal CD line */ | |
28 | S3C_SDHCI_CD_EXTERNAL, /* use external callback */ | |
29 | S3C_SDHCI_CD_GPIO, /* use external gpio pin for CD line */ | |
30 | S3C_SDHCI_CD_NONE, /* no CD line, use polling to detect card */ | |
31 | S3C_SDHCI_CD_PERMANENT, /* no CD line, card permanently wired to host */ | |
32 | }; | |
33 | ||
28c80aa7 JS |
34 | enum clk_types { |
35 | S3C_SDHCI_CLK_DIV_INTERNAL, /* use mmc internal clock divider */ | |
36 | S3C_SDHCI_CLK_DIV_EXTERNAL, /* use external clock divider */ | |
37 | }; | |
38 | ||
5cc7fd88 BD |
39 | /** |
40 | * struct s3c_sdhci_platdata() - Platform device data for Samsung SDHCI | |
41 | * @max_width: The maximum number of data bits supported. | |
42 | * @host_caps: Standard MMC host capabilities bit field. | |
19206b17 | 43 | * @cd_type: Type of Card Detection method (see cd_types enum above) |
28c80aa7 | 44 | * @clk_type: Type of clock divider method (see clk_types enum above) |
19206b17 MS |
45 | * @ext_cd_init: Initialize external card detect subsystem. Called on |
46 | * sdhci-s3c driver probe when cd_type == S3C_SDHCI_CD_EXTERNAL. | |
47 | * notify_func argument is a callback to the sdhci-s3c driver | |
48 | * that triggers the card detection event. Callback arguments: | |
49 | * dev is pointer to platform device of the host controller, | |
50 | * state is new state of the card (0 - removed, 1 - inserted). | |
51 | * @ext_cd_cleanup: Cleanup external card detect subsystem. Called on | |
52 | * sdhci-s3c driver remove when cd_type == S3C_SDHCI_CD_EXTERNAL. | |
53 | * notify_func argument is the same callback as for ext_cd_init. | |
54 | * @ext_cd_gpio: gpio pin used for external CD line, valid only if | |
55 | * cd_type == S3C_SDHCI_CD_GPIO | |
56 | * @ext_cd_gpio_invert: invert values for external CD gpio line | |
5cc7fd88 | 57 | * @cfg_gpio: Configure the GPIO for a specific card bit-width |
5cc7fd88 BD |
58 | * |
59 | * Initialisation data specific to either the machine or the platform | |
60 | * for the device driver to use or call-back when configuring gpio or | |
61 | * card speed information. | |
62 | */ | |
63 | struct s3c_sdhci_platdata { | |
64 | unsigned int max_width; | |
65 | unsigned int host_caps; | |
19206b17 | 66 | enum cd_types cd_type; |
28c80aa7 | 67 | enum clk_types clk_type; |
5cc7fd88 BD |
68 | |
69 | char **clocks; /* set of clock sources */ | |
70 | ||
19206b17 MS |
71 | int ext_cd_gpio; |
72 | bool ext_cd_gpio_invert; | |
73 | int (*ext_cd_init)(void (*notify_func)(struct platform_device *, | |
74 | int state)); | |
75 | int (*ext_cd_cleanup)(void (*notify_func)(struct platform_device *, | |
76 | int state)); | |
77 | ||
5cc7fd88 | 78 | void (*cfg_gpio)(struct platform_device *dev, int width); |
5cc7fd88 BD |
79 | }; |
80 | ||
5e8e0a10 BG |
81 | /* s3c_sdhci_set_platdata() - common helper for setting SDHCI platform data |
82 | * @pd: The default platform data for this device. | |
83 | * @set: Pointer to the platform data to fill in. | |
84 | */ | |
85 | extern void s3c_sdhci_set_platdata(struct s3c_sdhci_platdata *pd, | |
86 | struct s3c_sdhci_platdata *set); | |
87 | ||
5cc7fd88 BD |
88 | /** |
89 | * s3c_sdhci0_set_platdata - Set platform data for S3C SDHCI device. | |
90 | * @pd: Platform data to register to device. | |
91 | * | |
92 | * Register the given platform data for use withe S3C SDHCI device. | |
93 | * The call will copy the platform data, so the board definitions can | |
94 | * make the structure itself __initdata. | |
95 | */ | |
96 | extern void s3c_sdhci0_set_platdata(struct s3c_sdhci_platdata *pd); | |
a2205cd2 | 97 | extern void s3c_sdhci1_set_platdata(struct s3c_sdhci_platdata *pd); |
86cd4f5f | 98 | extern void s3c_sdhci2_set_platdata(struct s3c_sdhci_platdata *pd); |
b3c674bc | 99 | extern void s3c_sdhci3_set_platdata(struct s3c_sdhci_platdata *pd); |
5cc7fd88 BD |
100 | |
101 | /* Default platform data, exported so that per-cpu initialisation can | |
102 | * set the correct one when there are more than one cpu type selected. | |
103 | */ | |
104 | ||
a2205cd2 BD |
105 | extern struct s3c_sdhci_platdata s3c_hsmmc0_def_platdata; |
106 | extern struct s3c_sdhci_platdata s3c_hsmmc1_def_platdata; | |
86cd4f5f | 107 | extern struct s3c_sdhci_platdata s3c_hsmmc2_def_platdata; |
b3c674bc | 108 | extern struct s3c_sdhci_platdata s3c_hsmmc3_def_platdata; |
5cc7fd88 | 109 | |
25985edc | 110 | /* Helper function availability */ |
5cc7fd88 | 111 | |
c29cfa6d YK |
112 | extern void s3c2416_setup_sdhci0_cfg_gpio(struct platform_device *, int w); |
113 | extern void s3c2416_setup_sdhci1_cfg_gpio(struct platform_device *, int w); | |
4faf6867 BD |
114 | extern void s3c64xx_setup_sdhci0_cfg_gpio(struct platform_device *, int w); |
115 | extern void s3c64xx_setup_sdhci1_cfg_gpio(struct platform_device *, int w); | |
86cd4f5f KP |
116 | extern void s5pc100_setup_sdhci0_cfg_gpio(struct platform_device *, int w); |
117 | extern void s5pc100_setup_sdhci1_cfg_gpio(struct platform_device *, int w); | |
118 | extern void s5pc100_setup_sdhci2_cfg_gpio(struct platform_device *, int w); | |
92b118f6 | 119 | extern void s3c64xx_setup_sdhci2_cfg_gpio(struct platform_device *, int w); |
e6f66a9f MS |
120 | extern void s5pv210_setup_sdhci0_cfg_gpio(struct platform_device *, int w); |
121 | extern void s5pv210_setup_sdhci1_cfg_gpio(struct platform_device *, int w); | |
122 | extern void s5pv210_setup_sdhci2_cfg_gpio(struct platform_device *, int w); | |
976a62f2 | 123 | extern void s5pv210_setup_sdhci3_cfg_gpio(struct platform_device *, int w); |
3db3ae5e KK |
124 | extern void exynos4_setup_sdhci0_cfg_gpio(struct platform_device *, int w); |
125 | extern void exynos4_setup_sdhci1_cfg_gpio(struct platform_device *, int w); | |
126 | extern void exynos4_setup_sdhci2_cfg_gpio(struct platform_device *, int w); | |
127 | extern void exynos4_setup_sdhci3_cfg_gpio(struct platform_device *, int w); | |
4faf6867 | 128 | |
c29cfa6d YK |
129 | /* S3C2416 SDHCI setup */ |
130 | ||
131 | #ifdef CONFIG_S3C2416_SETUP_SDHCI | |
132 | extern char *s3c2416_hsmmc_clksrcs[4]; | |
133 | ||
c29cfa6d YK |
134 | static inline void s3c2416_default_sdhci0(void) |
135 | { | |
136 | #ifdef CONFIG_S3C_DEV_HSMMC | |
137 | s3c_hsmmc0_def_platdata.clocks = s3c2416_hsmmc_clksrcs; | |
138 | s3c_hsmmc0_def_platdata.cfg_gpio = s3c2416_setup_sdhci0_cfg_gpio; | |
c29cfa6d YK |
139 | #endif /* CONFIG_S3C_DEV_HSMMC */ |
140 | } | |
141 | ||
142 | static inline void s3c2416_default_sdhci1(void) | |
143 | { | |
144 | #ifdef CONFIG_S3C_DEV_HSMMC1 | |
145 | s3c_hsmmc1_def_platdata.clocks = s3c2416_hsmmc_clksrcs; | |
146 | s3c_hsmmc1_def_platdata.cfg_gpio = s3c2416_setup_sdhci1_cfg_gpio; | |
c29cfa6d YK |
147 | #endif /* CONFIG_S3C_DEV_HSMMC1 */ |
148 | } | |
149 | ||
150 | #else | |
151 | static inline void s3c2416_default_sdhci0(void) { } | |
152 | static inline void s3c2416_default_sdhci1(void) { } | |
153 | ||
154 | #endif /* CONFIG_S3C2416_SETUP_SDHCI */ | |
88eb7156 | 155 | /* S3C64XX SDHCI setup */ |
4faf6867 | 156 | |
2f6c2ac1 BD |
157 | #ifdef CONFIG_S3C64XX_SETUP_SDHCI |
158 | extern char *s3c64xx_hsmmc_clksrcs[4]; | |
4faf6867 | 159 | |
4faf6867 BD |
160 | static inline void s3c6400_default_sdhci0(void) |
161 | { | |
88eb7156 | 162 | #ifdef CONFIG_S3C_DEV_HSMMC |
2f6c2ac1 | 163 | s3c_hsmmc0_def_platdata.clocks = s3c64xx_hsmmc_clksrcs; |
4faf6867 | 164 | s3c_hsmmc0_def_platdata.cfg_gpio = s3c64xx_setup_sdhci0_cfg_gpio; |
88eb7156 | 165 | #endif |
4faf6867 BD |
166 | } |
167 | ||
4faf6867 BD |
168 | static inline void s3c6400_default_sdhci1(void) |
169 | { | |
88eb7156 | 170 | #ifdef CONFIG_S3C_DEV_HSMMC1 |
2f6c2ac1 | 171 | s3c_hsmmc1_def_platdata.clocks = s3c64xx_hsmmc_clksrcs; |
4faf6867 | 172 | s3c_hsmmc1_def_platdata.cfg_gpio = s3c64xx_setup_sdhci1_cfg_gpio; |
88eb7156 | 173 | #endif |
4faf6867 | 174 | } |
4faf6867 | 175 | |
92b118f6 MC |
176 | static inline void s3c6400_default_sdhci2(void) |
177 | { | |
88eb7156 | 178 | #ifdef CONFIG_S3C_DEV_HSMMC2 |
2f6c2ac1 | 179 | s3c_hsmmc2_def_platdata.clocks = s3c64xx_hsmmc_clksrcs; |
92b118f6 | 180 | s3c_hsmmc2_def_platdata.cfg_gpio = s3c64xx_setup_sdhci2_cfg_gpio; |
88eb7156 | 181 | #endif |
92b118f6 | 182 | } |
4faf6867 | 183 | |
5cc7fd88 BD |
184 | static inline void s3c6410_default_sdhci0(void) |
185 | { | |
88eb7156 | 186 | #ifdef CONFIG_S3C_DEV_HSMMC |
2f6c2ac1 | 187 | s3c_hsmmc0_def_platdata.clocks = s3c64xx_hsmmc_clksrcs; |
4faf6867 | 188 | s3c_hsmmc0_def_platdata.cfg_gpio = s3c64xx_setup_sdhci0_cfg_gpio; |
88eb7156 | 189 | #endif |
5cc7fd88 | 190 | } |
a2205cd2 BD |
191 | |
192 | static inline void s3c6410_default_sdhci1(void) | |
193 | { | |
88eb7156 | 194 | #ifdef CONFIG_S3C_DEV_HSMMC1 |
2f6c2ac1 | 195 | s3c_hsmmc1_def_platdata.clocks = s3c64xx_hsmmc_clksrcs; |
4faf6867 | 196 | s3c_hsmmc1_def_platdata.cfg_gpio = s3c64xx_setup_sdhci1_cfg_gpio; |
88eb7156 | 197 | #endif |
a2205cd2 | 198 | } |
713e9ded | 199 | |
92b118f6 MC |
200 | static inline void s3c6410_default_sdhci2(void) |
201 | { | |
88eb7156 | 202 | #ifdef CONFIG_S3C_DEV_HSMMC2 |
2f6c2ac1 | 203 | s3c_hsmmc2_def_platdata.clocks = s3c64xx_hsmmc_clksrcs; |
92b118f6 | 204 | s3c_hsmmc2_def_platdata.cfg_gpio = s3c64xx_setup_sdhci2_cfg_gpio; |
88eb7156 | 205 | #endif |
92b118f6 | 206 | } |
92b118f6 | 207 | |
5cc7fd88 BD |
208 | #else |
209 | static inline void s3c6410_default_sdhci0(void) { } | |
a2205cd2 | 210 | static inline void s3c6410_default_sdhci1(void) { } |
6b34f498 | 211 | static inline void s3c6410_default_sdhci2(void) { } |
2f6c2ac1 BD |
212 | static inline void s3c6400_default_sdhci0(void) { } |
213 | static inline void s3c6400_default_sdhci1(void) { } | |
6b34f498 | 214 | static inline void s3c6400_default_sdhci2(void) { } |
2f6c2ac1 BD |
215 | |
216 | #endif /* CONFIG_S3C64XX_SETUP_SDHCI */ | |
5cc7fd88 | 217 | |
86cd4f5f KP |
218 | /* S5PC100 SDHCI setup */ |
219 | ||
220 | #ifdef CONFIG_S5PC100_SETUP_SDHCI | |
221 | extern char *s5pc100_hsmmc_clksrcs[4]; | |
222 | ||
86cd4f5f KP |
223 | static inline void s5pc100_default_sdhci0(void) |
224 | { | |
88eb7156 | 225 | #ifdef CONFIG_S3C_DEV_HSMMC |
86cd4f5f KP |
226 | s3c_hsmmc0_def_platdata.clocks = s5pc100_hsmmc_clksrcs; |
227 | s3c_hsmmc0_def_platdata.cfg_gpio = s5pc100_setup_sdhci0_cfg_gpio; | |
88eb7156 | 228 | #endif |
86cd4f5f | 229 | } |
86cd4f5f | 230 | |
86cd4f5f KP |
231 | static inline void s5pc100_default_sdhci1(void) |
232 | { | |
88eb7156 | 233 | #ifdef CONFIG_S3C_DEV_HSMMC1 |
86cd4f5f KP |
234 | s3c_hsmmc1_def_platdata.clocks = s5pc100_hsmmc_clksrcs; |
235 | s3c_hsmmc1_def_platdata.cfg_gpio = s5pc100_setup_sdhci1_cfg_gpio; | |
88eb7156 | 236 | #endif |
86cd4f5f | 237 | } |
86cd4f5f | 238 | |
86cd4f5f KP |
239 | static inline void s5pc100_default_sdhci2(void) |
240 | { | |
88eb7156 | 241 | #ifdef CONFIG_S3C_DEV_HSMMC2 |
86cd4f5f KP |
242 | s3c_hsmmc2_def_platdata.clocks = s5pc100_hsmmc_clksrcs; |
243 | s3c_hsmmc2_def_platdata.cfg_gpio = s5pc100_setup_sdhci2_cfg_gpio; | |
88eb7156 | 244 | #endif |
86cd4f5f | 245 | } |
86cd4f5f KP |
246 | |
247 | #else | |
248 | static inline void s5pc100_default_sdhci0(void) { } | |
249 | static inline void s5pc100_default_sdhci1(void) { } | |
250 | static inline void s5pc100_default_sdhci2(void) { } | |
88eb7156 | 251 | |
86cd4f5f KP |
252 | #endif /* CONFIG_S5PC100_SETUP_SDHCI */ |
253 | ||
88eb7156 | 254 | /* S5PV210 SDHCI setup */ |
e6f66a9f | 255 | |
e6f66a9f MS |
256 | #ifdef CONFIG_S5PV210_SETUP_SDHCI |
257 | extern char *s5pv210_hsmmc_clksrcs[4]; | |
258 | ||
e6f66a9f MS |
259 | static inline void s5pv210_default_sdhci0(void) |
260 | { | |
88eb7156 | 261 | #ifdef CONFIG_S3C_DEV_HSMMC |
e6f66a9f MS |
262 | s3c_hsmmc0_def_platdata.clocks = s5pv210_hsmmc_clksrcs; |
263 | s3c_hsmmc0_def_platdata.cfg_gpio = s5pv210_setup_sdhci0_cfg_gpio; | |
88eb7156 | 264 | #endif |
e6f66a9f | 265 | } |
e6f66a9f | 266 | |
e6f66a9f MS |
267 | static inline void s5pv210_default_sdhci1(void) |
268 | { | |
88eb7156 | 269 | #ifdef CONFIG_S3C_DEV_HSMMC1 |
e6f66a9f MS |
270 | s3c_hsmmc1_def_platdata.clocks = s5pv210_hsmmc_clksrcs; |
271 | s3c_hsmmc1_def_platdata.cfg_gpio = s5pv210_setup_sdhci1_cfg_gpio; | |
88eb7156 | 272 | #endif |
e6f66a9f | 273 | } |
e6f66a9f | 274 | |
e6f66a9f MS |
275 | static inline void s5pv210_default_sdhci2(void) |
276 | { | |
88eb7156 | 277 | #ifdef CONFIG_S3C_DEV_HSMMC2 |
e6f66a9f MS |
278 | s3c_hsmmc2_def_platdata.clocks = s5pv210_hsmmc_clksrcs; |
279 | s3c_hsmmc2_def_platdata.cfg_gpio = s5pv210_setup_sdhci2_cfg_gpio; | |
88eb7156 | 280 | #endif |
e6f66a9f | 281 | } |
e6f66a9f | 282 | |
976a62f2 HL |
283 | static inline void s5pv210_default_sdhci3(void) |
284 | { | |
d61bd77f | 285 | #ifdef CONFIG_S3C_DEV_HSMMC3 |
976a62f2 HL |
286 | s3c_hsmmc3_def_platdata.clocks = s5pv210_hsmmc_clksrcs; |
287 | s3c_hsmmc3_def_platdata.cfg_gpio = s5pv210_setup_sdhci3_cfg_gpio; | |
d61bd77f | 288 | #endif |
976a62f2 | 289 | } |
976a62f2 | 290 | |
e6f66a9f MS |
291 | #else |
292 | static inline void s5pv210_default_sdhci0(void) { } | |
293 | static inline void s5pv210_default_sdhci1(void) { } | |
294 | static inline void s5pv210_default_sdhci2(void) { } | |
976a62f2 | 295 | static inline void s5pv210_default_sdhci3(void) { } |
e6f66a9f | 296 | |
88eb7156 | 297 | #endif /* CONFIG_S5PV210_SETUP_SDHCI */ |
e6f66a9f | 298 | |
3db3ae5e KK |
299 | /* EXYNOS4 SDHCI setup */ |
300 | #ifdef CONFIG_EXYNOS4_SETUP_SDHCI | |
301 | extern char *exynos4_hsmmc_clksrcs[4]; | |
1036c3ab | 302 | |
3db3ae5e | 303 | static inline void exynos4_default_sdhci0(void) |
1036c3ab HL |
304 | { |
305 | #ifdef CONFIG_S3C_DEV_HSMMC | |
3db3ae5e KK |
306 | s3c_hsmmc0_def_platdata.clocks = exynos4_hsmmc_clksrcs; |
307 | s3c_hsmmc0_def_platdata.cfg_gpio = exynos4_setup_sdhci0_cfg_gpio; | |
1036c3ab HL |
308 | #endif |
309 | } | |
310 | ||
3db3ae5e | 311 | static inline void exynos4_default_sdhci1(void) |
1036c3ab HL |
312 | { |
313 | #ifdef CONFIG_S3C_DEV_HSMMC1 | |
3db3ae5e KK |
314 | s3c_hsmmc1_def_platdata.clocks = exynos4_hsmmc_clksrcs; |
315 | s3c_hsmmc1_def_platdata.cfg_gpio = exynos4_setup_sdhci1_cfg_gpio; | |
1036c3ab HL |
316 | #endif |
317 | } | |
318 | ||
3db3ae5e | 319 | static inline void exynos4_default_sdhci2(void) |
1036c3ab HL |
320 | { |
321 | #ifdef CONFIG_S3C_DEV_HSMMC2 | |
3db3ae5e KK |
322 | s3c_hsmmc2_def_platdata.clocks = exynos4_hsmmc_clksrcs; |
323 | s3c_hsmmc2_def_platdata.cfg_gpio = exynos4_setup_sdhci2_cfg_gpio; | |
1036c3ab HL |
324 | #endif |
325 | } | |
326 | ||
3db3ae5e | 327 | static inline void exynos4_default_sdhci3(void) |
1036c3ab HL |
328 | { |
329 | #ifdef CONFIG_S3C_DEV_HSMMC3 | |
3db3ae5e KK |
330 | s3c_hsmmc3_def_platdata.clocks = exynos4_hsmmc_clksrcs; |
331 | s3c_hsmmc3_def_platdata.cfg_gpio = exynos4_setup_sdhci3_cfg_gpio; | |
1036c3ab HL |
332 | #endif |
333 | } | |
334 | ||
335 | #else | |
3db3ae5e KK |
336 | static inline void exynos4_default_sdhci0(void) { } |
337 | static inline void exynos4_default_sdhci1(void) { } | |
338 | static inline void exynos4_default_sdhci2(void) { } | |
339 | static inline void exynos4_default_sdhci3(void) { } | |
1036c3ab | 340 | |
3db3ae5e | 341 | #endif /* CONFIG_EXYNOS4_SETUP_SDHCI */ |
1036c3ab | 342 | |
5cc7fd88 | 343 | #endif /* __PLAT_S3C_SDHCI_H */ |