[deliverable/linux.git] / arch / arm / plat-samsung / pm.c

/* linux/arch/arm/plat-s3c/pm.c
 *
 * Copyright 2008 Openmoko, Inc.
 * Copyright 2004-2008 Simtec Electronics
 *	Ben Dooks <ben@simtec.co.uk>
 *	http://armlinux.simtec.co.uk/
 *
 * S3C common power management (suspend to ram) support.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
*/

#include <linux/init.h>
#include <linux/suspend.h>
#include <linux/errno.h>
#include <linux/delay.h>
#include <linux/of.h>
#include <linux/serial_core.h>
#include <linux/io.h>

#include <asm/cacheflush.h>
#include <asm/suspend.h>

#include <plat/regs-serial.h>

#ifdef CONFIG_SAMSUNG_ATAGS
#include <mach/hardware.h>
#include <mach/map.h>
#include <mach/regs-clock.h>
#include <mach/regs-irq.h>
#include <mach/irqs.h>
#endif

#include <asm/irq.h>

#include <plat/pm.h>
#include <mach/pm-core.h>

/* for external use */

unsigned long s3c_pm_flags;

/* Debug code:
 *
 * This code supports debug output to the low level UARTs for use on
 * resume before the console layer is available.
*/

#ifdef CONFIG_SAMSUNG_PM_DEBUG
extern void printascii(const char *);

void s3c_pm_dbg(const char *fmt, ...)
{
	va_list va;
	char buff[256];

	va_start(va, fmt);
	vsnprintf(buff, sizeof(buff), fmt, va);
	va_end(va);

	printascii(buff);
}

static inline void s3c_pm_debug_init(void)
{
	/* restart uart clocks so we can use them to output */
	s3c_pm_debug_init_uart();
}

#else
#define s3c_pm_debug_init() do { } while(0)

#endif /* CONFIG_SAMSUNG_PM_DEBUG */

/* Save the UART configurations if we are configured for debug. */

unsigned char pm_uart_udivslot;

#ifdef CONFIG_SAMSUNG_PM_DEBUG

static struct pm_uart_save uart_save;

static void s3c_pm_save_uart(unsigned int uart, struct pm_uart_save *save)
{
	void __iomem *regs = S3C_VA_UARTx(uart);

	save->ulcon = __raw_readl(regs + S3C2410_ULCON);
	save->ucon = __raw_readl(regs + S3C2410_UCON);
	save->ufcon = __raw_readl(regs + S3C2410_UFCON);
	save->umcon = __raw_readl(regs + S3C2410_UMCON);
	save->ubrdiv = __raw_readl(regs + S3C2410_UBRDIV);

	if (pm_uart_udivslot)
		save->udivslot = __raw_readl(regs + S3C2443_DIVSLOT);

	S3C_PMDBG("UART[%d]: ULCON=%04x, UCON=%04x, UFCON=%04x, UBRDIV=%04x\n",
		  uart, save->ulcon, save->ucon, save->ufcon, save->ubrdiv);
}

static void s3c_pm_save_uarts(void)
{
	s3c_pm_save_uart(CONFIG_DEBUG_S3C_UART, &uart_save);
}

static void s3c_pm_restore_uart(unsigned int uart, struct pm_uart_save *save)
{
	void __iomem *regs = S3C_VA_UARTx(uart);

	s3c_pm_arch_update_uart(regs, save);

	__raw_writel(save->ulcon, regs + S3C2410_ULCON);
	__raw_writel(save->ucon,  regs + S3C2410_UCON);
	__raw_writel(save->ufcon, regs + S3C2410_UFCON);
	__raw_writel(save->umcon, regs + S3C2410_UMCON);
	__raw_writel(save->ubrdiv, regs + S3C2410_UBRDIV);

	if (pm_uart_udivslot)
		__raw_writel(save->udivslot, regs + S3C2443_DIVSLOT);
}

static void s3c_pm_restore_uarts(void)
{
	s3c_pm_restore_uart(CONFIG_DEBUG_S3C_UART, &uart_save);
}
#else
static void s3c_pm_save_uarts(void) { }
static void s3c_pm_restore_uarts(void) { }
#endif

/* The IRQ ext-int code goes here, it is too small to currently bother
 * with its own file. */

unsigned long s3c_irqwake_intmask	= 0xffffffffL;
unsigned long s3c_irqwake_eintmask	= 0xffffffffL;

int s3c_irqext_wake(struct irq_data *data, unsigned int state)
{
	unsigned long bit = 1L << IRQ_EINT_BIT(data->irq);

	if (!(s3c_irqwake_eintallow & bit))
		return -ENOENT;

	printk(KERN_INFO "wake %s for irq %d\n",
	       state ? "enabled" : "disabled", data->irq);

	if (!state)
		s3c_irqwake_eintmask |= bit;
	else
		s3c_irqwake_eintmask &= ~bit;

	return 0;
}

/* helper functions to save and restore register state */

/**
 * s3c_pm_do_save() - save a set of registers for restoration on resume.
 * @ptr: Pointer to an array of registers.
 * @count: Size of the ptr array.
 *
 * Run through the list of registers given, saving their contents in the
 * array for later restoration when we wakeup.
 */
void s3c_pm_do_save(struct sleep_save *ptr, int count)
{
	for (; count > 0; count--, ptr++) {
		ptr->val = __raw_readl(ptr->reg);
		S3C_PMDBG("saved %p value %08lx\n", ptr->reg, ptr->val);
	}
}

/**
 * s3c_pm_do_restore() - restore register values from the save list.
 * @ptr: Pointer to an array of registers.
 * @count: Size of the ptr array.
 *
 * Restore the register values saved from s3c_pm_do_save().
 *
 * Note, we do not use S3C_PMDBG() in here, as the system may not have
 * restore the UARTs state yet
*/

void s3c_pm_do_restore(struct sleep_save *ptr, int count)
{
	for (; count > 0; count--, ptr++) {
		printk(KERN_DEBUG "restore %p (restore %08lx, was %08x)\n",
		       ptr->reg, ptr->val, __raw_readl(ptr->reg));

		__raw_writel(ptr->val, ptr->reg);
	}
}

/**
 * s3c_pm_do_restore_core() - early restore register values from save list.
 *
 * This is similar to s3c_pm_do_restore() except we try and minimise the
 * side effects of the function in case registers that hardware might need
 * to work has been restored.
 *
 * WARNING: Do not put any debug in here that may effect memory or use
 * peripherals, as things may be changing!
*/

void s3c_pm_do_restore_core(struct sleep_save *ptr, int count)
{
	for (; count > 0; count--, ptr++)
		__raw_writel(ptr->val, ptr->reg);
}

/* s3c2410_pm_show_resume_irqs
 *
 * print any IRQs asserted at resume time (ie, we woke from)
*/
static void __maybe_unused s3c_pm_show_resume_irqs(int start,
						   unsigned long which,
						   unsigned long mask)
{
	int i;

	which &= ~mask;

	for (i = 0; i <= 31; i++) {
		if (which & (1L<<i)) {
			S3C_PMDBG("IRQ %d asserted at resume\n", start+i);
		}
	}
}


void (*pm_cpu_prep)(void);
int (*pm_cpu_sleep)(unsigned long);

#define any_allowed(mask, allow) (((mask) & (allow)) != (allow))

/* s3c_pm_enter
 *
 * central control for sleep/resume process
*/

static int s3c_pm_enter(suspend_state_t state)
{
	int ret;
	/* ensure the debug is initialised (if enabled) */

	s3c_pm_debug_init();

	S3C_PMDBG("%s(%d)\n", __func__, state);

	if (pm_cpu_prep == NULL || pm_cpu_sleep == NULL) {
		printk(KERN_ERR "%s: error: no cpu sleep function\n", __func__);
		return -EINVAL;
	}

	/* check if we have anything to wake-up with... bad things seem
	 * to happen if you suspend with no wakeup (system will often
	 * require a full power-cycle)
	*/

	if (!of_have_populated_dt() &&
	    !any_allowed(s3c_irqwake_intmask, s3c_irqwake_intallow) &&
	    !any_allowed(s3c_irqwake_eintmask, s3c_irqwake_eintallow)) {
		printk(KERN_ERR "%s: No wake-up sources!\n", __func__);
		printk(KERN_ERR "%s: Aborting sleep\n", __func__);
		return -EINVAL;
	}

	/* save all necessary core registers not covered by the drivers */

	if (!of_have_populated_dt()) {
		samsung_pm_save_gpios();
		samsung_pm_saved_gpios();
	}

	s3c_pm_save_uarts();
	s3c_pm_save_core();

	/* set the irq configuration for wake */

	s3c_pm_configure_extint();

	S3C_PMDBG("sleep: irq wakeup masks: %08lx,%08lx\n",
	    s3c_irqwake_intmask, s3c_irqwake_eintmask);

	s3c_pm_arch_prepare_irqs();

	/* call cpu specific preparation */

	pm_cpu_prep();

	/* flush cache back to ram */

	flush_cache_all();

	s3c_pm_check_store();

	/* send the cpu to sleep... */

	s3c_pm_arch_stop_clocks();

	/* this will also act as our return point from when
	 * we resume as it saves its own register state and restores it
	 * during the resume.  */

	ret = cpu_suspend(0, pm_cpu_sleep);
	if (ret)
		return ret;

	/* restore the system state */

	s3c_pm_restore_core();
	s3c_pm_restore_uarts();

	if (!of_have_populated_dt()) {
		samsung_pm_restore_gpios();
		s3c_pm_restored_gpios();
	}

	s3c_pm_debug_init();

	/* check what irq (if any) restored the system */

	s3c_pm_arch_show_resume_irqs();

	S3C_PMDBG("%s: post sleep, preparing to return\n", __func__);

	/* LEDs should now be 1110 */
	s3c_pm_debug_smdkled(1 << 1, 0);

	s3c_pm_check_restore();

	/* ok, let's return from sleep */

	S3C_PMDBG("S3C PM Resume (post-restore)\n");
	return 0;
}

static int s3c_pm_prepare(void)
{
	/* prepare check area if configured */

	s3c_pm_check_prepare();
	return 0;
}

static void s3c_pm_finish(void)
{
	s3c_pm_check_cleanup();
}

static const struct platform_suspend_ops s3c_pm_ops = {
	.enter		= s3c_pm_enter,
	.prepare	= s3c_pm_prepare,
	.finish		= s3c_pm_finish,
	.valid		= suspend_valid_only_mem,
};

/* s3c_pm_init
 *
 * Attach the power management functions. This should be called
 * from the board specific initialisation if the board supports
 * it.
*/

int __init s3c_pm_init(void)
{
	printk("S3C Power Management, Copyright 2004 Simtec Electronics\n");

	suspend_set_ops(&s3c_pm_ops);
	return 0;
}
Commit	Line	Data
6419711a BD	1	/* linux/arch/arm/plat-s3c/pm.c
	2	*
	3	* Copyright 2008 Openmoko, Inc.
ccae941e	4	* Copyright 2004-2008 Simtec Electronics
6419711a BD	5	* Ben Dooks <ben@simtec.co.uk>
	6	* http://armlinux.simtec.co.uk/
	7	*
	8	* S3C common power management (suspend to ram) support.
	9	*
	10	* This program is free software; you can redistribute it and/or modify
	11	* it under the terms of the GNU General Public License version 2 as
	12	* published by the Free Software Foundation.
	13	*/
	14
	15	#include <linux/init.h>
	16	#include <linux/suspend.h>
	17	#include <linux/errno.h>
2261e0e6	18	#include <linux/delay.h>
cd3fc1b9	19	#include <linux/of.h>
2261e0e6	20	#include <linux/serial_core.h>
6419711a BD	21	#include <linux/io.h>
6419711a BD	22
2261e0e6	23	#include <asm/cacheflush.h>
2c74a0ce	24	#include <asm/suspend.h>
2261e0e6 BD	25
2261e0e6 BD	26	#include <plat/regs-serial.h>
d6280ffb TF	27
	28	#ifdef CONFIG_SAMSUNG_ATAGS
	29	#include <mach/hardware.h>
	30	#include <mach/map.h>
2261e0e6	31	#include <mach/regs-clock.h>
2261e0e6	32	#include <mach/regs-irq.h>
7ba8022f	33	#include <mach/irqs.h>
d6280ffb TF	34	#endif
d6280ffb TF	35
56b34426	36	#include <asm/irq.h>
2261e0e6	37
6419711a	38	#include <plat/pm.h>
431fb7df	39	#include <mach/pm-core.h>
6419711a BD	40
	41	/* for external use */
	42
	43	unsigned long s3c_pm_flags;
	44
2261e0e6 BD	45	/* Debug code:
	46	*
	47	* This code supports debug output to the low level UARTs for use on
	48	* resume before the console layer is available.
	49	*/
	50
8005745d	51	#ifdef CONFIG_SAMSUNG_PM_DEBUG
6419711a BD	52	extern void printascii(const char *);
	53
	54	void s3c_pm_dbg(const char *fmt, ...)
	55	{
	56	va_list va;
	57	char buff[256];
	58
	59	va_start(va, fmt);
8baaa265	60	vsnprintf(buff, sizeof(buff), fmt, va);
6419711a BD	61	va_end(va);
	62
	63	printascii(buff);
	64	}
2261e0e6 BD	65
	66	static inline void s3c_pm_debug_init(void)
	67	{
	68	/* restart uart clocks so we can use them to output */
	69	s3c_pm_debug_init_uart();
	70	}
	71
	72	#else
	73	#define s3c_pm_debug_init() do { } while(0)
	74
8005745d	75	#endif /* CONFIG_SAMSUNG_PM_DEBUG */
6419711a	76
2261e0e6 BD	77	/* Save the UART configurations if we are configured for debug. */
2261e0e6 BD	78
4b637dc2 BD	79	unsigned char pm_uart_udivslot;
4b637dc2 BD	80
8005745d	81	#ifdef CONFIG_SAMSUNG_PM_DEBUG
2261e0e6	82
7bdc84fb	83	static struct pm_uart_save uart_save;
d2b07fe2 BD	84
	85	static void s3c_pm_save_uart(unsigned int uart, struct pm_uart_save *save)
	86	{
	87	void __iomem *regs = S3C_VA_UARTx(uart);
	88
	89	save->ulcon = __raw_readl(regs + S3C2410_ULCON);
	90	save->ucon = __raw_readl(regs + S3C2410_UCON);
	91	save->ufcon = __raw_readl(regs + S3C2410_UFCON);
	92	save->umcon = __raw_readl(regs + S3C2410_UMCON);
	93	save->ubrdiv = __raw_readl(regs + S3C2410_UBRDIV);
57699e9a	94
4b637dc2 BD	95	if (pm_uart_udivslot)
	96	save->udivslot = __raw_readl(regs + S3C2443_DIVSLOT);
	97
57699e9a BD	98	S3C_PMDBG("UART[%d]: ULCON=%04x, UCON=%04x, UFCON=%04x, UBRDIV=%04x\n",
57699e9a BD	99	uart, save->ulcon, save->ucon, save->ufcon, save->ubrdiv);
d2b07fe2	100	}
2261e0e6	101
d2b07fe2	102	static void s3c_pm_save_uarts(void)
2261e0e6	103	{
7bdc84fb	104	s3c_pm_save_uart(CONFIG_DEBUG_S3C_UART, &uart_save);
d2b07fe2 BD	105	}
	106
	107	static void s3c_pm_restore_uart(unsigned int uart, struct pm_uart_save *save)
	108	{
	109	void __iomem *regs = S3C_VA_UARTx(uart);
	110
57699e9a BD	111	s3c_pm_arch_update_uart(regs, save);
57699e9a BD	112
d2b07fe2 BD	113	__raw_writel(save->ulcon, regs + S3C2410_ULCON);
	114	__raw_writel(save->ucon, regs + S3C2410_UCON);
	115	__raw_writel(save->ufcon, regs + S3C2410_UFCON);
	116	__raw_writel(save->umcon, regs + S3C2410_UMCON);
	117	__raw_writel(save->ubrdiv, regs + S3C2410_UBRDIV);
4b637dc2 BD	118
	119	if (pm_uart_udivslot)
	120	__raw_writel(save->udivslot, regs + S3C2443_DIVSLOT);
2261e0e6 BD	121	}
2261e0e6 BD	122
d2b07fe2	123	static void s3c_pm_restore_uarts(void)
2261e0e6	124	{
7bdc84fb	125	s3c_pm_restore_uart(CONFIG_DEBUG_S3C_UART, &uart_save);
2261e0e6 BD	126	}
2261e0e6 BD	127	#else
d2b07fe2 BD	128	static void s3c_pm_save_uarts(void) { }
d2b07fe2 BD	129	static void s3c_pm_restore_uarts(void) { }
2261e0e6 BD	130	#endif
2261e0e6 BD	131
56b34426 BD	132	/* The IRQ ext-int code goes here, it is too small to currently bother
	133	* with its own file. */
	134
	135	unsigned long s3c_irqwake_intmask = 0xffffffffL;
	136	unsigned long s3c_irqwake_eintmask = 0xffffffffL;
	137
f5aeffb7	138	int s3c_irqext_wake(struct irq_data *data, unsigned int state)
56b34426	139	{
f5aeffb7	140	unsigned long bit = 1L << IRQ_EINT_BIT(data->irq);
56b34426 BD	141
	142	if (!(s3c_irqwake_eintallow & bit))
	143	return -ENOENT;
	144
	145	printk(KERN_INFO "wake %s for irq %d\n",
f5aeffb7	146	state ? "enabled" : "disabled", data->irq);
56b34426 BD	147
	148	if (!state)
	149	s3c_irqwake_eintmask \|= bit;
	150	else
	151	s3c_irqwake_eintmask &= ~bit;
	152
	153	return 0;
	154	}
6419711a BD	155
	156	/* helper functions to save and restore register state */
	157
	158	/**
	159	* s3c_pm_do_save() - save a set of registers for restoration on resume.
	160	* @ptr: Pointer to an array of registers.
	161	* @count: Size of the ptr array.
	162	*
	163	* Run through the list of registers given, saving their contents in the
	164	* array for later restoration when we wakeup.
	165	*/
	166	void s3c_pm_do_save(struct sleep_save *ptr, int count)
	167	{
	168	for (; count > 0; count--, ptr++) {
	169	ptr->val = __raw_readl(ptr->reg);
	170	S3C_PMDBG("saved %p value %08lx\n", ptr->reg, ptr->val);
	171	}
	172	}
	173
	174	/**
	175	* s3c_pm_do_restore() - restore register values from the save list.
	176	* @ptr: Pointer to an array of registers.
	177	* @count: Size of the ptr array.
	178	*
	179	* Restore the register values saved from s3c_pm_do_save().
	180	*
	181	* Note, we do not use S3C_PMDBG() in here, as the system may not have
	182	* restore the UARTs state yet
	183	*/
	184
	185	void s3c_pm_do_restore(struct sleep_save *ptr, int count)
	186	{
	187	for (; count > 0; count--, ptr++) {
	188	printk(KERN_DEBUG "restore %p (restore %08lx, was %08x)\n",
	189	ptr->reg, ptr->val, __raw_readl(ptr->reg));
	190
	191	__raw_writel(ptr->val, ptr->reg);
	192	}
	193	}
	194
	195	/**
	196	* s3c_pm_do_restore_core() - early restore register values from save list.
	197	*
	198	* This is similar to s3c_pm_do_restore() except we try and minimise the
	199	* side effects of the function in case registers that hardware might need
	200	* to work has been restored.
	201	*
	202	* WARNING: Do not put any debug in here that may effect memory or use
	203	* peripherals, as things may be changing!
	204	*/
	205
	206	void s3c_pm_do_restore_core(struct sleep_save *ptr, int count)
	207	{
	208	for (; count > 0; count--, ptr++)
	209	__raw_writel(ptr->val, ptr->reg);
	210	}
2261e0e6 BD	211
	212	/* s3c2410_pm_show_resume_irqs
	213	*
	214	* print any IRQs asserted at resume time (ie, we woke from)
	215	*/
baab7307 MC	216	static void __maybe_unused s3c_pm_show_resume_irqs(int start,
	217	unsigned long which,
	218	unsigned long mask)
2261e0e6 BD	219	{
	220	int i;
	221
	222	which &= ~mask;
	223
	224	for (i = 0; i <= 31; i++) {
	225	if (which & (1L<<i)) {
	226	S3C_PMDBG("IRQ %d asserted at resume\n", start+i);
	227	}
	228	}
	229	}
	230
	231
	232	void (*pm_cpu_prep)(void);
29cb3cd2	233	int (*pm_cpu_sleep)(unsigned long);
2261e0e6 BD	234
	235	#define any_allowed(mask, allow) (((mask) & (allow)) != (allow))
	236
	237	/* s3c_pm_enter
	238	*
	239	* central control for sleep/resume process
	240	*/
	241
	242	static int s3c_pm_enter(suspend_state_t state)
	243	{
d3fcacf5	244	int ret;
2261e0e6 BD	245	/* ensure the debug is initialised (if enabled) */
	246
	247	s3c_pm_debug_init();
	248
	249	S3C_PMDBG("%s(%d)\n", __func__, state);
	250
	251	if (pm_cpu_prep == NULL \|\| pm_cpu_sleep == NULL) {
	252	printk(KERN_ERR "%s: error: no cpu sleep function\n", __func__);
	253	return -EINVAL;
	254	}
	255
	256	/* check if we have anything to wake-up with... bad things seem
	257	* to happen if you suspend with no wakeup (system will often
	258	* require a full power-cycle)
	259	*/
	260
cd3fc1b9 TF	261	if (!of_have_populated_dt() &&
cd3fc1b9 TF	262	!any_allowed(s3c_irqwake_intmask, s3c_irqwake_intallow) &&
2261e0e6 BD	263	!any_allowed(s3c_irqwake_eintmask, s3c_irqwake_eintallow)) {
	264	printk(KERN_ERR "%s: No wake-up sources!\n", __func__);
	265	printk(KERN_ERR "%s: Aborting sleep\n", __func__);
	266	return -EINVAL;
	267	}
	268
2261e0e6 BD	269	/* save all necessary core registers not covered by the drivers */
2261e0e6 BD	270
cd3fc1b9 TF	271	if (!of_have_populated_dt()) {
	272	samsung_pm_save_gpios();
	273	samsung_pm_saved_gpios();
	274	}
	275
d2b07fe2	276	s3c_pm_save_uarts();
2261e0e6 BD	277	s3c_pm_save_core();
	278
	279	/* set the irq configuration for wake */
	280
	281	s3c_pm_configure_extint();
	282
	283	S3C_PMDBG("sleep: irq wakeup masks: %08lx,%08lx\n",
	284	s3c_irqwake_intmask, s3c_irqwake_eintmask);
	285
	286	s3c_pm_arch_prepare_irqs();
	287
	288	/* call cpu specific preparation */
	289
	290	pm_cpu_prep();
	291
	292	/* flush cache back to ram */
	293
	294	flush_cache_all();
	295
	296	s3c_pm_check_store();
	297
	298	/* send the cpu to sleep... */
	299
	300	s3c_pm_arch_stop_clocks();
	301
e7089da9	302	/* this will also act as our return point from when
fff94cd9 BD	303	* we resume as it saves its own register state and restores it
fff94cd9 BD	304	* during the resume. */
2261e0e6	305
d3fcacf5 AK	306	ret = cpu_suspend(0, pm_cpu_sleep);
	307	if (ret)
	308	return ret;
2261e0e6	309
2261e0e6 BD	310	/* restore the system state */
	311
	312	s3c_pm_restore_core();
d2b07fe2	313	s3c_pm_restore_uarts();
cd3fc1b9 TF	314
	315	if (!of_have_populated_dt()) {
	316	samsung_pm_restore_gpios();
	317	s3c_pm_restored_gpios();
	318	}
2261e0e6 BD	319
	320	s3c_pm_debug_init();
	321
	322	/* check what irq (if any) restored the system */
	323
	324	s3c_pm_arch_show_resume_irqs();
	325
	326	S3C_PMDBG("%s: post sleep, preparing to return\n", __func__);
	327
bd117bd1 BD	328	/* LEDs should now be 1110 */
	329	s3c_pm_debug_smdkled(1 << 1, 0);
	330
2261e0e6 BD	331	s3c_pm_check_restore();
	332
	333	/* ok, let's return from sleep */
	334
	335	S3C_PMDBG("S3C PM Resume (post-restore)\n");
	336	return 0;
	337	}
	338
aa8aba69 BD	339	static int s3c_pm_prepare(void)
	340	{
	341	/* prepare check area if configured */
	342
	343	s3c_pm_check_prepare();
	344	return 0;
	345	}
	346
	347	static void s3c_pm_finish(void)
	348	{
	349	s3c_pm_check_cleanup();
	350	}
	351
2f55ac07	352	static const struct platform_suspend_ops s3c_pm_ops = {
2261e0e6	353	.enter = s3c_pm_enter,
aa8aba69 BD	354	.prepare = s3c_pm_prepare,
aa8aba69 BD	355	.finish = s3c_pm_finish,
2261e0e6 BD	356	.valid = suspend_valid_only_mem,
	357	};
	358
4e59c25d	359	/* s3c_pm_init
2261e0e6 BD	360	*
	361	* Attach the power management functions. This should be called
	362	* from the board specific initialisation if the board supports
	363	* it.
	364	*/
	365
4e59c25d	366	int __init s3c_pm_init(void)
2261e0e6 BD	367	{
	368	printk("S3C Power Management, Copyright 2004 Simtec Electronics\n");
	369
	370	suspend_set_ops(&s3c_pm_ops);
	371	return 0;
	372	}