Commit | Line | Data |
---|---|---|
bf46aaea | 1 | /* |
1a0e8a52 KK |
2 | * Copyright 2009 Samsung Electronics Co., Ltd. |
3 | * http://www.samsung.com/ | |
4 | * | |
5 | * S5P - Common clock support | |
6 | * | |
7 | * This program is free software; you can redistribute it and/or modify | |
8 | * it under the terms of the GNU General Public License version 2 as | |
9 | * published by the Free Software Foundation. | |
10 | */ | |
11 | ||
12 | #include <linux/init.h> | |
13 | #include <linux/module.h> | |
14 | #include <linux/kernel.h> | |
15 | #include <linux/list.h> | |
16 | #include <linux/errno.h> | |
17 | #include <linux/err.h> | |
18 | #include <linux/clk.h> | |
edbaa603 | 19 | #include <linux/device.h> |
1a0e8a52 KK |
20 | #include <linux/io.h> |
21 | #include <asm/div64.h> | |
22 | ||
d4b34c6c SY |
23 | #include <mach/regs-clock.h> |
24 | ||
1a0e8a52 KK |
25 | #include <plat/clock.h> |
26 | #include <plat/clock-clksrc.h> | |
27 | #include <plat/s5p-clock.h> | |
28 | ||
29 | /* fin_apll, fin_mpll and fin_epll are all the same clock, which we call | |
30 | * clk_ext_xtal_mux. | |
31 | */ | |
32 | struct clk clk_ext_xtal_mux = { | |
33 | .name = "ext_xtal", | |
34 | .id = -1, | |
35 | }; | |
36 | ||
f001d5b2 TA |
37 | struct clk clk_xusbxti = { |
38 | .name = "xusbxti", | |
39 | .id = -1, | |
40 | }; | |
41 | ||
a443a637 | 42 | struct clk s5p_clk_27m = { |
0c1945d3 KK |
43 | .name = "clk_27m", |
44 | .id = -1, | |
45 | .rate = 27000000, | |
46 | }; | |
47 | ||
1a0e8a52 KK |
48 | /* 48MHz USB Phy clock output */ |
49 | struct clk clk_48m = { | |
50 | .name = "clk_48m", | |
51 | .id = -1, | |
52 | .rate = 48000000, | |
53 | }; | |
54 | ||
55 | /* APLL clock output | |
56 | * No need .ctrlbit, this is always on | |
57 | */ | |
58 | struct clk clk_fout_apll = { | |
59 | .name = "fout_apll", | |
60 | .id = -1, | |
61 | }; | |
62 | ||
87b3c6ef KK |
63 | /* BPLL clock output */ |
64 | ||
65 | struct clk clk_fout_bpll = { | |
66 | .name = "fout_bpll", | |
67 | .id = -1, | |
68 | }; | |
69 | ||
57b317f9 KY |
70 | struct clk clk_fout_bpll_div2 = { |
71 | .name = "fout_bpll_div2", | |
72 | .id = -1, | |
73 | }; | |
74 | ||
87b3c6ef KK |
75 | /* CPLL clock output */ |
76 | ||
77 | struct clk clk_fout_cpll = { | |
78 | .name = "fout_cpll", | |
79 | .id = -1, | |
80 | }; | |
81 | ||
1a0e8a52 KK |
82 | /* MPLL clock output |
83 | * No need .ctrlbit, this is always on | |
84 | */ | |
85 | struct clk clk_fout_mpll = { | |
86 | .name = "fout_mpll", | |
87 | .id = -1, | |
88 | }; | |
89 | ||
57b317f9 KY |
90 | struct clk clk_fout_mpll_div2 = { |
91 | .name = "fout_mpll_div2", | |
92 | .id = -1, | |
93 | }; | |
94 | ||
1a0e8a52 KK |
95 | /* EPLL clock output */ |
96 | struct clk clk_fout_epll = { | |
97 | .name = "fout_epll", | |
98 | .id = -1, | |
99 | .ctrlbit = (1 << 31), | |
100 | }; | |
101 | ||
3109e550 KK |
102 | /* DPLL clock output */ |
103 | struct clk clk_fout_dpll = { | |
104 | .name = "fout_dpll", | |
105 | .id = -1, | |
106 | .ctrlbit = (1 << 31), | |
107 | }; | |
108 | ||
f445dbd5 TA |
109 | /* VPLL clock output */ |
110 | struct clk clk_fout_vpll = { | |
111 | .name = "fout_vpll", | |
112 | .id = -1, | |
113 | .ctrlbit = (1 << 31), | |
114 | }; | |
115 | ||
1a0e8a52 KK |
116 | /* Possible clock sources for APLL Mux */ |
117 | static struct clk *clk_src_apll_list[] = { | |
118 | [0] = &clk_fin_apll, | |
119 | [1] = &clk_fout_apll, | |
120 | }; | |
121 | ||
122 | struct clksrc_sources clk_src_apll = { | |
123 | .sources = clk_src_apll_list, | |
124 | .nr_sources = ARRAY_SIZE(clk_src_apll_list), | |
125 | }; | |
126 | ||
87b3c6ef KK |
127 | /* Possible clock sources for BPLL Mux */ |
128 | static struct clk *clk_src_bpll_list[] = { | |
129 | [0] = &clk_fin_bpll, | |
130 | [1] = &clk_fout_bpll, | |
131 | }; | |
132 | ||
133 | struct clksrc_sources clk_src_bpll = { | |
134 | .sources = clk_src_bpll_list, | |
135 | .nr_sources = ARRAY_SIZE(clk_src_bpll_list), | |
136 | }; | |
137 | ||
57b317f9 KY |
138 | static struct clk *clk_src_bpll_fout_list[] = { |
139 | [0] = &clk_fout_bpll_div2, | |
140 | [1] = &clk_fout_bpll, | |
141 | }; | |
142 | ||
143 | struct clksrc_sources clk_src_bpll_fout = { | |
144 | .sources = clk_src_bpll_fout_list, | |
145 | .nr_sources = ARRAY_SIZE(clk_src_bpll_fout_list), | |
146 | }; | |
147 | ||
87b3c6ef KK |
148 | /* Possible clock sources for CPLL Mux */ |
149 | static struct clk *clk_src_cpll_list[] = { | |
150 | [0] = &clk_fin_cpll, | |
151 | [1] = &clk_fout_cpll, | |
152 | }; | |
153 | ||
154 | struct clksrc_sources clk_src_cpll = { | |
155 | .sources = clk_src_cpll_list, | |
156 | .nr_sources = ARRAY_SIZE(clk_src_cpll_list), | |
157 | }; | |
158 | ||
1a0e8a52 KK |
159 | /* Possible clock sources for MPLL Mux */ |
160 | static struct clk *clk_src_mpll_list[] = { | |
161 | [0] = &clk_fin_mpll, | |
162 | [1] = &clk_fout_mpll, | |
163 | }; | |
164 | ||
165 | struct clksrc_sources clk_src_mpll = { | |
166 | .sources = clk_src_mpll_list, | |
167 | .nr_sources = ARRAY_SIZE(clk_src_mpll_list), | |
168 | }; | |
169 | ||
57b317f9 KY |
170 | static struct clk *clk_src_mpll_fout_list[] = { |
171 | [0] = &clk_fout_mpll_div2, | |
172 | [1] = &clk_fout_mpll, | |
173 | }; | |
174 | ||
175 | struct clksrc_sources clk_src_mpll_fout = { | |
176 | .sources = clk_src_mpll_fout_list, | |
177 | .nr_sources = ARRAY_SIZE(clk_src_mpll_fout_list), | |
178 | }; | |
179 | ||
1a0e8a52 KK |
180 | /* Possible clock sources for EPLL Mux */ |
181 | static struct clk *clk_src_epll_list[] = { | |
182 | [0] = &clk_fin_epll, | |
183 | [1] = &clk_fout_epll, | |
184 | }; | |
185 | ||
186 | struct clksrc_sources clk_src_epll = { | |
187 | .sources = clk_src_epll_list, | |
188 | .nr_sources = ARRAY_SIZE(clk_src_epll_list), | |
189 | }; | |
190 | ||
3109e550 KK |
191 | /* Possible clock sources for DPLL Mux */ |
192 | static struct clk *clk_src_dpll_list[] = { | |
193 | [0] = &clk_fin_dpll, | |
194 | [1] = &clk_fout_dpll, | |
195 | }; | |
196 | ||
197 | struct clksrc_sources clk_src_dpll = { | |
198 | .sources = clk_src_dpll_list, | |
199 | .nr_sources = ARRAY_SIZE(clk_src_dpll_list), | |
200 | }; | |
201 | ||
0c1945d3 KK |
202 | struct clk clk_vpll = { |
203 | .name = "vpll", | |
204 | .id = -1, | |
205 | }; | |
206 | ||
1a0e8a52 KK |
207 | int s5p_gatectrl(void __iomem *reg, struct clk *clk, int enable) |
208 | { | |
209 | unsigned int ctrlbit = clk->ctrlbit; | |
210 | u32 con; | |
211 | ||
212 | con = __raw_readl(reg); | |
213 | con = enable ? (con | ctrlbit) : (con & ~ctrlbit); | |
214 | __raw_writel(con, reg); | |
215 | return 0; | |
216 | } | |
217 | ||
d4b34c6c SY |
218 | int s5p_epll_enable(struct clk *clk, int enable) |
219 | { | |
220 | unsigned int ctrlbit = clk->ctrlbit; | |
221 | unsigned int epll_con = __raw_readl(S5P_EPLL_CON) & ~ctrlbit; | |
222 | ||
223 | if (enable) | |
224 | __raw_writel(epll_con | ctrlbit, S5P_EPLL_CON); | |
225 | else | |
226 | __raw_writel(epll_con, S5P_EPLL_CON); | |
227 | ||
228 | return 0; | |
229 | } | |
230 | ||
231 | unsigned long s5p_epll_get_rate(struct clk *clk) | |
232 | { | |
233 | return clk->rate; | |
234 | } | |
235 | ||
65f5eaa2 NKC |
236 | int s5p_spdif_set_rate(struct clk *clk, unsigned long rate) |
237 | { | |
238 | struct clk *pclk; | |
239 | int ret; | |
240 | ||
241 | pclk = clk_get_parent(clk); | |
242 | if (IS_ERR(pclk)) | |
243 | return -EINVAL; | |
244 | ||
245 | ret = pclk->ops->set_rate(pclk, rate); | |
246 | clk_put(pclk); | |
247 | ||
248 | return ret; | |
249 | } | |
250 | ||
251 | unsigned long s5p_spdif_get_rate(struct clk *clk) | |
252 | { | |
253 | struct clk *pclk; | |
254 | int rate; | |
255 | ||
256 | pclk = clk_get_parent(clk); | |
257 | if (IS_ERR(pclk)) | |
258 | return -EINVAL; | |
259 | ||
5d747c6f | 260 | rate = pclk->ops->get_rate(pclk); |
65f5eaa2 NKC |
261 | clk_put(pclk); |
262 | ||
263 | return rate; | |
264 | } | |
265 | ||
266 | struct clk_ops s5p_sclk_spdif_ops = { | |
267 | .set_rate = s5p_spdif_set_rate, | |
268 | .get_rate = s5p_spdif_get_rate, | |
269 | }; | |
270 | ||
1a0e8a52 KK |
271 | static struct clk *s5p_clks[] __initdata = { |
272 | &clk_ext_xtal_mux, | |
273 | &clk_48m, | |
0c1945d3 | 274 | &s5p_clk_27m, |
1a0e8a52 KK |
275 | &clk_fout_apll, |
276 | &clk_fout_mpll, | |
277 | &clk_fout_epll, | |
3109e550 | 278 | &clk_fout_dpll, |
f445dbd5 | 279 | &clk_fout_vpll, |
0c1945d3 | 280 | &clk_vpll, |
8fb9d2d7 | 281 | &clk_xusbxti, |
1a0e8a52 KK |
282 | }; |
283 | ||
284 | void __init s5p_register_clocks(unsigned long xtal_freq) | |
285 | { | |
286 | int ret; | |
287 | ||
288 | clk_ext_xtal_mux.rate = xtal_freq; | |
289 | ||
290 | ret = s3c24xx_register_clocks(s5p_clks, ARRAY_SIZE(s5p_clks)); | |
291 | if (ret > 0) | |
292 | printk(KERN_ERR "Failed to register s5p clocks\n"); | |
293 | } |