Commit | Line | Data |
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bf46aaea | 1 | /* |
1a0e8a52 KK |
2 | * Copyright 2009 Samsung Electronics Co., Ltd. |
3 | * http://www.samsung.com/ | |
4 | * | |
5 | * S5P - Common clock support | |
6 | * | |
7 | * This program is free software; you can redistribute it and/or modify | |
8 | * it under the terms of the GNU General Public License version 2 as | |
9 | * published by the Free Software Foundation. | |
10 | */ | |
11 | ||
12 | #include <linux/init.h> | |
13 | #include <linux/module.h> | |
14 | #include <linux/kernel.h> | |
15 | #include <linux/list.h> | |
16 | #include <linux/errno.h> | |
17 | #include <linux/err.h> | |
18 | #include <linux/clk.h> | |
edbaa603 | 19 | #include <linux/device.h> |
1a0e8a52 KK |
20 | #include <linux/io.h> |
21 | #include <asm/div64.h> | |
22 | ||
d4b34c6c SY |
23 | #include <mach/regs-clock.h> |
24 | ||
1a0e8a52 KK |
25 | #include <plat/clock.h> |
26 | #include <plat/clock-clksrc.h> | |
27 | #include <plat/s5p-clock.h> | |
28 | ||
29 | /* fin_apll, fin_mpll and fin_epll are all the same clock, which we call | |
30 | * clk_ext_xtal_mux. | |
31 | */ | |
32 | struct clk clk_ext_xtal_mux = { | |
33 | .name = "ext_xtal", | |
34 | .id = -1, | |
35 | }; | |
36 | ||
f001d5b2 TA |
37 | struct clk clk_xusbxti = { |
38 | .name = "xusbxti", | |
39 | .id = -1, | |
40 | }; | |
41 | ||
a443a637 | 42 | struct clk s5p_clk_27m = { |
0c1945d3 KK |
43 | .name = "clk_27m", |
44 | .id = -1, | |
45 | .rate = 27000000, | |
46 | }; | |
47 | ||
1a0e8a52 KK |
48 | /* 48MHz USB Phy clock output */ |
49 | struct clk clk_48m = { | |
50 | .name = "clk_48m", | |
51 | .id = -1, | |
52 | .rate = 48000000, | |
53 | }; | |
54 | ||
55 | /* APLL clock output | |
56 | * No need .ctrlbit, this is always on | |
57 | */ | |
58 | struct clk clk_fout_apll = { | |
59 | .name = "fout_apll", | |
60 | .id = -1, | |
61 | }; | |
62 | ||
87b3c6ef KK |
63 | /* BPLL clock output */ |
64 | ||
65 | struct clk clk_fout_bpll = { | |
66 | .name = "fout_bpll", | |
67 | .id = -1, | |
68 | }; | |
69 | ||
70 | /* CPLL clock output */ | |
71 | ||
72 | struct clk clk_fout_cpll = { | |
73 | .name = "fout_cpll", | |
74 | .id = -1, | |
75 | }; | |
76 | ||
1a0e8a52 KK |
77 | /* MPLL clock output |
78 | * No need .ctrlbit, this is always on | |
79 | */ | |
80 | struct clk clk_fout_mpll = { | |
81 | .name = "fout_mpll", | |
82 | .id = -1, | |
83 | }; | |
84 | ||
85 | /* EPLL clock output */ | |
86 | struct clk clk_fout_epll = { | |
87 | .name = "fout_epll", | |
88 | .id = -1, | |
89 | .ctrlbit = (1 << 31), | |
90 | }; | |
91 | ||
3109e550 KK |
92 | /* DPLL clock output */ |
93 | struct clk clk_fout_dpll = { | |
94 | .name = "fout_dpll", | |
95 | .id = -1, | |
96 | .ctrlbit = (1 << 31), | |
97 | }; | |
98 | ||
f445dbd5 TA |
99 | /* VPLL clock output */ |
100 | struct clk clk_fout_vpll = { | |
101 | .name = "fout_vpll", | |
102 | .id = -1, | |
103 | .ctrlbit = (1 << 31), | |
104 | }; | |
105 | ||
1a0e8a52 KK |
106 | /* Possible clock sources for APLL Mux */ |
107 | static struct clk *clk_src_apll_list[] = { | |
108 | [0] = &clk_fin_apll, | |
109 | [1] = &clk_fout_apll, | |
110 | }; | |
111 | ||
112 | struct clksrc_sources clk_src_apll = { | |
113 | .sources = clk_src_apll_list, | |
114 | .nr_sources = ARRAY_SIZE(clk_src_apll_list), | |
115 | }; | |
116 | ||
87b3c6ef KK |
117 | /* Possible clock sources for BPLL Mux */ |
118 | static struct clk *clk_src_bpll_list[] = { | |
119 | [0] = &clk_fin_bpll, | |
120 | [1] = &clk_fout_bpll, | |
121 | }; | |
122 | ||
123 | struct clksrc_sources clk_src_bpll = { | |
124 | .sources = clk_src_bpll_list, | |
125 | .nr_sources = ARRAY_SIZE(clk_src_bpll_list), | |
126 | }; | |
127 | ||
128 | /* Possible clock sources for CPLL Mux */ | |
129 | static struct clk *clk_src_cpll_list[] = { | |
130 | [0] = &clk_fin_cpll, | |
131 | [1] = &clk_fout_cpll, | |
132 | }; | |
133 | ||
134 | struct clksrc_sources clk_src_cpll = { | |
135 | .sources = clk_src_cpll_list, | |
136 | .nr_sources = ARRAY_SIZE(clk_src_cpll_list), | |
137 | }; | |
138 | ||
1a0e8a52 KK |
139 | /* Possible clock sources for MPLL Mux */ |
140 | static struct clk *clk_src_mpll_list[] = { | |
141 | [0] = &clk_fin_mpll, | |
142 | [1] = &clk_fout_mpll, | |
143 | }; | |
144 | ||
145 | struct clksrc_sources clk_src_mpll = { | |
146 | .sources = clk_src_mpll_list, | |
147 | .nr_sources = ARRAY_SIZE(clk_src_mpll_list), | |
148 | }; | |
149 | ||
150 | /* Possible clock sources for EPLL Mux */ | |
151 | static struct clk *clk_src_epll_list[] = { | |
152 | [0] = &clk_fin_epll, | |
153 | [1] = &clk_fout_epll, | |
154 | }; | |
155 | ||
156 | struct clksrc_sources clk_src_epll = { | |
157 | .sources = clk_src_epll_list, | |
158 | .nr_sources = ARRAY_SIZE(clk_src_epll_list), | |
159 | }; | |
160 | ||
3109e550 KK |
161 | /* Possible clock sources for DPLL Mux */ |
162 | static struct clk *clk_src_dpll_list[] = { | |
163 | [0] = &clk_fin_dpll, | |
164 | [1] = &clk_fout_dpll, | |
165 | }; | |
166 | ||
167 | struct clksrc_sources clk_src_dpll = { | |
168 | .sources = clk_src_dpll_list, | |
169 | .nr_sources = ARRAY_SIZE(clk_src_dpll_list), | |
170 | }; | |
171 | ||
0c1945d3 KK |
172 | struct clk clk_vpll = { |
173 | .name = "vpll", | |
174 | .id = -1, | |
175 | }; | |
176 | ||
1a0e8a52 KK |
177 | int s5p_gatectrl(void __iomem *reg, struct clk *clk, int enable) |
178 | { | |
179 | unsigned int ctrlbit = clk->ctrlbit; | |
180 | u32 con; | |
181 | ||
182 | con = __raw_readl(reg); | |
183 | con = enable ? (con | ctrlbit) : (con & ~ctrlbit); | |
184 | __raw_writel(con, reg); | |
185 | return 0; | |
186 | } | |
187 | ||
d4b34c6c SY |
188 | int s5p_epll_enable(struct clk *clk, int enable) |
189 | { | |
190 | unsigned int ctrlbit = clk->ctrlbit; | |
191 | unsigned int epll_con = __raw_readl(S5P_EPLL_CON) & ~ctrlbit; | |
192 | ||
193 | if (enable) | |
194 | __raw_writel(epll_con | ctrlbit, S5P_EPLL_CON); | |
195 | else | |
196 | __raw_writel(epll_con, S5P_EPLL_CON); | |
197 | ||
198 | return 0; | |
199 | } | |
200 | ||
201 | unsigned long s5p_epll_get_rate(struct clk *clk) | |
202 | { | |
203 | return clk->rate; | |
204 | } | |
205 | ||
65f5eaa2 NKC |
206 | int s5p_spdif_set_rate(struct clk *clk, unsigned long rate) |
207 | { | |
208 | struct clk *pclk; | |
209 | int ret; | |
210 | ||
211 | pclk = clk_get_parent(clk); | |
212 | if (IS_ERR(pclk)) | |
213 | return -EINVAL; | |
214 | ||
215 | ret = pclk->ops->set_rate(pclk, rate); | |
216 | clk_put(pclk); | |
217 | ||
218 | return ret; | |
219 | } | |
220 | ||
221 | unsigned long s5p_spdif_get_rate(struct clk *clk) | |
222 | { | |
223 | struct clk *pclk; | |
224 | int rate; | |
225 | ||
226 | pclk = clk_get_parent(clk); | |
227 | if (IS_ERR(pclk)) | |
228 | return -EINVAL; | |
229 | ||
5d747c6f | 230 | rate = pclk->ops->get_rate(pclk); |
65f5eaa2 NKC |
231 | clk_put(pclk); |
232 | ||
233 | return rate; | |
234 | } | |
235 | ||
236 | struct clk_ops s5p_sclk_spdif_ops = { | |
237 | .set_rate = s5p_spdif_set_rate, | |
238 | .get_rate = s5p_spdif_get_rate, | |
239 | }; | |
240 | ||
1a0e8a52 KK |
241 | static struct clk *s5p_clks[] __initdata = { |
242 | &clk_ext_xtal_mux, | |
243 | &clk_48m, | |
0c1945d3 | 244 | &s5p_clk_27m, |
1a0e8a52 KK |
245 | &clk_fout_apll, |
246 | &clk_fout_mpll, | |
247 | &clk_fout_epll, | |
3109e550 | 248 | &clk_fout_dpll, |
f445dbd5 | 249 | &clk_fout_vpll, |
0c1945d3 | 250 | &clk_vpll, |
8fb9d2d7 | 251 | &clk_xusbxti, |
1a0e8a52 KK |
252 | }; |
253 | ||
254 | void __init s5p_register_clocks(unsigned long xtal_freq) | |
255 | { | |
256 | int ret; | |
257 | ||
258 | clk_ext_xtal_mux.rate = xtal_freq; | |
259 | ||
260 | ret = s3c24xx_register_clocks(s5p_clks, ARRAY_SIZE(s5p_clks)); | |
261 | if (ret > 0) | |
262 | printk(KERN_ERR "Failed to register s5p clocks\n"); | |
263 | } |