Commit | Line | Data |
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68ae8998 | 1 | /* |
0df04f82 JL |
2 | * Copyright (c) 2010 Samsung Electronics Co., Ltd. |
3 | * http://www.samsung.com | |
4 | * | |
5 | * S5P - IRQ EINT support | |
6 | * | |
7 | * This program is free software; you can redistribute it and/or modify | |
8 | * it under the terms of the GNU General Public License version 2 as | |
9 | * published by the Free Software Foundation. | |
10 | */ | |
11 | ||
12 | #include <linux/kernel.h> | |
13 | #include <linux/interrupt.h> | |
14 | #include <linux/irq.h> | |
15 | #include <linux/io.h> | |
edbaa603 | 16 | #include <linux/device.h> |
0df04f82 | 17 | #include <linux/gpio.h> |
9e47b8bf | 18 | #include <linux/irqchip/arm-vic.h> |
bffd649d | 19 | #include <linux/of.h> |
0df04f82 JL |
20 | |
21 | #include <plat/regs-irqtype.h> | |
22 | ||
23 | #include <mach/map.h> | |
24 | #include <plat/cpu.h> | |
25 | #include <plat/pm.h> | |
26 | ||
27 | #include <plat/gpio-cfg.h> | |
28 | #include <mach/regs-gpio.h> | |
29 | ||
bb0b2374 | 30 | static inline void s5p_irq_eint_mask(struct irq_data *data) |
0df04f82 JL |
31 | { |
32 | u32 mask; | |
33 | ||
bb0b2374 LB |
34 | mask = __raw_readl(S5P_EINT_MASK(EINT_REG_NR(data->irq))); |
35 | mask |= eint_irq_to_bit(data->irq); | |
36 | __raw_writel(mask, S5P_EINT_MASK(EINT_REG_NR(data->irq))); | |
0df04f82 JL |
37 | } |
38 | ||
bb0b2374 | 39 | static void s5p_irq_eint_unmask(struct irq_data *data) |
0df04f82 JL |
40 | { |
41 | u32 mask; | |
42 | ||
bb0b2374 LB |
43 | mask = __raw_readl(S5P_EINT_MASK(EINT_REG_NR(data->irq))); |
44 | mask &= ~(eint_irq_to_bit(data->irq)); | |
45 | __raw_writel(mask, S5P_EINT_MASK(EINT_REG_NR(data->irq))); | |
0df04f82 JL |
46 | } |
47 | ||
bb0b2374 | 48 | static inline void s5p_irq_eint_ack(struct irq_data *data) |
0df04f82 | 49 | { |
bb0b2374 LB |
50 | __raw_writel(eint_irq_to_bit(data->irq), |
51 | S5P_EINT_PEND(EINT_REG_NR(data->irq))); | |
0df04f82 JL |
52 | } |
53 | ||
bb0b2374 | 54 | static void s5p_irq_eint_maskack(struct irq_data *data) |
0df04f82 JL |
55 | { |
56 | /* compiler should in-line these */ | |
bb0b2374 LB |
57 | s5p_irq_eint_mask(data); |
58 | s5p_irq_eint_ack(data); | |
0df04f82 JL |
59 | } |
60 | ||
bb0b2374 | 61 | static int s5p_irq_eint_set_type(struct irq_data *data, unsigned int type) |
0df04f82 | 62 | { |
bb0b2374 | 63 | int offs = EINT_OFFSET(data->irq); |
0df04f82 JL |
64 | int shift; |
65 | u32 ctrl, mask; | |
66 | u32 newvalue = 0; | |
67 | ||
68 | switch (type) { | |
69 | case IRQ_TYPE_EDGE_RISING: | |
9adf5d22 | 70 | newvalue = S5P_IRQ_TYPE_EDGE_RISING; |
0df04f82 JL |
71 | break; |
72 | ||
73 | case IRQ_TYPE_EDGE_FALLING: | |
9adf5d22 | 74 | newvalue = S5P_IRQ_TYPE_EDGE_FALLING; |
0df04f82 JL |
75 | break; |
76 | ||
77 | case IRQ_TYPE_EDGE_BOTH: | |
9adf5d22 | 78 | newvalue = S5P_IRQ_TYPE_EDGE_BOTH; |
0df04f82 JL |
79 | break; |
80 | ||
81 | case IRQ_TYPE_LEVEL_LOW: | |
9adf5d22 | 82 | newvalue = S5P_IRQ_TYPE_LEVEL_LOW; |
0df04f82 JL |
83 | break; |
84 | ||
85 | case IRQ_TYPE_LEVEL_HIGH: | |
9adf5d22 | 86 | newvalue = S5P_IRQ_TYPE_LEVEL_HIGH; |
0df04f82 JL |
87 | break; |
88 | ||
89 | default: | |
90 | printk(KERN_ERR "No such irq type %d", type); | |
91 | return -EINVAL; | |
92 | } | |
93 | ||
94 | shift = (offs & 0x7) * 4; | |
95 | mask = 0x7 << shift; | |
96 | ||
bb0b2374 | 97 | ctrl = __raw_readl(S5P_EINT_CON(EINT_REG_NR(data->irq))); |
0df04f82 JL |
98 | ctrl &= ~mask; |
99 | ctrl |= newvalue << shift; | |
bb0b2374 | 100 | __raw_writel(ctrl, S5P_EINT_CON(EINT_REG_NR(data->irq))); |
0df04f82 JL |
101 | |
102 | if ((0 <= offs) && (offs < 8)) | |
103 | s3c_gpio_cfgpin(EINT_GPIO_0(offs & 0x7), EINT_MODE); | |
104 | ||
105 | else if ((8 <= offs) && (offs < 16)) | |
106 | s3c_gpio_cfgpin(EINT_GPIO_1(offs & 0x7), EINT_MODE); | |
107 | ||
108 | else if ((16 <= offs) && (offs < 24)) | |
109 | s3c_gpio_cfgpin(EINT_GPIO_2(offs & 0x7), EINT_MODE); | |
110 | ||
111 | else if ((24 <= offs) && (offs < 32)) | |
112 | s3c_gpio_cfgpin(EINT_GPIO_3(offs & 0x7), EINT_MODE); | |
113 | ||
114 | else | |
115 | printk(KERN_ERR "No such irq number %d", offs); | |
116 | ||
117 | return 0; | |
118 | } | |
119 | ||
120 | static struct irq_chip s5p_irq_eint = { | |
121 | .name = "s5p-eint", | |
bb0b2374 LB |
122 | .irq_mask = s5p_irq_eint_mask, |
123 | .irq_unmask = s5p_irq_eint_unmask, | |
124 | .irq_mask_ack = s5p_irq_eint_maskack, | |
125 | .irq_ack = s5p_irq_eint_ack, | |
126 | .irq_set_type = s5p_irq_eint_set_type, | |
0df04f82 | 127 | #ifdef CONFIG_PM |
f5aeffb7 | 128 | .irq_set_wake = s3c_irqext_wake, |
0df04f82 JL |
129 | #endif |
130 | }; | |
131 | ||
132 | /* s5p_irq_demux_eint | |
133 | * | |
134 | * This function demuxes the IRQ from the group0 external interrupts, | |
135 | * from EINTs 16 to 31. It is designed to be inlined into the specific | |
136 | * handler s5p_irq_demux_eintX_Y. | |
137 | * | |
138 | * Each EINT pend/mask registers handle eight of them. | |
139 | */ | |
140 | static inline void s5p_irq_demux_eint(unsigned int start) | |
141 | { | |
5fae4058 | 142 | u32 status = __raw_readl(S5P_EINT_PEND(EINT_REG_NR(start))); |
0df04f82 JL |
143 | u32 mask = __raw_readl(S5P_EINT_MASK(EINT_REG_NR(start))); |
144 | unsigned int irq; | |
145 | ||
0df04f82 JL |
146 | status &= ~mask; |
147 | status &= 0xff; | |
148 | ||
149 | while (status) { | |
5fae4058 PB |
150 | irq = fls(status) - 1; |
151 | generic_handle_irq(irq + start); | |
0df04f82 JL |
152 | status &= ~(1 << irq); |
153 | } | |
154 | } | |
155 | ||
156 | static void s5p_irq_demux_eint16_31(unsigned int irq, struct irq_desc *desc) | |
157 | { | |
158 | s5p_irq_demux_eint(IRQ_EINT(16)); | |
159 | s5p_irq_demux_eint(IRQ_EINT(24)); | |
160 | } | |
161 | ||
bb0b2374 | 162 | static inline void s5p_irq_vic_eint_mask(struct irq_data *data) |
0df04f82 | 163 | { |
bb0b2374 | 164 | void __iomem *base = irq_data_get_irq_chip_data(data); |
5fae4058 | 165 | |
bb0b2374 LB |
166 | s5p_irq_eint_mask(data); |
167 | writel(1 << EINT_OFFSET(data->irq), base + VIC_INT_ENABLE_CLEAR); | |
0df04f82 JL |
168 | } |
169 | ||
bb0b2374 | 170 | static void s5p_irq_vic_eint_unmask(struct irq_data *data) |
0df04f82 | 171 | { |
bb0b2374 | 172 | void __iomem *base = irq_data_get_irq_chip_data(data); |
5fae4058 | 173 | |
bb0b2374 LB |
174 | s5p_irq_eint_unmask(data); |
175 | writel(1 << EINT_OFFSET(data->irq), base + VIC_INT_ENABLE); | |
0df04f82 JL |
176 | } |
177 | ||
bb0b2374 | 178 | static inline void s5p_irq_vic_eint_ack(struct irq_data *data) |
0df04f82 | 179 | { |
bb0b2374 LB |
180 | __raw_writel(eint_irq_to_bit(data->irq), |
181 | S5P_EINT_PEND(EINT_REG_NR(data->irq))); | |
0df04f82 JL |
182 | } |
183 | ||
bb0b2374 | 184 | static void s5p_irq_vic_eint_maskack(struct irq_data *data) |
0df04f82 | 185 | { |
bb0b2374 LB |
186 | s5p_irq_vic_eint_mask(data); |
187 | s5p_irq_vic_eint_ack(data); | |
0df04f82 JL |
188 | } |
189 | ||
190 | static struct irq_chip s5p_irq_vic_eint = { | |
191 | .name = "s5p_vic_eint", | |
bb0b2374 LB |
192 | .irq_mask = s5p_irq_vic_eint_mask, |
193 | .irq_unmask = s5p_irq_vic_eint_unmask, | |
194 | .irq_mask_ack = s5p_irq_vic_eint_maskack, | |
195 | .irq_ack = s5p_irq_vic_eint_ack, | |
196 | .irq_set_type = s5p_irq_eint_set_type, | |
0df04f82 | 197 | #ifdef CONFIG_PM |
f5aeffb7 | 198 | .irq_set_wake = s3c_irqext_wake, |
0df04f82 JL |
199 | #endif |
200 | }; | |
201 | ||
6d259a25 | 202 | static int __init s5p_init_irq_eint(void) |
0df04f82 JL |
203 | { |
204 | int irq; | |
205 | ||
bffd649d MK |
206 | if (of_have_populated_dt()) |
207 | return -ENODEV; | |
208 | ||
0df04f82 | 209 | for (irq = IRQ_EINT(0); irq <= IRQ_EINT(15); irq++) |
6845664a | 210 | irq_set_chip(irq, &s5p_irq_vic_eint); |
0df04f82 JL |
211 | |
212 | for (irq = IRQ_EINT(16); irq <= IRQ_EINT(31); irq++) { | |
f38c02f3 | 213 | irq_set_chip_and_handler(irq, &s5p_irq_eint, handle_level_irq); |
0df04f82 JL |
214 | set_irq_flags(irq, IRQF_VALID); |
215 | } | |
216 | ||
6845664a | 217 | irq_set_chained_handler(IRQ_EINT16_31, s5p_irq_demux_eint16_31); |
0df04f82 JL |
218 | return 0; |
219 | } | |
220 | ||
221 | arch_initcall(s5p_init_irq_eint); |