[deliverable/linux.git] / arch / arm / plat-samsung / s5p-irq-gpioint.c

/*
 * Copyright (c) 2010 Samsung Electronics Co., Ltd.
 * Author: Kyungmin Park <kyungmin.park@samsung.com>
 * Author: Joonyoung Shim <jy0922.shim@samsung.com>
 * Author: Marek Szyprowski <m.szyprowski@samsung.com>
 *
 *  This program is free software; you can redistribute  it and/or modify it
 *  under  the terms of  the GNU General  Public License as published by the
 *  Free Software Foundation;  either version 2 of the  License, or (at your
 *  option) any later version.
 *
 */

#include <linux/kernel.h>
#include <linux/interrupt.h>
#include <linux/irq.h>
#include <linux/irqchip/chained_irq.h>
#include <linux/io.h>
#include <linux/gpio.h>
#include <linux/slab.h>

#include <mach/map.h>
#include <plat/gpio-core.h>
#include <plat/gpio-cfg.h>

#define GPIO_BASE(chip)		((void __iomem *)((unsigned long)((chip)->base) & 0xFFFFF000u))

#define CON_OFFSET		0x700
#define MASK_OFFSET		0x900
#define PEND_OFFSET		0xA00
#define REG_OFFSET(x)		((x) << 2)

struct s5p_gpioint_bank {
	struct list_head	list;
	int			start;
	int			nr_groups;
	int			irq;
	struct samsung_gpio_chip	**chips;
	void			(*handler)(unsigned int, struct irq_desc *);
};

static LIST_HEAD(banks);

static int s5p_gpioint_set_type(struct irq_data *d, unsigned int type)
{
	struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
	struct irq_chip_type *ct = gc->chip_types;
	unsigned int shift = (d->irq - gc->irq_base) << 2;

	switch (type) {
	case IRQ_TYPE_EDGE_RISING:
		type = S5P_IRQ_TYPE_EDGE_RISING;
		break;
	case IRQ_TYPE_EDGE_FALLING:
		type = S5P_IRQ_TYPE_EDGE_FALLING;
		break;
	case IRQ_TYPE_EDGE_BOTH:
		type = S5P_IRQ_TYPE_EDGE_BOTH;
		break;
	case IRQ_TYPE_LEVEL_HIGH:
		type = S5P_IRQ_TYPE_LEVEL_HIGH;
		break;
	case IRQ_TYPE_LEVEL_LOW:
		type = S5P_IRQ_TYPE_LEVEL_LOW;
		break;
	case IRQ_TYPE_NONE:
	default:
		printk(KERN_WARNING "No irq type\n");
		return -EINVAL;
	}

	gc->type_cache &= ~(0x7 << shift);
	gc->type_cache |= type << shift;
	writel(gc->type_cache, gc->reg_base + ct->regs.type);
	return 0;
}

static void s5p_gpioint_handler(unsigned int irq, struct irq_desc *desc)
{
	struct s5p_gpioint_bank *bank = irq_get_handler_data(irq);
	int group, pend_offset, mask_offset;
	unsigned int pend, mask;

	struct irq_chip *chip = irq_get_chip(irq);
	chained_irq_enter(chip, desc);

	for (group = 0; group < bank->nr_groups; group++) {
		struct samsung_gpio_chip *chip = bank->chips[group];
		if (!chip)
			continue;

		pend_offset = REG_OFFSET(group);
		pend = __raw_readl(GPIO_BASE(chip) + PEND_OFFSET + pend_offset);
		if (!pend)
			continue;

		mask_offset = REG_OFFSET(group);
		mask = __raw_readl(GPIO_BASE(chip) + MASK_OFFSET + mask_offset);
		pend &= ~mask;

		while (pend) {
			int offset = fls(pend) - 1;
			int real_irq = chip->irq_base + offset;
			generic_handle_irq(real_irq);
			pend &= ~BIT(offset);
		}
	}
	chained_irq_exit(chip, desc);
}

static __init int s5p_gpioint_add(struct samsung_gpio_chip *chip)
{
	static int used_gpioint_groups = 0;
	int group = chip->group;
	struct s5p_gpioint_bank *b, *bank = NULL;
	struct irq_chip_generic *gc;
	struct irq_chip_type *ct;

	if (used_gpioint_groups >= S5P_GPIOINT_GROUP_COUNT)
		return -ENOMEM;

	list_for_each_entry(b, &banks, list) {
		if (group >= b->start && group < b->start + b->nr_groups) {
			bank = b;
			break;
		}
	}
	if (!bank)
		return -EINVAL;

	if (!bank->handler) {
		bank->chips = kzalloc(sizeof(struct samsung_gpio_chip *) *
				      bank->nr_groups, GFP_KERNEL);
		if (!bank->chips)
			return -ENOMEM;

		irq_set_chained_handler(bank->irq, s5p_gpioint_handler);
		irq_set_handler_data(bank->irq, bank);
		bank->handler = s5p_gpioint_handler;
		printk(KERN_INFO "Registered chained gpio int handler for interrupt %d.\n",
		       bank->irq);
	}

	/*
	 * chained GPIO irq has been successfully registered, allocate new gpio
	 * int group and assign irq nubmers
	 */
	chip->irq_base = S5P_GPIOINT_BASE +
			 used_gpioint_groups * S5P_GPIOINT_GROUP_SIZE;
	used_gpioint_groups++;

	bank->chips[group - bank->start] = chip;

	gc = irq_alloc_generic_chip("s5p_gpioint", 1, chip->irq_base,
				    GPIO_BASE(chip),
				    handle_level_irq);
	if (!gc)
		return -ENOMEM;
	ct = gc->chip_types;
	ct->chip.irq_ack = irq_gc_ack_set_bit;
	ct->chip.irq_mask = irq_gc_mask_set_bit;
	ct->chip.irq_unmask = irq_gc_mask_clr_bit;
	ct->chip.irq_set_type = s5p_gpioint_set_type,
	ct->regs.ack = PEND_OFFSET + REG_OFFSET(group - bank->start);
	ct->regs.mask = MASK_OFFSET + REG_OFFSET(group - bank->start);
	ct->regs.type = CON_OFFSET + REG_OFFSET(group - bank->start);
	irq_setup_generic_chip(gc, IRQ_MSK(chip->chip.ngpio),
			       IRQ_GC_INIT_MASK_CACHE,
			       IRQ_NOREQUEST | IRQ_NOPROBE, 0);
	return 0;
}

int __init s5p_register_gpio_interrupt(int pin)
{
	struct samsung_gpio_chip *my_chip = samsung_gpiolib_getchip(pin);
	int offset, group;
	int ret;

	if (!my_chip)
		return -EINVAL;

	offset = pin - my_chip->chip.base;
	group = my_chip->group;

	/* check if the group has been already registered */
	if (my_chip->irq_base)
		goto success;

	/* register gpio group */
	ret = s5p_gpioint_add(my_chip);
	if (ret == 0) {
		my_chip->chip.to_irq = samsung_gpiolib_to_irq;
		printk(KERN_INFO "Registered interrupt support for gpio group %d.\n",
		       group);
		goto success;
	}
	return ret;
success:
	my_chip->bitmap_gpio_int |= BIT(offset);

	return my_chip->irq_base + offset;
}

int __init s5p_register_gpioint_bank(int chain_irq, int start, int nr_groups)
{
	struct s5p_gpioint_bank *bank;

	bank = kzalloc(sizeof(*bank), GFP_KERNEL);
	if (!bank)
		return -ENOMEM;

	bank->start = start;
	bank->nr_groups = nr_groups;
	bank->irq = chain_irq;

	list_add_tail(&bank->list, &banks);
	return 0;
}
Commit	Line	Data
68ae8998	1	/*
170a4617 MS	2	* Copyright (c) 2010 Samsung Electronics Co., Ltd.
	3	* Author: Kyungmin Park <kyungmin.park@samsung.com>
	4	* Author: Joonyoung Shim <jy0922.shim@samsung.com>
	5	* Author: Marek Szyprowski <m.szyprowski@samsung.com>
	6	*
	7	* This program is free software; you can redistribute it and/or modify it
	8	* under the terms of the GNU General Public License as published by the
	9	* Free Software Foundation; either version 2 of the License, or (at your
	10	* option) any later version.
	11	*
	12	*/
	13
	14	#include <linux/kernel.h>
	15	#include <linux/interrupt.h>
	16	#include <linux/irq.h>
de88cbb7	17	#include <linux/irqchip/chained_irq.h>
170a4617 MS	18	#include <linux/io.h>
170a4617 MS	19	#include <linux/gpio.h>
a43efddc	20	#include <linux/slab.h>
170a4617 MS	21
	22	#include <mach/map.h>
	23	#include <plat/gpio-core.h>
	24	#include <plat/gpio-cfg.h>
	25
5fa1a2e1	26	#define GPIO_BASE(chip) ((void __iomem *)((unsigned long)((chip)->base) & 0xFFFFF000u))
170a4617	27
2de09262 MS	28	#define CON_OFFSET 0x700
	29	#define MASK_OFFSET 0x900
	30	#define PEND_OFFSET 0xA00
	31	#define REG_OFFSET(x) ((x) << 2)
170a4617	32
a43efddc MS	33	struct s5p_gpioint_bank {
	34	struct list_head list;
	35	int start;
	36	int nr_groups;
	37	int irq;
782d8a3c	38	struct samsung_gpio_chip **chips;
a43efddc MS	39	void (handler)(unsigned int, struct irq_desc );
	40	};
	41
6d259a25	42	static LIST_HEAD(banks);
170a4617	43
ad739dcf	44	static int s5p_gpioint_set_type(struct irq_data *d, unsigned int type)
170a4617	45	{
ad739dcf TG	46	struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
	47	struct irq_chip_type *ct = gc->chip_types;
	48	unsigned int shift = (d->irq - gc->irq_base) << 2;
170a4617 MS	49
	50	switch (type) {
	51	case IRQ_TYPE_EDGE_RISING:
9adf5d22	52	type = S5P_IRQ_TYPE_EDGE_RISING;
170a4617 MS	53	break;
170a4617 MS	54	case IRQ_TYPE_EDGE_FALLING:
9adf5d22	55	type = S5P_IRQ_TYPE_EDGE_FALLING;
170a4617 MS	56	break;
170a4617 MS	57	case IRQ_TYPE_EDGE_BOTH:
9adf5d22	58	type = S5P_IRQ_TYPE_EDGE_BOTH;
170a4617 MS	59	break;
170a4617 MS	60	case IRQ_TYPE_LEVEL_HIGH:
9adf5d22	61	type = S5P_IRQ_TYPE_LEVEL_HIGH;
170a4617 MS	62	break;
170a4617 MS	63	case IRQ_TYPE_LEVEL_LOW:
9adf5d22	64	type = S5P_IRQ_TYPE_LEVEL_LOW;
170a4617 MS	65	break;
	66	case IRQ_TYPE_NONE:
	67	default:
	68	printk(KERN_WARNING "No irq type\n");
	69	return -EINVAL;
	70	}
	71
ad739dcf TG	72	gc->type_cache &= ~(0x7 << shift);
	73	gc->type_cache \|= type << shift;
	74	writel(gc->type_cache, gc->reg_base + ct->regs.type);
170a4617 MS	75	return 0;
	76	}
	77
170a4617 MS	78	static void s5p_gpioint_handler(unsigned int irq, struct irq_desc *desc)
170a4617 MS	79	{
6845664a	80	struct s5p_gpioint_bank *bank = irq_get_handler_data(irq);
2de09262	81	int group, pend_offset, mask_offset;
170a4617 MS	82	unsigned int pend, mask;
170a4617 MS	83
3f6065dd MS	84	struct irq_chip *chip = irq_get_chip(irq);
	85	chained_irq_enter(chip, desc);
	86
a43efddc	87	for (group = 0; group < bank->nr_groups; group++) {
782d8a3c	88	struct samsung_gpio_chip *chip = bank->chips[group];
2de09262 MS	89	if (!chip)
	90	continue;
	91
	92	pend_offset = REG_OFFSET(group);
	93	pend = __raw_readl(GPIO_BASE(chip) + PEND_OFFSET + pend_offset);
170a4617 MS	94	if (!pend)
	95	continue;
	96
2de09262 MS	97	mask_offset = REG_OFFSET(group);
2de09262 MS	98	mask = __raw_readl(GPIO_BASE(chip) + MASK_OFFSET + mask_offset);
170a4617 MS	99	pend &= ~mask;
170a4617 MS	100
2de09262 MS	101	while (pend) {
	102	int offset = fls(pend) - 1;
	103	int real_irq = chip->irq_base + offset;
	104	generic_handle_irq(real_irq);
	105	pend &= ~BIT(offset);
170a4617 MS	106	}
170a4617 MS	107	}
3f6065dd	108	chained_irq_exit(chip, desc);
170a4617 MS	109	}
170a4617 MS	110
782d8a3c	111	static __init int s5p_gpioint_add(struct samsung_gpio_chip *chip)
170a4617 MS	112	{
170a4617 MS	113	static int used_gpioint_groups = 0;
ad739dcf	114	int group = chip->group;
b76f7cdc	115	struct s5p_gpioint_bank b, bank = NULL;
ad739dcf TG	116	struct irq_chip_generic *gc;
ad739dcf TG	117	struct irq_chip_type *ct;
170a4617 MS	118
	119	if (used_gpioint_groups >= S5P_GPIOINT_GROUP_COUNT)
	120	return -ENOMEM;
	121
b76f7cdc MS	122	list_for_each_entry(b, &banks, list) {
	123	if (group >= b->start && group < b->start + b->nr_groups) {
	124	bank = b;
a43efddc	125	break;
b76f7cdc	126	}
a43efddc MS	127	}
	128	if (!bank)
	129	return -EINVAL;
	130
	131	if (!bank->handler) {
782d8a3c	132	bank->chips = kzalloc(sizeof(struct samsung_gpio_chip )
a43efddc MS	133	bank->nr_groups, GFP_KERNEL);
	134	if (!bank->chips)
	135	return -ENOMEM;
	136
6845664a TG	137	irq_set_chained_handler(bank->irq, s5p_gpioint_handler);
6845664a TG	138	irq_set_handler_data(bank->irq, bank);
a43efddc MS	139	bank->handler = s5p_gpioint_handler;
	140	printk(KERN_INFO "Registered chained gpio int handler for interrupt %d.\n",
	141	bank->irq);
	142	}
	143
	144	/*
25985edc	145	* chained GPIO irq has been successfully registered, allocate new gpio
a43efddc MS	146	* int group and assign irq nubmers
a43efddc MS	147	*/
170a4617 MS	148	chip->irq_base = S5P_GPIOINT_BASE +
	149	used_gpioint_groups * S5P_GPIOINT_GROUP_SIZE;
	150	used_gpioint_groups++;
	151
a43efddc	152	bank->chips[group - bank->start] = chip;
ad739dcf TG	153
ad739dcf TG	154	gc = irq_alloc_generic_chip("s5p_gpioint", 1, chip->irq_base,
5fa1a2e1	155	GPIO_BASE(chip),
ad739dcf TG	156	handle_level_irq);
	157	if (!gc)
	158	return -ENOMEM;
	159	ct = gc->chip_types;
659fb32d	160	ct->chip.irq_ack = irq_gc_ack_set_bit;
ad739dcf TG	161	ct->chip.irq_mask = irq_gc_mask_set_bit;
	162	ct->chip.irq_unmask = irq_gc_mask_clr_bit;
	163	ct->chip.irq_set_type = s5p_gpioint_set_type,
1052cff3 MS	164	ct->regs.ack = PEND_OFFSET + REG_OFFSET(group - bank->start);
	165	ct->regs.mask = MASK_OFFSET + REG_OFFSET(group - bank->start);
	166	ct->regs.type = CON_OFFSET + REG_OFFSET(group - bank->start);
ad739dcf TG	167	irq_setup_generic_chip(gc, IRQ_MSK(chip->chip.ngpio),
	168	IRQ_GC_INIT_MASK_CACHE,
	169	IRQ_NOREQUEST \| IRQ_NOPROBE, 0);
170a4617 MS	170	return 0;
	171	}
	172
	173	int __init s5p_register_gpio_interrupt(int pin)
	174	{
782d8a3c	175	struct samsung_gpio_chip *my_chip = samsung_gpiolib_getchip(pin);
170a4617 MS	176	int offset, group;
	177	int ret;
	178
	179	if (!my_chip)
	180	return -EINVAL;
	181
	182	offset = pin - my_chip->chip.base;
	183	group = my_chip->group;
	184
	185	/* check if the group has been already registered */
	186	if (my_chip->irq_base)
453e2dd7	187	goto success;
170a4617 MS	188
	189	/* register gpio group */
	190	ret = s5p_gpioint_add(my_chip);
	191	if (ret == 0) {
8ce14a22	192	my_chip->chip.to_irq = samsung_gpiolib_to_irq;
170a4617 MS	193	printk(KERN_INFO "Registered interrupt support for gpio group %d.\n",
170a4617 MS	194	group);
453e2dd7	195	goto success;
170a4617 MS	196	}
170a4617 MS	197	return ret;
453e2dd7 EK	198	success:
	199	my_chip->bitmap_gpio_int \|= BIT(offset);
	200
	201	return my_chip->irq_base + offset;
170a4617	202	}
a43efddc MS	203
	204	int __init s5p_register_gpioint_bank(int chain_irq, int start, int nr_groups)
	205	{
	206	struct s5p_gpioint_bank *bank;
	207
	208	bank = kzalloc(sizeof(*bank), GFP_KERNEL);
	209	if (!bank)
	210	return -ENOMEM;
	211
	212	bank->start = start;
	213	bank->nr_groups = nr_groups;
	214	bank->irq = chain_irq;
	215
	216	list_add_tail(&bank->list, &banks);
	217	return 0;
	218	}