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8eadcf74 | 1 | /* |
ea31fd43 JL |
2 | * Copyright (c) 2010 Samsung Electronics Co., Ltd. |
3 | * http://www.samsung.com | |
4 | * | |
5 | * Based on arch/arm/plat-s3c24xx/irq-pm.c, | |
6 | * Copyright (c) 2003,2004 Simtec Electronics | |
7 | * Ben Dooks <ben@simtec.co.uk> | |
8 | * http://armlinux.simtec.co.uk/ | |
9 | * | |
10 | * This program is free software; you can redistribute it and/or modify | |
11 | * it under the terms of the GNU General Public License version 2 as | |
12 | * published by the Free Software Foundation. | |
13 | */ | |
14 | ||
15 | #include <linux/init.h> | |
16 | #include <linux/module.h> | |
17 | #include <linux/interrupt.h> | |
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18 | |
19 | #include <plat/cpu.h> | |
20 | #include <plat/irqs.h> | |
21 | #include <plat/pm.h> | |
22 | #include <mach/map.h> | |
23 | ||
24 | #include <mach/regs-gpio.h> | |
25 | #include <mach/regs-irq.h> | |
26 | ||
27 | /* state for IRQs over sleep */ | |
28 | ||
29 | /* default is to allow for EINT0..EINT31, and IRQ_RTC_TIC, IRQ_RTC_ALARM, | |
30 | * as wakeup sources | |
31 | * | |
32 | * set bit to 1 in allow bitfield to enable the wakeup settings on it | |
33 | */ | |
34 | ||
35 | unsigned long s3c_irqwake_intallow = 0x00000006L; | |
36 | unsigned long s3c_irqwake_eintallow = 0xffffffffL; | |
37 | ||
bb0b2374 | 38 | int s3c_irq_wake(struct irq_data *data, unsigned int state) |
ea31fd43 JL |
39 | { |
40 | unsigned long irqbit; | |
bb19a751 KK |
41 | unsigned int irq_rtc_tic, irq_rtc_alarm; |
42 | ||
43 | #ifdef CONFIG_ARCH_EXYNOS | |
44 | if (soc_is_exynos5250()) { | |
45 | irq_rtc_tic = EXYNOS5_IRQ_RTC_TIC; | |
46 | irq_rtc_alarm = EXYNOS5_IRQ_RTC_ALARM; | |
47 | } else { | |
48 | irq_rtc_tic = EXYNOS4_IRQ_RTC_TIC; | |
49 | irq_rtc_alarm = EXYNOS4_IRQ_RTC_ALARM; | |
50 | } | |
51 | #else | |
52 | irq_rtc_tic = IRQ_RTC_TIC; | |
53 | irq_rtc_alarm = IRQ_RTC_ALARM; | |
54 | #endif | |
55 | ||
56 | if (data->irq == irq_rtc_tic || data->irq == irq_rtc_alarm) { | |
57 | irqbit = 1 << (data->irq + 1 - irq_rtc_alarm); | |
ea31fd43 | 58 | |
ea31fd43 JL |
59 | if (!state) |
60 | s3c_irqwake_intmask |= irqbit; | |
61 | else | |
62 | s3c_irqwake_intmask &= ~irqbit; | |
bb19a751 | 63 | } else { |
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64 | return -ENOENT; |
65 | } | |
bb19a751 | 66 | |
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67 | return 0; |
68 | } | |
69 | ||
70 | static struct sleep_save eint_save[] = { | |
71 | SAVE_ITEM(S5P_EINT_CON(0)), | |
72 | SAVE_ITEM(S5P_EINT_CON(1)), | |
73 | SAVE_ITEM(S5P_EINT_CON(2)), | |
74 | SAVE_ITEM(S5P_EINT_CON(3)), | |
75 | ||
76 | SAVE_ITEM(S5P_EINT_FLTCON(0)), | |
77 | SAVE_ITEM(S5P_EINT_FLTCON(1)), | |
78 | SAVE_ITEM(S5P_EINT_FLTCON(2)), | |
79 | SAVE_ITEM(S5P_EINT_FLTCON(3)), | |
80 | SAVE_ITEM(S5P_EINT_FLTCON(4)), | |
81 | SAVE_ITEM(S5P_EINT_FLTCON(5)), | |
82 | SAVE_ITEM(S5P_EINT_FLTCON(6)), | |
83 | SAVE_ITEM(S5P_EINT_FLTCON(7)), | |
84 | ||
85 | SAVE_ITEM(S5P_EINT_MASK(0)), | |
86 | SAVE_ITEM(S5P_EINT_MASK(1)), | |
87 | SAVE_ITEM(S5P_EINT_MASK(2)), | |
88 | SAVE_ITEM(S5P_EINT_MASK(3)), | |
89 | }; | |
90 | ||
bb072c3c | 91 | int s3c24xx_irq_suspend(void) |
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92 | { |
93 | s3c_pm_do_save(eint_save, ARRAY_SIZE(eint_save)); | |
94 | ||
95 | return 0; | |
96 | } | |
97 | ||
bb072c3c | 98 | void s3c24xx_irq_resume(void) |
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99 | { |
100 | s3c_pm_do_restore(eint_save, ARRAY_SIZE(eint_save)); | |
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101 | } |
102 |