projects / deliverable / linux.git / blame
| Commit | Line | Data |
|---|---|---|
| 8eadcf74 | 1 | /* |
| ea31fd43 JL |
2 | * Copyright (c) 2010 Samsung Electronics Co., Ltd. |
| 3 | * http://www.samsung.com | |
| 4 | * | |
| 5 | * Based on arch/arm/plat-s3c24xx/irq-pm.c, | |
| 6 | * Copyright (c) 2003,2004 Simtec Electronics | |
| 7 | * Ben Dooks <ben@simtec.co.uk> | |
| 8 | * http://armlinux.simtec.co.uk/ | |
| 9 | * | |
| 10 | * This program is free software; you can redistribute it and/or modify | |
| 11 | * it under the terms of the GNU General Public License version 2 as | |
| 12 | * published by the Free Software Foundation. | |
| 13 | */ | |
| 14 | ||
| 15 | #include <linux/init.h> | |
| 16 | #include <linux/module.h> | |
| 17 | #include <linux/interrupt.h> | |
| ea31fd43 JL |
18 | |
| 19 | #include <plat/cpu.h> | |
| 20 | #include <plat/irqs.h> | |
| 21 | #include <plat/pm.h> | |
| 22 | #include <mach/map.h> | |
| 23 | ||
| 24 | #include <mach/regs-gpio.h> | |
| 25 | #include <mach/regs-irq.h> | |
| 26 | ||
| 27 | /* state for IRQs over sleep */ | |
| 28 | ||
| 29 | /* default is to allow for EINT0..EINT31, and IRQ_RTC_TIC, IRQ_RTC_ALARM, | |
| 30 | * as wakeup sources | |
| 31 | * | |
| 32 | * set bit to 1 in allow bitfield to enable the wakeup settings on it | |
| 33 | */ | |
| 34 | ||
| 35 | unsigned long s3c_irqwake_intallow = 0x00000006L; | |
| 36 | unsigned long s3c_irqwake_eintallow = 0xffffffffL; | |
| 37 | ||
| bb0b2374 | 38 | int s3c_irq_wake(struct irq_data *data, unsigned int state) |
| ea31fd43 JL |
39 | { |
| 40 | unsigned long irqbit; | |
| bb19a751 KK |
41 | unsigned int irq_rtc_tic, irq_rtc_alarm; |
| 42 | ||
| bb19a751 KK |
43 | irq_rtc_tic = IRQ_RTC_TIC; |
| 44 | irq_rtc_alarm = IRQ_RTC_ALARM; | |
| bb19a751 KK |
45 | |
| 46 | if (data->irq == irq_rtc_tic || data->irq == irq_rtc_alarm) { | |
| 47 | irqbit = 1 << (data->irq + 1 - irq_rtc_alarm); | |
| ea31fd43 | 48 | |
| ea31fd43 JL |
49 | if (!state) |
| 50 | s3c_irqwake_intmask |= irqbit; | |
| 51 | else | |
| 52 | s3c_irqwake_intmask &= ~irqbit; | |
| bb19a751 | 53 | } else { |
| ea31fd43 JL |
54 | return -ENOENT; |
| 55 | } | |
| bb19a751 | 56 | |
| ea31fd43 JL |
57 | return 0; |
| 58 | } | |
| 59 | ||
| 60 | static struct sleep_save eint_save[] = { | |
| 61 | SAVE_ITEM(S5P_EINT_CON(0)), | |
| 62 | SAVE_ITEM(S5P_EINT_CON(1)), | |
| 63 | SAVE_ITEM(S5P_EINT_CON(2)), | |
| 64 | SAVE_ITEM(S5P_EINT_CON(3)), | |
| 65 | ||
| 66 | SAVE_ITEM(S5P_EINT_FLTCON(0)), | |
| 67 | SAVE_ITEM(S5P_EINT_FLTCON(1)), | |
| 68 | SAVE_ITEM(S5P_EINT_FLTCON(2)), | |
| 69 | SAVE_ITEM(S5P_EINT_FLTCON(3)), | |
| 70 | SAVE_ITEM(S5P_EINT_FLTCON(4)), | |
| 71 | SAVE_ITEM(S5P_EINT_FLTCON(5)), | |
| 72 | SAVE_ITEM(S5P_EINT_FLTCON(6)), | |
| 73 | SAVE_ITEM(S5P_EINT_FLTCON(7)), | |
| 74 | ||
| 75 | SAVE_ITEM(S5P_EINT_MASK(0)), | |
| 76 | SAVE_ITEM(S5P_EINT_MASK(1)), | |
| 77 | SAVE_ITEM(S5P_EINT_MASK(2)), | |
| 78 | SAVE_ITEM(S5P_EINT_MASK(3)), | |
| 79 | }; | |
| 80 | ||
| bb072c3c | 81 | int s3c24xx_irq_suspend(void) |
| ea31fd43 JL |
82 | { |
| 83 | s3c_pm_do_save(eint_save, ARRAY_SIZE(eint_save)); | |
| 84 | ||
| 85 | return 0; | |
| 86 | } | |
| 87 | ||
| bb072c3c | 88 | void s3c24xx_irq_resume(void) |
| ea31fd43 JL |
89 | { |
| 90 | s3c_pm_do_restore(eint_save, ARRAY_SIZE(eint_save)); | |
| ea31fd43 JL |
91 | } |
| 92 |