[deliverable/linux.git] / arch / arm / plat-samsung / time.c

/* linux/arch/arm/plat-samsung/time.c
 *
 * Copyright (C) 2003-2005 Simtec Electronics
 *	Ben Dooks, <ben@simtec.co.uk>
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
 */

#include <linux/kernel.h>
#include <linux/sched.h>
#include <linux/init.h>
#include <linux/interrupt.h>
#include <linux/irq.h>
#include <linux/err.h>
#include <linux/clk.h>
#include <linux/io.h>
#include <linux/platform_device.h>
#include <linux/syscore_ops.h>

#include <asm/mach-types.h>

#include <asm/irq.h>
#include <mach/map.h>
#include <plat/regs-timer.h>
#include <mach/regs-irq.h>
#include <asm/mach/time.h>
#include <mach/tick.h>

#include <plat/clock.h>
#include <plat/cpu.h>

static unsigned long timer_startval;
static unsigned long timer_usec_ticks;

#ifndef TICK_MAX
#define TICK_MAX (0xffff)
#endif

#define TIMER_USEC_SHIFT 16

/* we use the shifted arithmetic to work out the ratio of timer ticks
 * to usecs, as often the peripheral clock is not a nice even multiple
 * of 1MHz.
 *
 * shift of 14 and 15 are too low for the 12MHz, 16 seems to be ok
 * for the current HZ value of 200 without producing overflows.
 *
 * Original patch by Dimitry Andric, updated by Ben Dooks
*/


/* timer_mask_usec_ticks
 *
 * given a clock and divisor, make the value to pass into timer_ticks_to_usec
 * to scale the ticks into usecs
*/

static inline unsigned long
timer_mask_usec_ticks(unsigned long scaler, unsigned long pclk)
{
	unsigned long den = pclk / 1000;

	return ((1000 << TIMER_USEC_SHIFT) * scaler + (den >> 1)) / den;
}

/* timer_ticks_to_usec
 *
 * convert timer ticks to usec.
*/

static inline unsigned long timer_ticks_to_usec(unsigned long ticks)
{
	unsigned long res;

	res = ticks * timer_usec_ticks;
	res += 1 << (TIMER_USEC_SHIFT - 4);	/* round up slightly */

	return res >> TIMER_USEC_SHIFT;
}

/***
 * Returns microsecond  since last clock interrupt.  Note that interrupts
 * will have been disabled by do_gettimeoffset()
 * IRQs are disabled before entering here from do_gettimeofday()
 */

static u32 s3c2410_gettimeoffset(void)
{
	unsigned long tdone;
	unsigned long tval;

	/* work out how many ticks have gone since last timer interrupt */

	tval =  __raw_readl(S3C2410_TCNTO(4));
	tdone = timer_startval - tval;

	/* check to see if there is an interrupt pending */

	if (s3c24xx_ostimer_pending()) {
		/* re-read the timer, and try and fix up for the missed
		 * interrupt. Note, the interrupt may go off before the
		 * timer has re-loaded from wrapping.
		 */

		tval =  __raw_readl(S3C2410_TCNTO(4));
		tdone = timer_startval - tval;

		if (tval != 0)
			tdone += timer_startval;
	}

	return timer_ticks_to_usec(tdone) * 1000;
}


/*
 * IRQ handler for the timer
 */
static irqreturn_t
s3c2410_timer_interrupt(int irq, void *dev_id)
{
	timer_tick();
	return IRQ_HANDLED;
}

static struct irqaction s3c2410_timer_irq = {
	.name		= "S3C2410 Timer Tick",
	.flags		= IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL,
	.handler	= s3c2410_timer_interrupt,
};

#define use_tclk1_12() ( \
	machine_is_bast()	|| \
	machine_is_vr1000()	|| \
	machine_is_anubis()	|| \
	machine_is_osiris())

static struct clk *tin;
static struct clk *tdiv;
static struct clk *timerclk;

/*
 * Set up timer interrupt, and return the current time in seconds.
 *
 * Currently we only use timer4, as it is the only timer which has no
 * other function that can be exploited externally
 */
static void s3c2410_timer_setup (void)
{
	unsigned long tcon;
	unsigned long tcnt;
	unsigned long tcfg1;
	unsigned long tcfg0;

	tcnt = TICK_MAX;  /* default value for tcnt */

	/* configure the system for whichever machine is in use */

	if (use_tclk1_12()) {
		/* timer is at 12MHz, scaler is 1 */
		timer_usec_ticks = timer_mask_usec_ticks(1, 12000000);
		tcnt = 12000000 / HZ;

		tcfg1 = __raw_readl(S3C2410_TCFG1);
		tcfg1 &= ~S3C2410_TCFG1_MUX4_MASK;
		tcfg1 |= S3C2410_TCFG1_MUX4_TCLK1;
		__raw_writel(tcfg1, S3C2410_TCFG1);
	} else {
		unsigned long pclk;
		struct clk *tscaler;

		/* for the h1940 (and others), we use the pclk from the core
		 * to generate the timer values. since values around 50 to
		 * 70MHz are not values we can directly generate the timer
		 * value from, we need to pre-scale and divide before using it.
		 *
		 * for instance, using 50.7MHz and dividing by 6 gives 8.45MHz
		 * (8.45 ticks per usec)
		 */

		pclk = clk_get_rate(timerclk);

		/* configure clock tick */

		timer_usec_ticks = timer_mask_usec_ticks(6, pclk);

		tscaler = clk_get_parent(tdiv);

		clk_set_rate(tscaler, pclk / 3);
		clk_set_rate(tdiv, pclk / 6);
		clk_set_parent(tin, tdiv);

		tcnt = clk_get_rate(tin) / HZ;
	}

	tcon = __raw_readl(S3C2410_TCON);
	tcfg0 = __raw_readl(S3C2410_TCFG0);
	tcfg1 = __raw_readl(S3C2410_TCFG1);

	/* timers reload after counting zero, so reduce the count by 1 */

	tcnt--;

	printk(KERN_DEBUG "timer tcon=%08lx, tcnt %04lx, tcfg %08lx,%08lx, usec %08lx\n",
	       tcon, tcnt, tcfg0, tcfg1, timer_usec_ticks);

	/* check to see if timer is within 16bit range... */
	if (tcnt > TICK_MAX) {
		panic("setup_timer: HZ is too small, cannot configure timer!");
		return;
	}

	__raw_writel(tcfg1, S3C2410_TCFG1);
	__raw_writel(tcfg0, S3C2410_TCFG0);

	timer_startval = tcnt;
	__raw_writel(tcnt, S3C2410_TCNTB(4));

	/* ensure timer is stopped... */

	tcon &= ~(7<<20);
	tcon |= S3C2410_TCON_T4RELOAD;
	tcon |= S3C2410_TCON_T4MANUALUPD;

	__raw_writel(tcon, S3C2410_TCON);
	__raw_writel(tcnt, S3C2410_TCNTB(4));
	__raw_writel(tcnt, S3C2410_TCMPB(4));

	/* start the timer running */
	tcon |= S3C2410_TCON_T4START;
	tcon &= ~S3C2410_TCON_T4MANUALUPD;
	__raw_writel(tcon, S3C2410_TCON);
}

static void __init s3c2410_timer_resources(void)
{
	struct platform_device tmpdev;

	tmpdev.dev.bus = &platform_bus_type;
	tmpdev.id = 4;

	timerclk = clk_get(NULL, "timers");
	if (IS_ERR(timerclk))
		panic("failed to get clock for system timer");

	clk_enable(timerclk);

	if (!use_tclk1_12()) {
		tmpdev.id = 4;
		tmpdev.dev.init_name = "s3c24xx-pwm.4";
		tin = clk_get(&tmpdev.dev, "pwm-tin");
		if (IS_ERR(tin))
			panic("failed to get pwm-tin clock for system timer");

		tdiv = clk_get(&tmpdev.dev, "pwm-tdiv");
		if (IS_ERR(tdiv))
			panic("failed to get pwm-tdiv clock for system timer");
	}

	clk_enable(tin);
}

static struct syscore_ops s3c24xx_syscore_ops = {
	.resume		= s3c2410_timer_setup,
};

void __init s3c24xx_timer_init(void)
{
	arch_gettimeoffset = s3c2410_gettimeoffset;

	s3c2410_timer_resources();
	s3c2410_timer_setup();
	setup_irq(IRQ_TIMER4, &s3c2410_timer_irq);
	register_syscore_ops(&s3c24xx_syscore_ops);
}
Commit	Line	Data
6c6971dc	1	/* linux/arch/arm/plat-samsung/time.c
1da177e4 LT	2	*
	3	* Copyright (C) 2003-2005 Simtec Electronics
	4	* Ben Dooks, <ben@simtec.co.uk>
	5	*
	6	* This program is free software; you can redistribute it and/or modify
	7	* it under the terms of the GNU General Public License as published by
	8	* the Free Software Foundation; either version 2 of the License, or
	9	* (at your option) any later version.
	10	*
	11	* This program is distributed in the hope that it will be useful,
	12	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	13	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	14	* GNU General Public License for more details.
	15	*
	16	* You should have received a copy of the GNU General Public License
	17	* along with this program; if not, write to the Free Software
	18	* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
	19	*/
	20
1da177e4 LT	21	#include <linux/kernel.h>
	22	#include <linux/sched.h>
	23	#include <linux/init.h>
	24	#include <linux/interrupt.h>
544b46de	25	#include <linux/irq.h>
1da177e4	26	#include <linux/err.h>
f8ce2547	27	#include <linux/clk.h>
fced80c7	28	#include <linux/io.h>
9d325f23	29	#include <linux/platform_device.h>
656c669b	30	#include <linux/syscore_ops.h>
1da177e4	31
1da177e4 LT	32	#include <asm/mach-types.h>
1da177e4 LT	33
1da177e4	34	#include <asm/irq.h>
a09e64fb	35	#include <mach/map.h>
a2b7ba9c	36	#include <plat/regs-timer.h>
a09e64fb	37	#include <mach/regs-irq.h>
1da177e4	38	#include <asm/mach/time.h>
9bc1aaea	39	#include <mach/tick.h>
1da177e4	40
d5120ae7	41	#include <plat/clock.h>
a2b7ba9c	42	#include <plat/cpu.h>
1da177e4 LT	43
	44	static unsigned long timer_startval;
	45	static unsigned long timer_usec_ticks;
	46
c652d2dd BD	47	#ifndef TICK_MAX
	48	#define TICK_MAX (0xffff)
	49	#endif
	50
1da177e4 LT	51	#define TIMER_USEC_SHIFT 16
	52
	53	/* we use the shifted arithmetic to work out the ratio of timer ticks
	54	* to usecs, as often the peripheral clock is not a nice even multiple
	55	* of 1MHz.
	56	*
	57	* shift of 14 and 15 are too low for the 12MHz, 16 seems to be ok
	58	* for the current HZ value of 200 without producing overflows.
	59	*
	60	* Original patch by Dimitry Andric, updated by Ben Dooks
	61	*/
	62
	63
	64	/* timer_mask_usec_ticks
	65	*
	66	* given a clock and divisor, make the value to pass into timer_ticks_to_usec
	67	* to scale the ticks into usecs
	68	*/
	69
	70	static inline unsigned long
	71	timer_mask_usec_ticks(unsigned long scaler, unsigned long pclk)
	72	{
	73	unsigned long den = pclk / 1000;
	74
	75	return ((1000 << TIMER_USEC_SHIFT) * scaler + (den >> 1)) / den;
	76	}
	77
	78	/* timer_ticks_to_usec
	79	*
	80	* convert timer ticks to usec.
	81	*/
	82
	83	static inline unsigned long timer_ticks_to_usec(unsigned long ticks)
	84	{
	85	unsigned long res;
	86
	87	res = ticks * timer_usec_ticks;
	88	res += 1 << (TIMER_USEC_SHIFT - 4); /* round up slightly */
	89
	90	return res >> TIMER_USEC_SHIFT;
	91	}
	92
	93	/***
	94	* Returns microsecond since last clock interrupt. Note that interrupts
	95	* will have been disabled by do_gettimeoffset()
	96	* IRQs are disabled before entering here from do_gettimeofday()
	97	*/
	98
23c197b7	99	static u32 s3c2410_gettimeoffset(void)
1da177e4 LT	100	{
1da177e4 LT	101	unsigned long tdone;
1da177e4 LT	102	unsigned long tval;
	103
	104	/* work out how many ticks have gone since last timer interrupt */
	105
b915a125	106	tval = __raw_readl(S3C2410_TCNTO(4));
1da177e4 LT	107	tdone = timer_startval - tval;
	108
	109	/* check to see if there is an interrupt pending */
	110
9bc1aaea	111	if (s3c24xx_ostimer_pending()) {
1da177e4 LT	112	/* re-read the timer, and try and fix up for the missed
	113	* interrupt. Note, the interrupt may go off before the
	114	* timer has re-loaded from wrapping.
	115	*/
	116
	117	tval = __raw_readl(S3C2410_TCNTO(4));
	118	tdone = timer_startval - tval;
	119
	120	if (tval != 0)
	121	tdone += timer_startval;
	122	}
	123
23c197b7	124	return timer_ticks_to_usec(tdone) * 1000;
1da177e4 LT	125	}
	126
	127
	128	/*
	129	* IRQ handler for the timer
	130	*/
	131	static irqreturn_t
0cd61b68	132	s3c2410_timer_interrupt(int irq, void *dev_id)
1da177e4	133	{
0cd61b68	134	timer_tick();
1da177e4 LT	135	return IRQ_HANDLED;
	136	}
	137
	138	static struct irqaction s3c2410_timer_irq = {
	139	.name = "S3C2410 Timer Tick",
b30fabad	140	.flags = IRQF_DISABLED \| IRQF_TIMER \| IRQF_IRQPOLL,
09b8b5f8	141	.handler = s3c2410_timer_interrupt,
1da177e4 LT	142	};
1da177e4 LT	143
766636cc BD	144	#define use_tclk1_12() ( \
	145	machine_is_bast() \|\| \
	146	machine_is_vr1000() \|\| \
	147	machine_is_anubis() \|\| \
b915a125	148	machine_is_osiris())
766636cc	149
9d325f23 BD	150	static struct clk *tin;
	151	static struct clk *tdiv;
	152	static struct clk *timerclk;
	153
1da177e4 LT	154	/*
	155	* Set up timer interrupt, and return the current time in seconds.
	156	*
	157	* Currently we only use timer4, as it is the only timer which has no
	158	* other function that can be exploited externally
	159	*/
	160	static void s3c2410_timer_setup (void)
	161	{
	162	unsigned long tcon;
	163	unsigned long tcnt;
	164	unsigned long tcfg1;
	165	unsigned long tcfg0;
	166
c652d2dd	167	tcnt = TICK_MAX; /* default value for tcnt */
1da177e4	168
1da177e4 LT	169	/* configure the system for whichever machine is in use */
1da177e4 LT	170
766636cc	171	if (use_tclk1_12()) {
1da177e4 LT	172	/* timer is at 12MHz, scaler is 1 */
	173	timer_usec_ticks = timer_mask_usec_ticks(1, 12000000);
	174	tcnt = 12000000 / HZ;
	175
9d325f23	176	tcfg1 = __raw_readl(S3C2410_TCFG1);
1da177e4 LT	177	tcfg1 &= ~S3C2410_TCFG1_MUX4_MASK;
1da177e4 LT	178	tcfg1 \|= S3C2410_TCFG1_MUX4_TCLK1;
9d325f23	179	__raw_writel(tcfg1, S3C2410_TCFG1);
1da177e4 LT	180	} else {
1da177e4 LT	181	unsigned long pclk;
9d325f23	182	struct clk *tscaler;
1da177e4 LT	183
	184	/* for the h1940 (and others), we use the pclk from the core
	185	* to generate the timer values. since values around 50 to
	186	* 70MHz are not values we can directly generate the timer
	187	* value from, we need to pre-scale and divide before using it.
	188	*
	189	* for instance, using 50.7MHz and dividing by 6 gives 8.45MHz
	190	* (8.45 ticks per usec)
	191	*/
	192
9d325f23	193	pclk = clk_get_rate(timerclk);
1da177e4 LT	194
	195	/* configure clock tick */
	196
	197	timer_usec_ticks = timer_mask_usec_ticks(6, pclk);
	198
9d325f23	199	tscaler = clk_get_parent(tdiv);
1da177e4	200
9d325f23 BD	201	clk_set_rate(tscaler, pclk / 3);
	202	clk_set_rate(tdiv, pclk / 6);
	203	clk_set_parent(tin, tdiv);
1da177e4	204
9d325f23	205	tcnt = clk_get_rate(tin) / HZ;
1da177e4 LT	206	}
1da177e4 LT	207
9d325f23 BD	208	tcon = __raw_readl(S3C2410_TCON);
	209	tcfg0 = __raw_readl(S3C2410_TCFG0);
	210	tcfg1 = __raw_readl(S3C2410_TCFG1);
	211
1da177e4 LT	212	/* timers reload after counting zero, so reduce the count by 1 */
	213
	214	tcnt--;
	215
b915a125	216	printk(KERN_DEBUG "timer tcon=%08lx, tcnt %04lx, tcfg %08lx,%08lx, usec %08lx\n",
1da177e4 LT	217	tcon, tcnt, tcfg0, tcfg1, timer_usec_ticks);
	218
	219	/* check to see if timer is within 16bit range... */
c652d2dd	220	if (tcnt > TICK_MAX) {
1da177e4 LT	221	panic("setup_timer: HZ is too small, cannot configure timer!");
	222	return;
	223	}
	224
	225	__raw_writel(tcfg1, S3C2410_TCFG1);
	226	__raw_writel(tcfg0, S3C2410_TCFG0);
	227
	228	timer_startval = tcnt;
	229	__raw_writel(tcnt, S3C2410_TCNTB(4));
	230
	231	/* ensure timer is stopped... */
	232
	233	tcon &= ~(7<<20);
	234	tcon \|= S3C2410_TCON_T4RELOAD;
	235	tcon \|= S3C2410_TCON_T4MANUALUPD;
	236
	237	__raw_writel(tcon, S3C2410_TCON);
	238	__raw_writel(tcnt, S3C2410_TCNTB(4));
	239	__raw_writel(tcnt, S3C2410_TCMPB(4));
	240
	241	/* start the timer running */
	242	tcon \|= S3C2410_TCON_T4START;
	243	tcon &= ~S3C2410_TCON_T4MANUALUPD;
	244	__raw_writel(tcon, S3C2410_TCON);
	245	}
	246
9d325f23 BD	247	static void __init s3c2410_timer_resources(void)
	248	{
	249	struct platform_device tmpdev;
	250
	251	tmpdev.dev.bus = &platform_bus_type;
	252	tmpdev.id = 4;
	253
	254	timerclk = clk_get(NULL, "timers");
	255	if (IS_ERR(timerclk))
	256	panic("failed to get clock for system timer");
	257
	258	clk_enable(timerclk);
	259
	260	if (!use_tclk1_12()) {
e83626f2 TA	261	tmpdev.id = 4;
e83626f2 TA	262	tmpdev.dev.init_name = "s3c24xx-pwm.4";
9d325f23 BD	263	tin = clk_get(&tmpdev.dev, "pwm-tin");
	264	if (IS_ERR(tin))
	265	panic("failed to get pwm-tin clock for system timer");
	266
	267	tdiv = clk_get(&tmpdev.dev, "pwm-tdiv");
	268	if (IS_ERR(tdiv))
	269	panic("failed to get pwm-tdiv clock for system timer");
	270	}
	271
	272	clk_enable(tin);
	273	}
	274
656c669b SW	275	static struct syscore_ops s3c24xx_syscore_ops = {
	276	.resume = s3c2410_timer_setup,
	277	};
	278
6bb27d73	279	void __init s3c24xx_timer_init(void)
1da177e4	280	{
23c197b7 SW	281	arch_gettimeoffset = s3c2410_gettimeoffset;
23c197b7 SW	282
9d325f23	283	s3c2410_timer_resources();
1da177e4 LT	284	s3c2410_timer_setup();
1da177e4 LT	285	setup_irq(IRQ_TIMER4, &s3c2410_timer_irq);
656c669b	286	register_syscore_ops(&s3c24xx_syscore_ops);
1da177e4	287	}