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0462b447 RK |
1 | /* |
2 | * linux/arch/arm/plat-versatile/platsmp.c | |
3 | * | |
4 | * Copyright (C) 2002 ARM Ltd. | |
5 | * All Rights Reserved | |
6 | * | |
7 | * This program is free software; you can redistribute it and/or modify | |
8 | * it under the terms of the GNU General Public License version 2 as | |
9 | * published by the Free Software Foundation. | |
10 | */ | |
11 | #include <linux/init.h> | |
12 | #include <linux/errno.h> | |
13 | #include <linux/delay.h> | |
14 | #include <linux/device.h> | |
15 | #include <linux/jiffies.h> | |
16 | #include <linux/smp.h> | |
17 | ||
18 | #include <asm/cacheflush.h> | |
19 | ||
20 | /* | |
21 | * control for which core is the next to come out of the secondary | |
22 | * boot "holding pen" | |
23 | */ | |
24 | volatile int __cpuinitdata pen_release = -1; | |
25 | ||
26 | /* | |
27 | * Write pen_release in a way that is guaranteed to be visible to all | |
28 | * observers, irrespective of whether they're taking part in coherency | |
29 | * or not. This is necessary for the hotplug code to work reliably. | |
30 | */ | |
31 | static void __cpuinit write_pen_release(int val) | |
32 | { | |
33 | pen_release = val; | |
34 | smp_wmb(); | |
35 | __cpuc_flush_dcache_area((void *)&pen_release, sizeof(pen_release)); | |
36 | outer_clean_range(__pa(&pen_release), __pa(&pen_release + 1)); | |
37 | } | |
38 | ||
39 | static DEFINE_SPINLOCK(boot_lock); | |
40 | ||
41 | void __cpuinit platform_secondary_init(unsigned int cpu) | |
42 | { | |
43 | /* | |
44 | * if any interrupts are already enabled for the primary | |
45 | * core (e.g. timer irq), then they will not have been enabled | |
46 | * for us: do so | |
47 | */ | |
48 | gic_secondary_init(0); | |
49 | ||
50 | /* | |
51 | * let the primary processor know we're out of the | |
52 | * pen, then head off into the C entry point | |
53 | */ | |
54 | write_pen_release(-1); | |
55 | ||
56 | /* | |
57 | * Synchronise with the boot thread. | |
58 | */ | |
59 | spin_lock(&boot_lock); | |
60 | spin_unlock(&boot_lock); | |
61 | } | |
62 | ||
63 | int __cpuinit boot_secondary(unsigned int cpu, struct task_struct *idle) | |
64 | { | |
65 | unsigned long timeout; | |
66 | ||
67 | /* | |
68 | * Set synchronisation state between this boot processor | |
69 | * and the secondary one | |
70 | */ | |
71 | spin_lock(&boot_lock); | |
72 | ||
73 | /* | |
74 | * This is really belt and braces; we hold unintended secondary | |
75 | * CPUs in the holding pen until we're ready for them. However, | |
76 | * since we haven't sent them a soft interrupt, they shouldn't | |
77 | * be there. | |
78 | */ | |
79 | write_pen_release(cpu); | |
80 | ||
81 | /* | |
82 | * Send the secondary CPU a soft interrupt, thereby causing | |
83 | * the boot monitor to read the system wide flags register, | |
84 | * and branch to the address found there. | |
85 | */ | |
86 | smp_cross_call(cpumask_of(cpu), 1); | |
87 | ||
88 | timeout = jiffies + (1 * HZ); | |
89 | while (time_before(jiffies, timeout)) { | |
90 | smp_rmb(); | |
91 | if (pen_release == -1) | |
92 | break; | |
93 | ||
94 | udelay(10); | |
95 | } | |
96 | ||
97 | /* | |
98 | * now the secondary core is starting up let it run its | |
99 | * calibrations, then wait for it to finish | |
100 | */ | |
101 | spin_unlock(&boot_lock); | |
102 | ||
103 | return pen_release != -1 ? -ENOSYS : 0; | |
104 | } |