[deliverable/linux.git] / arch / arm / vfp / vfphw.S

/*
 *  linux/arch/arm/vfp/vfphw.S
 *
 *  Copyright (C) 2004 ARM Limited.
 *  Written by Deep Blue Solutions Limited.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 *
 * This code is called from the kernel's undefined instruction trap.
 * r9 holds the return address for successful handling.
 * lr holds the return address for unrecognised instructions.
 * r10 points at the start of the private FP workspace in the thread structure
 * sp points to a struct pt_regs (as defined in include/asm/proc/ptrace.h)
 */
#include <linux/init.h>
#include <linux/linkage.h>
#include <asm/thread_info.h>
#include <asm/vfpmacros.h>
#include <linux/kern_levels.h>
#include <asm/assembler.h>
#include <asm/asm-offsets.h>

	.macro	DBGSTR, str
#ifdef DEBUG
	stmfd	sp!, {r0-r3, ip, lr}
	ldr	r0, =1f
	bl	printk
	ldmfd	sp!, {r0-r3, ip, lr}

	.pushsection .rodata, "a"
1:	.ascii	KERN_DEBUG "VFP: \str\n"
	.byte	0
	.previous
#endif
	.endm

	.macro  DBGSTR1, str, arg
#ifdef DEBUG
	stmfd	sp!, {r0-r3, ip, lr}
	mov	r1, \arg
	ldr	r0, =1f
	bl	printk
	ldmfd	sp!, {r0-r3, ip, lr}

	.pushsection .rodata, "a"
1:	.ascii	KERN_DEBUG "VFP: \str\n"
	.byte	0
	.previous
#endif
	.endm

	.macro  DBGSTR3, str, arg1, arg2, arg3
#ifdef DEBUG
	stmfd	sp!, {r0-r3, ip, lr}
	mov	r3, \arg3
	mov	r2, \arg2
	mov	r1, \arg1
	ldr	r0, =1f
	bl	printk
	ldmfd	sp!, {r0-r3, ip, lr}

	.pushsection .rodata, "a"
1:	.ascii	KERN_DEBUG "VFP: \str\n"
	.byte	0
	.previous
#endif
	.endm


@ VFP hardware support entry point.
@
@  r0  = instruction opcode (32-bit ARM or two 16-bit Thumb)
@  r2  = PC value to resume execution after successful emulation
@  r9  = normal "successful" return address
@  r10 = vfp_state union
@  r11 = CPU number
@  lr  = unrecognised instruction return address
@  IRQs enabled.
ENTRY(vfp_support_entry)
	DBGSTR3	"instr %08x pc %08x state %p", r0, r2, r10

	ldr	r3, [sp, #S_PSR]	@ Neither lazy restore nor FP exceptions
	and	r3, r3, #MODE_MASK	@ are supported in kernel mode
	teq	r3, #USR_MODE
	bne	vfp_kmode_exception	@ Returns through lr

	VFPFMRX	r1, FPEXC		@ Is the VFP enabled?
	DBGSTR1	"fpexc %08x", r1
	tst	r1, #FPEXC_EN
	bne	look_for_VFP_exceptions	@ VFP is already enabled

	DBGSTR1 "enable %x", r10
	ldr	r3, vfp_current_hw_state_address
	orr	r1, r1, #FPEXC_EN	@ user FPEXC has the enable bit set
	ldr	r4, [r3, r11, lsl #2]	@ vfp_current_hw_state pointer
	bic	r5, r1, #FPEXC_EX	@ make sure exceptions are disabled
	cmp	r4, r10			@ this thread owns the hw context?
#ifndef CONFIG_SMP
	@ For UP, checking that this thread owns the hw context is
	@ sufficient to determine that the hardware state is valid.
	beq	vfp_hw_state_valid

	@ On UP, we lazily save the VFP context.  As a different
	@ thread wants ownership of the VFP hardware, save the old
	@ state if there was a previous (valid) owner.

	VFPFMXR	FPEXC, r5		@ enable VFP, disable any pending
					@ exceptions, so we can get at the
					@ rest of it

	DBGSTR1	"save old state %p", r4
	cmp	r4, #0			@ if the vfp_current_hw_state is NULL
	beq	vfp_reload_hw		@ then the hw state needs reloading
	VFPFSTMIA r4, r5		@ save the working registers
	VFPFMRX	r5, FPSCR		@ current status
#ifndef CONFIG_CPU_FEROCEON
	tst	r1, #FPEXC_EX		@ is there additional state to save?
	beq	1f
	VFPFMRX	r6, FPINST		@ FPINST (only if FPEXC.EX is set)
	tst	r1, #FPEXC_FP2V		@ is there an FPINST2 to read?
	beq	1f
	VFPFMRX	r8, FPINST2		@ FPINST2 if needed (and present)
1:
#endif
	stmia	r4, {r1, r5, r6, r8}	@ save FPEXC, FPSCR, FPINST, FPINST2
vfp_reload_hw:

#else
	@ For SMP, if this thread does not own the hw context, then we
	@ need to reload it.  No need to save the old state as on SMP,
	@ we always save the state when we switch away from a thread.
	bne	vfp_reload_hw

	@ This thread has ownership of the current hardware context.
	@ However, it may have been migrated to another CPU, in which
	@ case the saved state is newer than the hardware context.
	@ Check this by looking at the CPU number which the state was
	@ last loaded onto.
	ldr	ip, [r10, #VFP_CPU]
	teq	ip, r11
	beq	vfp_hw_state_valid

vfp_reload_hw:
	@ We're loading this threads state into the VFP hardware. Update
	@ the CPU number which contains the most up to date VFP context.
	str	r11, [r10, #VFP_CPU]

	VFPFMXR	FPEXC, r5		@ enable VFP, disable any pending
					@ exceptions, so we can get at the
					@ rest of it
#endif

	DBGSTR1	"load state %p", r10
	str	r10, [r3, r11, lsl #2]	@ update the vfp_current_hw_state pointer
					@ Load the saved state back into the VFP
	VFPFLDMIA r10, r5		@ reload the working registers while
					@ FPEXC is in a safe state
	ldmia	r10, {r1, r5, r6, r8}	@ load FPEXC, FPSCR, FPINST, FPINST2
#ifndef CONFIG_CPU_FEROCEON
	tst	r1, #FPEXC_EX		@ is there additional state to restore?
	beq	1f
	VFPFMXR	FPINST, r6		@ restore FPINST (only if FPEXC.EX is set)
	tst	r1, #FPEXC_FP2V		@ is there an FPINST2 to write?
	beq	1f
	VFPFMXR	FPINST2, r8		@ FPINST2 if needed (and present)
1:
#endif
	VFPFMXR	FPSCR, r5		@ restore status

@ The context stored in the VFP hardware is up to date with this thread
vfp_hw_state_valid:
	tst	r1, #FPEXC_EX
	bne	process_exception	@ might as well handle the pending
					@ exception before retrying branch
					@ out before setting an FPEXC that
					@ stops us reading stuff
	VFPFMXR	FPEXC, r1		@ Restore FPEXC last
	sub	r2, r2, #4		@ Retry current instruction - if Thumb
	str	r2, [sp, #S_PC]		@ mode it's two 16-bit instructions,
					@ else it's one 32-bit instruction, so
					@ always subtract 4 from the following
					@ instruction address.
	dec_preempt_count_ti r10, r4
	mov	pc, r9			@ we think we have handled things


look_for_VFP_exceptions:
	@ Check for synchronous or asynchronous exception
	tst	r1, #FPEXC_EX | FPEXC_DEX
	bne	process_exception
	@ On some implementations of the VFP subarch 1, setting FPSCR.IXE
	@ causes all the CDP instructions to be bounced synchronously without
	@ setting the FPEXC.EX bit
	VFPFMRX	r5, FPSCR
	tst	r5, #FPSCR_IXE
	bne	process_exception

	@ Fall into hand on to next handler - appropriate coproc instr
	@ not recognised by VFP

	DBGSTR	"not VFP"
	dec_preempt_count_ti r10, r4
	mov	pc, lr

process_exception:
	DBGSTR	"bounce"
	mov	r2, sp			@ nothing stacked - regdump is at TOS
	mov	lr, r9			@ setup for a return to the user code.

	@ Now call the C code to package up the bounce to the support code
	@   r0 holds the trigger instruction
	@   r1 holds the FPEXC value
	@   r2 pointer to register dump
	b	VFP_bounce		@ we have handled this - the support
					@ code will raise an exception if
					@ required. If not, the user code will
					@ retry the faulted instruction
ENDPROC(vfp_support_entry)

ENTRY(vfp_save_state)
	@ Save the current VFP state
	@ r0 - save location
	@ r1 - FPEXC
	DBGSTR1	"save VFP state %p", r0
	VFPFSTMIA r0, r2		@ save the working registers
	VFPFMRX	r2, FPSCR		@ current status
	tst	r1, #FPEXC_EX		@ is there additional state to save?
	beq	1f
	VFPFMRX	r3, FPINST		@ FPINST (only if FPEXC.EX is set)
	tst	r1, #FPEXC_FP2V		@ is there an FPINST2 to read?
	beq	1f
	VFPFMRX	r12, FPINST2		@ FPINST2 if needed (and present)
1:
	stmia	r0, {r1, r2, r3, r12}	@ save FPEXC, FPSCR, FPINST, FPINST2
	mov	pc, lr
ENDPROC(vfp_save_state)

	.align
vfp_current_hw_state_address:
	.word	vfp_current_hw_state

	.macro	tbl_branch, base, tmp, shift
#ifdef CONFIG_THUMB2_KERNEL
	adr	\tmp, 1f
	add	\tmp, \tmp, \base, lsl \shift
	mov	pc, \tmp
#else
	add	pc, pc, \base, lsl \shift
	mov	r0, r0
#endif
1:
	.endm

ENTRY(vfp_get_float)
	tbl_branch r0, r3, #3
	.irp	dr,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15
1:	mrc	p10, 0, r0, c\dr, c0, 0	@ fmrs	r0, s0
	mov	pc, lr
	.org	1b + 8
1:	mrc	p10, 0, r0, c\dr, c0, 4	@ fmrs	r0, s1
	mov	pc, lr
	.org	1b + 8
	.endr
ENDPROC(vfp_get_float)

ENTRY(vfp_put_float)
	tbl_branch r1, r3, #3
	.irp	dr,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15
1:	mcr	p10, 0, r0, c\dr, c0, 0	@ fmsr	r0, s0
	mov	pc, lr
	.org	1b + 8
1:	mcr	p10, 0, r0, c\dr, c0, 4	@ fmsr	r0, s1
	mov	pc, lr
	.org	1b + 8
	.endr
ENDPROC(vfp_put_float)

ENTRY(vfp_get_double)
	tbl_branch r0, r3, #3
	.irp	dr,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15
1:	fmrrd	r0, r1, d\dr
	mov	pc, lr
	.org	1b + 8
	.endr
#ifdef CONFIG_VFPv3
	@ d16 - d31 registers
	.irp	dr,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15
1:	mrrc	p11, 3, r0, r1, c\dr	@ fmrrd	r0, r1, d\dr
	mov	pc, lr
	.org	1b + 8
	.endr
#endif

	@ virtual register 16 (or 32 if VFPv3) for compare with zero
	mov	r0, #0
	mov	r1, #0
	mov	pc, lr
ENDPROC(vfp_get_double)

ENTRY(vfp_put_double)
	tbl_branch r2, r3, #3
	.irp	dr,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15
1:	fmdrr	d\dr, r0, r1
	mov	pc, lr
	.org	1b + 8
	.endr
#ifdef CONFIG_VFPv3
	@ d16 - d31 registers
	.irp	dr,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15
1:	mcrr	p11, 3, r0, r1, c\dr	@ fmdrr	r0, r1, d\dr
	mov	pc, lr
	.org	1b + 8
	.endr
#endif
ENDPROC(vfp_put_double)
Commit	Line	Data
1da177e4 LT	1	/*
	2	* linux/arch/arm/vfp/vfphw.S
	3	*
	4	* Copyright (C) 2004 ARM Limited.
	5	* Written by Deep Blue Solutions Limited.
	6	*
	7	* This program is free software; you can redistribute it and/or modify
	8	* it under the terms of the GNU General Public License version 2 as
	9	* published by the Free Software Foundation.
	10	*
	11	* This code is called from the kernel's undefined instruction trap.
	12	* r9 holds the return address for successful handling.
	13	* lr holds the return address for unrecognised instructions.
	14	* r10 points at the start of the private FP workspace in the thread structure
	15	* sp points to a struct pt_regs (as defined in include/asm/proc/ptrace.h)
	16	*/
39ad04cc CM	17	#include <linux/init.h>
39ad04cc CM	18	#include <linux/linkage.h>
1da177e4 LT	19	#include <asm/thread_info.h>
1da177e4 LT	20	#include <asm/vfpmacros.h>
0cc41e4a	21	#include <linux/kern_levels.h>
39ad04cc CM	22	#include <asm/assembler.h>
39ad04cc CM	23	#include <asm/asm-offsets.h>
1da177e4 LT	24
	25	.macro DBGSTR, str
	26	#ifdef DEBUG
	27	stmfd sp!, {r0-r3, ip, lr}
ded3ef0f	28	ldr r0, =1f
1da177e4	29	bl printk
ded3ef0f RK	30	ldmfd sp!, {r0-r3, ip, lr}
	31
	32	.pushsection .rodata, "a"
	33	1: .ascii KERN_DEBUG "VFP: \str\n"
	34	.byte 0
	35	.previous
1da177e4 LT	36	#endif
	37	.endm
	38
	39	.macro DBGSTR1, str, arg
	40	#ifdef DEBUG
	41	stmfd sp!, {r0-r3, ip, lr}
	42	mov r1, \arg
ded3ef0f	43	ldr r0, =1f
1da177e4	44	bl printk
ded3ef0f RK	45	ldmfd sp!, {r0-r3, ip, lr}
	46
	47	.pushsection .rodata, "a"
	48	1: .ascii KERN_DEBUG "VFP: \str\n"
	49	.byte 0
	50	.previous
1da177e4 LT	51	#endif
	52	.endm
	53
	54	.macro DBGSTR3, str, arg1, arg2, arg3
	55	#ifdef DEBUG
	56	stmfd sp!, {r0-r3, ip, lr}
	57	mov r3, \arg3
	58	mov r2, \arg2
	59	mov r1, \arg1
ded3ef0f	60	ldr r0, =1f
1da177e4	61	bl printk
ded3ef0f RK	62	ldmfd sp!, {r0-r3, ip, lr}
	63
	64	.pushsection .rodata, "a"
	65	1: .ascii KERN_DEBUG "VFP: \str\n"
	66	.byte 0
	67	.previous
1da177e4 LT	68	#endif
	69	.endm
	70
	71
	72	@ VFP hardware support entry point.
	73	@
15ac49b6 RK	74	@ r0 = instruction opcode (32-bit ARM or two 16-bit Thumb)
	75	@ r2 = PC value to resume execution after successful emulation
	76	@ r9 = normal "successful" return address
1da177e4	77	@ r10 = vfp_state union
c6428464	78	@ r11 = CPU number
15ac49b6 RK	79	@ lr = unrecognised instruction return address
15ac49b6 RK	80	@ IRQs enabled.
93ed3970	81	ENTRY(vfp_support_entry)
1da177e4 LT	82	DBGSTR3 "instr %08x pc %08x state %p", r0, r2, r10
1da177e4 LT	83
ab3da156 AB	84	ldr r3, [sp, #S_PSR] @ Neither lazy restore nor FP exceptions
	85	and r3, r3, #MODE_MASK @ are supported in kernel mode
	86	teq r3, #USR_MODE
	87	bne vfp_kmode_exception @ Returns through lr
	88
1da177e4 LT	89	VFPFMRX r1, FPEXC @ Is the VFP enabled?
1da177e4 LT	90	DBGSTR1 "fpexc %08x", r1
228adef1	91	tst r1, #FPEXC_EN
1da177e4 LT	92	bne look_for_VFP_exceptions @ VFP is already enabled
	93
	94	DBGSTR1 "enable %x", r10
af61bdf0	95	ldr r3, vfp_current_hw_state_address
228adef1	96	orr r1, r1, #FPEXC_EN @ user FPEXC has the enable bit set
af61bdf0	97	ldr r4, [r3, r11, lsl #2] @ vfp_current_hw_state pointer
228adef1	98	bic r5, r1, #FPEXC_EX @ make sure exceptions are disabled
08409c33	99	cmp r4, r10 @ this thread owns the hw context?
f8f2a852 RK	100	#ifndef CONFIG_SMP
	101	@ For UP, checking that this thread owns the hw context is
	102	@ sufficient to determine that the hardware state is valid.
08409c33	103	beq vfp_hw_state_valid
1da177e4	104
f8f2a852 RK	105	@ On UP, we lazily save the VFP context. As a different
	106	@ thread wants ownership of the VFP hardware, save the old
	107	@ state if there was a previous (valid) owner.
	108
1da177e4 LT	109	VFPFMXR FPEXC, r5 @ enable VFP, disable any pending
	110	@ exceptions, so we can get at the
	111	@ rest of it
	112
1da177e4	113	DBGSTR1 "save old state %p", r4
f8f2a852 RK	114	cmp r4, #0 @ if the vfp_current_hw_state is NULL
f8f2a852 RK	115	beq vfp_reload_hw @ then the hw state needs reloading
25ebee02	116	VFPFSTMIA r4, r5 @ save the working registers
1da177e4	117	VFPFMRX r5, FPSCR @ current status
85d6943a	118	#ifndef CONFIG_CPU_FEROCEON
c98929c0	119	tst r1, #FPEXC_EX @ is there additional state to save?
24b647a0 CM	120	beq 1f
	121	VFPFMRX r6, FPINST @ FPINST (only if FPEXC.EX is set)
	122	tst r1, #FPEXC_FP2V @ is there an FPINST2 to read?
	123	beq 1f
	124	VFPFMRX r8, FPINST2 @ FPINST2 if needed (and present)
	125	1:
85d6943a	126	#endif
1da177e4	127	stmia r4, {r1, r5, r6, r8} @ save FPEXC, FPSCR, FPINST, FPINST2
f8f2a852 RK	128	vfp_reload_hw:
	129
	130	#else
	131	@ For SMP, if this thread does not own the hw context, then we
	132	@ need to reload it. No need to save the old state as on SMP,
	133	@ we always save the state when we switch away from a thread.
	134	bne vfp_reload_hw
	135
	136	@ This thread has ownership of the current hardware context.
	137	@ However, it may have been migrated to another CPU, in which
	138	@ case the saved state is newer than the hardware context.
	139	@ Check this by looking at the CPU number which the state was
	140	@ last loaded onto.
	141	ldr ip, [r10, #VFP_CPU]
	142	teq ip, r11
	143	beq vfp_hw_state_valid
	144
	145	vfp_reload_hw:
	146	@ We're loading this threads state into the VFP hardware. Update
	147	@ the CPU number which contains the most up to date VFP context.
	148	str r11, [r10, #VFP_CPU]
	149
	150	VFPFMXR FPEXC, r5 @ enable VFP, disable any pending
	151	@ exceptions, so we can get at the
	152	@ rest of it
c6428464	153	#endif
1da177e4	154
1da177e4	155	DBGSTR1 "load state %p", r10
af61bdf0	156	str r10, [r3, r11, lsl #2] @ update the vfp_current_hw_state pointer
1da177e4	157	@ Load the saved state back into the VFP
25ebee02	158	VFPFLDMIA r10, r5 @ reload the working registers while
1da177e4	159	@ FPEXC is in a safe state
80ed3547	160	ldmia r10, {r1, r5, r6, r8} @ load FPEXC, FPSCR, FPINST, FPINST2
85d6943a	161	#ifndef CONFIG_CPU_FEROCEON
c98929c0	162	tst r1, #FPEXC_EX @ is there additional state to restore?
24b647a0 CM	163	beq 1f
	164	VFPFMXR FPINST, r6 @ restore FPINST (only if FPEXC.EX is set)
	165	tst r1, #FPEXC_FP2V @ is there an FPINST2 to write?
	166	beq 1f
	167	VFPFMXR FPINST2, r8 @ FPINST2 if needed (and present)
	168	1:
85d6943a	169	#endif
1da177e4 LT	170	VFPFMXR FPSCR, r5 @ restore status
1da177e4 LT	171
08409c33 RK	172	@ The context stored in the VFP hardware is up to date with this thread
08409c33 RK	173	vfp_hw_state_valid:
228adef1	174	tst r1, #FPEXC_EX
1da177e4 LT	175	bne process_exception @ might as well handle the pending
	176	@ exception before retrying branch
	177	@ out before setting an FPEXC that
	178	@ stops us reading stuff
15ac49b6 RK	179	VFPFMXR FPEXC, r1 @ Restore FPEXC last
	180	sub r2, r2, #4 @ Retry current instruction - if Thumb
	181	str r2, [sp, #S_PC] @ mode it's two 16-bit instructions,
	182	@ else it's one 32-bit instruction, so
	183	@ always subtract 4 from the following
	184	@ instruction address.
0b1f68e8	185	dec_preempt_count_ti r10, r4
1da177e4 LT	186	mov pc, r9 @ we think we have handled things
	187
	188
	189	look_for_VFP_exceptions:
c98929c0 CM	190	@ Check for synchronous or asynchronous exception
c98929c0 CM	191	tst r1, #FPEXC_EX \| FPEXC_DEX
1da177e4	192	bne process_exception
c98929c0 CM	193	@ On some implementations of the VFP subarch 1, setting FPSCR.IXE
	194	@ causes all the CDP instructions to be bounced synchronously without
	195	@ setting the FPEXC.EX bit
1da177e4	196	VFPFMRX r5, FPSCR
c98929c0	197	tst r5, #FPSCR_IXE
1da177e4 LT	198	bne process_exception
	199
	200	@ Fall into hand on to next handler - appropriate coproc instr
	201	@ not recognised by VFP
	202
	203	DBGSTR "not VFP"
0b1f68e8	204	dec_preempt_count_ti r10, r4
1da177e4 LT	205	mov pc, lr
	206
	207	process_exception:
	208	DBGSTR "bounce"
1da177e4 LT	209	mov r2, sp @ nothing stacked - regdump is at TOS
	210	mov lr, r9 @ setup for a return to the user code.
	211
	212	@ Now call the C code to package up the bounce to the support code
	213	@ r0 holds the trigger instruction
	214	@ r1 holds the FPEXC value
	215	@ r2 pointer to register dump
c98929c0	216	b VFP_bounce @ we have handled this - the support
1da177e4 LT	217	@ code will raise an exception if
	218	@ required. If not, the user code will
	219	@ retry the faulted instruction
93ed3970	220	ENDPROC(vfp_support_entry)
1da177e4	221
93ed3970	222	ENTRY(vfp_save_state)
c6428464 CM	223	@ Save the current VFP state
	224	@ r0 - save location
	225	@ r1 - FPEXC
	226	DBGSTR1 "save VFP state %p", r0
25ebee02	227	VFPFSTMIA r0, r2 @ save the working registers
c6428464	228	VFPFMRX r2, FPSCR @ current status
c98929c0	229	tst r1, #FPEXC_EX @ is there additional state to save?
24b647a0 CM	230	beq 1f
	231	VFPFMRX r3, FPINST @ FPINST (only if FPEXC.EX is set)
	232	tst r1, #FPEXC_FP2V @ is there an FPINST2 to read?
	233	beq 1f
	234	VFPFMRX r12, FPINST2 @ FPINST2 if needed (and present)
	235	1:
c6428464 CM	236	stmia r0, {r1, r2, r3, r12} @ save FPEXC, FPSCR, FPINST, FPINST2
c6428464 CM	237	mov pc, lr
93ed3970	238	ENDPROC(vfp_save_state)
c6428464	239
7eb25ebe	240	.align
af61bdf0 RK	241	vfp_current_hw_state_address:
af61bdf0 RK	242	.word vfp_current_hw_state
1da177e4	243
07f33a03 CM	244	.macro tbl_branch, base, tmp, shift
	245	#ifdef CONFIG_THUMB2_KERNEL
	246	adr \tmp, 1f
	247	add \tmp, \tmp, \base, lsl \shift
	248	mov pc, \tmp
	249	#else
	250	add pc, pc, \base, lsl \shift
1da177e4	251	mov r0, r0
07f33a03 CM	252	#endif
	253	1:
	254	.endm
	255
	256	ENTRY(vfp_get_float)
	257	tbl_branch r0, r3, #3
1da177e4	258	.irp dr,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15
07f33a03	259	1: mrc p10, 0, r0, c\dr, c0, 0 @ fmrs r0, s0
1da177e4	260	mov pc, lr
07f33a03 CM	261	.org 1b + 8
07f33a03 CM	262	1: mrc p10, 0, r0, c\dr, c0, 4 @ fmrs r0, s1
1da177e4	263	mov pc, lr
07f33a03	264	.org 1b + 8
1da177e4	265	.endr
93ed3970	266	ENDPROC(vfp_get_float)
1da177e4	267
93ed3970	268	ENTRY(vfp_put_float)
07f33a03	269	tbl_branch r1, r3, #3
1da177e4	270	.irp dr,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15
07f33a03	271	1: mcr p10, 0, r0, c\dr, c0, 0 @ fmsr r0, s0
1da177e4	272	mov pc, lr
07f33a03 CM	273	.org 1b + 8
07f33a03 CM	274	1: mcr p10, 0, r0, c\dr, c0, 4 @ fmsr r0, s1
1da177e4	275	mov pc, lr
07f33a03	276	.org 1b + 8
1da177e4	277	.endr
93ed3970	278	ENDPROC(vfp_put_float)
1da177e4	279
93ed3970	280	ENTRY(vfp_get_double)
07f33a03	281	tbl_branch r0, r3, #3
1da177e4	282	.irp dr,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15
07f33a03	283	1: fmrrd r0, r1, d\dr
1da177e4	284	mov pc, lr
07f33a03	285	.org 1b + 8
1da177e4	286	.endr
25ebee02 CM	287	#ifdef CONFIG_VFPv3
	288	@ d16 - d31 registers
	289	.irp dr,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15
07f33a03	290	1: mrrc p11, 3, r0, r1, c\dr @ fmrrd r0, r1, d\dr
25ebee02	291	mov pc, lr
07f33a03	292	.org 1b + 8
25ebee02 CM	293	.endr
25ebee02 CM	294	#endif
1da177e4	295
25ebee02	296	@ virtual register 16 (or 32 if VFPv3) for compare with zero
1da177e4 LT	297	mov r0, #0
	298	mov r1, #0
	299	mov pc, lr
93ed3970	300	ENDPROC(vfp_get_double)
1da177e4	301
93ed3970	302	ENTRY(vfp_put_double)
07f33a03	303	tbl_branch r2, r3, #3
1da177e4	304	.irp dr,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15
07f33a03	305	1: fmdrr d\dr, r0, r1
1da177e4	306	mov pc, lr
07f33a03	307	.org 1b + 8
1da177e4	308	.endr
25ebee02 CM	309	#ifdef CONFIG_VFPv3
	310	@ d16 - d31 registers
	311	.irp dr,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15
138de1c4	312	1: mcrr p11, 3, r0, r1, c\dr @ fmdrr r0, r1, d\dr
25ebee02	313	mov pc, lr
07f33a03	314	.org 1b + 8
25ebee02 CM	315	.endr
25ebee02 CM	316	#endif
93ed3970	317	ENDPROC(vfp_put_double)