[deliverable/linux.git] / arch / arm / vfp / vfphw.S

/*
 *  linux/arch/arm/vfp/vfphw.S
 *
 *  Copyright (C) 2004 ARM Limited.
 *  Written by Deep Blue Solutions Limited.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 *
 * This code is called from the kernel's undefined instruction trap.
 * r9 holds the return address for successful handling.
 * lr holds the return address for unrecognised instructions.
 * r10 points at the start of the private FP workspace in the thread structure
 * sp points to a struct pt_regs (as defined in include/asm/proc/ptrace.h)
 */
#include <asm/thread_info.h>
#include <asm/vfpmacros.h>
#include "../kernel/entry-header.S"

	.macro	DBGSTR, str
#ifdef DEBUG
	stmfd	sp!, {r0-r3, ip, lr}
	add	r0, pc, #4
	bl	printk
	b	1f
	.asciz  "<7>VFP: \str\n"
	.balign 4
1:	ldmfd	sp!, {r0-r3, ip, lr}
#endif
	.endm

	.macro  DBGSTR1, str, arg
#ifdef DEBUG
	stmfd	sp!, {r0-r3, ip, lr}
	mov	r1, \arg
	add	r0, pc, #4
	bl	printk
	b	1f
	.asciz  "<7>VFP: \str\n"
	.balign 4
1:	ldmfd	sp!, {r0-r3, ip, lr}
#endif
	.endm

	.macro  DBGSTR3, str, arg1, arg2, arg3
#ifdef DEBUG
	stmfd	sp!, {r0-r3, ip, lr}
	mov	r3, \arg3
	mov	r2, \arg2
	mov	r1, \arg1
	add	r0, pc, #4
	bl	printk
	b	1f
	.asciz  "<7>VFP: \str\n"
	.balign 4
1:	ldmfd	sp!, {r0-r3, ip, lr}
#endif
	.endm


@ VFP hardware support entry point.
@
@  r0  = faulted instruction
@  r2  = faulted PC+4
@  r9  = successful return
@  r10 = vfp_state union
@  r11 = CPU number
@  lr  = failure return

ENTRY(vfp_support_entry)
	DBGSTR3	"instr %08x pc %08x state %p", r0, r2, r10

	VFPFMRX	r1, FPEXC		@ Is the VFP enabled?
	DBGSTR1	"fpexc %08x", r1
	tst	r1, #FPEXC_EN
	bne	look_for_VFP_exceptions	@ VFP is already enabled

	DBGSTR1 "enable %x", r10
	ldr	r3, vfp_current_hw_state_address
	orr	r1, r1, #FPEXC_EN	@ user FPEXC has the enable bit set
	ldr	r4, [r3, r11, lsl #2]	@ vfp_current_hw_state pointer
	bic	r5, r1, #FPEXC_EX	@ make sure exceptions are disabled
	cmp	r4, r10			@ this thread owns the hw context?
	beq	vfp_hw_state_valid

	VFPFMXR	FPEXC, r5		@ enable VFP, disable any pending
					@ exceptions, so we can get at the
					@ rest of it

#ifndef CONFIG_SMP
	@ Save out the current registers to the old thread state
	@ No need for SMP since this is not done lazily

	DBGSTR1	"save old state %p", r4
	cmp	r4, #0
	beq	no_old_VFP_process
	VFPFSTMIA r4, r5		@ save the working registers
	VFPFMRX	r5, FPSCR		@ current status
#ifndef CONFIG_CPU_FEROCEON
	tst	r1, #FPEXC_EX		@ is there additional state to save?
	beq	1f
	VFPFMRX	r6, FPINST		@ FPINST (only if FPEXC.EX is set)
	tst	r1, #FPEXC_FP2V		@ is there an FPINST2 to read?
	beq	1f
	VFPFMRX	r8, FPINST2		@ FPINST2 if needed (and present)
1:
#endif
	stmia	r4, {r1, r5, r6, r8}	@ save FPEXC, FPSCR, FPINST, FPINST2
					@ and point r4 at the word at the
					@ start of the register dump
#endif

no_old_VFP_process:
	DBGSTR1	"load state %p", r10
	str	r10, [r3, r11, lsl #2]	@ update the vfp_current_hw_state pointer
					@ Load the saved state back into the VFP
	VFPFLDMIA r10, r5		@ reload the working registers while
					@ FPEXC is in a safe state
	ldmia	r10, {r1, r5, r6, r8}	@ load FPEXC, FPSCR, FPINST, FPINST2
#ifndef CONFIG_CPU_FEROCEON
	tst	r1, #FPEXC_EX		@ is there additional state to restore?
	beq	1f
	VFPFMXR	FPINST, r6		@ restore FPINST (only if FPEXC.EX is set)
	tst	r1, #FPEXC_FP2V		@ is there an FPINST2 to write?
	beq	1f
	VFPFMXR	FPINST2, r8		@ FPINST2 if needed (and present)
1:
#endif
	VFPFMXR	FPSCR, r5		@ restore status

@ The context stored in the VFP hardware is up to date with this thread
vfp_hw_state_valid:
	tst	r1, #FPEXC_EX
	bne	process_exception	@ might as well handle the pending
					@ exception before retrying branch
					@ out before setting an FPEXC that
					@ stops us reading stuff
	VFPFMXR	FPEXC, r1		@ restore FPEXC last
	sub	r2, r2, #4
	str	r2, [sp, #S_PC]		@ retry the instruction
#ifdef CONFIG_PREEMPT
	get_thread_info	r10
	ldr	r4, [r10, #TI_PREEMPT]	@ get preempt count
	sub	r11, r4, #1		@ decrement it
	str	r11, [r10, #TI_PREEMPT]
#endif
	mov	pc, r9			@ we think we have handled things


look_for_VFP_exceptions:
	@ Check for synchronous or asynchronous exception
	tst	r1, #FPEXC_EX | FPEXC_DEX
	bne	process_exception
	@ On some implementations of the VFP subarch 1, setting FPSCR.IXE
	@ causes all the CDP instructions to be bounced synchronously without
	@ setting the FPEXC.EX bit
	VFPFMRX	r5, FPSCR
	tst	r5, #FPSCR_IXE
	bne	process_exception

	@ Fall into hand on to next handler - appropriate coproc instr
	@ not recognised by VFP

	DBGSTR	"not VFP"
#ifdef CONFIG_PREEMPT
	get_thread_info	r10
	ldr	r4, [r10, #TI_PREEMPT]	@ get preempt count
	sub	r11, r4, #1		@ decrement it
	str	r11, [r10, #TI_PREEMPT]
#endif
	mov	pc, lr

process_exception:
	DBGSTR	"bounce"
	mov	r2, sp			@ nothing stacked - regdump is at TOS
	mov	lr, r9			@ setup for a return to the user code.

	@ Now call the C code to package up the bounce to the support code
	@   r0 holds the trigger instruction
	@   r1 holds the FPEXC value
	@   r2 pointer to register dump
	b	VFP_bounce		@ we have handled this - the support
					@ code will raise an exception if
					@ required. If not, the user code will
					@ retry the faulted instruction
ENDPROC(vfp_support_entry)

ENTRY(vfp_save_state)
	@ Save the current VFP state
	@ r0 - save location
	@ r1 - FPEXC
	DBGSTR1	"save VFP state %p", r0
	VFPFSTMIA r0, r2		@ save the working registers
	VFPFMRX	r2, FPSCR		@ current status
	tst	r1, #FPEXC_EX		@ is there additional state to save?
	beq	1f
	VFPFMRX	r3, FPINST		@ FPINST (only if FPEXC.EX is set)
	tst	r1, #FPEXC_FP2V		@ is there an FPINST2 to read?
	beq	1f
	VFPFMRX	r12, FPINST2		@ FPINST2 if needed (and present)
1:
	stmia	r0, {r1, r2, r3, r12}	@ save FPEXC, FPSCR, FPINST, FPINST2
	mov	pc, lr
ENDPROC(vfp_save_state)

	.align
vfp_current_hw_state_address:
	.word	vfp_current_hw_state

	.macro	tbl_branch, base, tmp, shift
#ifdef CONFIG_THUMB2_KERNEL
	adr	\tmp, 1f
	add	\tmp, \tmp, \base, lsl \shift
	mov	pc, \tmp
#else
	add	pc, pc, \base, lsl \shift
	mov	r0, r0
#endif
1:
	.endm

ENTRY(vfp_get_float)
	tbl_branch r0, r3, #3
	.irp	dr,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15
1:	mrc	p10, 0, r0, c\dr, c0, 0	@ fmrs	r0, s0
	mov	pc, lr
	.org	1b + 8
1:	mrc	p10, 0, r0, c\dr, c0, 4	@ fmrs	r0, s1
	mov	pc, lr
	.org	1b + 8
	.endr
ENDPROC(vfp_get_float)

ENTRY(vfp_put_float)
	tbl_branch r1, r3, #3
	.irp	dr,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15
1:	mcr	p10, 0, r0, c\dr, c0, 0	@ fmsr	r0, s0
	mov	pc, lr
	.org	1b + 8
1:	mcr	p10, 0, r0, c\dr, c0, 4	@ fmsr	r0, s1
	mov	pc, lr
	.org	1b + 8
	.endr
ENDPROC(vfp_put_float)

ENTRY(vfp_get_double)
	tbl_branch r0, r3, #3
	.irp	dr,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15
1:	fmrrd	r0, r1, d\dr
	mov	pc, lr
	.org	1b + 8
	.endr
#ifdef CONFIG_VFPv3
	@ d16 - d31 registers
	.irp	dr,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15
1:	mrrc	p11, 3, r0, r1, c\dr	@ fmrrd	r0, r1, d\dr
	mov	pc, lr
	.org	1b + 8
	.endr
#endif

	@ virtual register 16 (or 32 if VFPv3) for compare with zero
	mov	r0, #0
	mov	r1, #0
	mov	pc, lr
ENDPROC(vfp_get_double)

ENTRY(vfp_put_double)
	tbl_branch r2, r3, #3
	.irp	dr,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15
1:	fmdrr	d\dr, r0, r1
	mov	pc, lr
	.org	1b + 8
	.endr
#ifdef CONFIG_VFPv3
	@ d16 - d31 registers
	.irp	dr,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15
1:	mcrr	p11, 3, r0, r1, c\dr	@ fmdrr	r0, r1, d\dr
	mov	pc, lr
	.org	1b + 8
	.endr
#endif
ENDPROC(vfp_put_double)
Commit	Line	Data
1da177e4 LT	1	/*
	2	* linux/arch/arm/vfp/vfphw.S
	3	*
	4	* Copyright (C) 2004 ARM Limited.
	5	* Written by Deep Blue Solutions Limited.
	6	*
	7	* This program is free software; you can redistribute it and/or modify
	8	* it under the terms of the GNU General Public License version 2 as
	9	* published by the Free Software Foundation.
	10	*
	11	* This code is called from the kernel's undefined instruction trap.
	12	* r9 holds the return address for successful handling.
	13	* lr holds the return address for unrecognised instructions.
	14	* r10 points at the start of the private FP workspace in the thread structure
	15	* sp points to a struct pt_regs (as defined in include/asm/proc/ptrace.h)
	16	*/
	17	#include <asm/thread_info.h>
	18	#include <asm/vfpmacros.h>
	19	#include "../kernel/entry-header.S"
	20
	21	.macro DBGSTR, str
	22	#ifdef DEBUG
	23	stmfd sp!, {r0-r3, ip, lr}
	24	add r0, pc, #4
	25	bl printk
	26	b 1f
	27	.asciz "<7>VFP: \str\n"
	28	.balign 4
	29	1: ldmfd sp!, {r0-r3, ip, lr}
	30	#endif
	31	.endm
	32
	33	.macro DBGSTR1, str, arg
	34	#ifdef DEBUG
	35	stmfd sp!, {r0-r3, ip, lr}
	36	mov r1, \arg
	37	add r0, pc, #4
	38	bl printk
	39	b 1f
	40	.asciz "<7>VFP: \str\n"
	41	.balign 4
	42	1: ldmfd sp!, {r0-r3, ip, lr}
	43	#endif
	44	.endm
	45
	46	.macro DBGSTR3, str, arg1, arg2, arg3
	47	#ifdef DEBUG
	48	stmfd sp!, {r0-r3, ip, lr}
	49	mov r3, \arg3
	50	mov r2, \arg2
	51	mov r1, \arg1
	52	add r0, pc, #4
	53	bl printk
	54	b 1f
	55	.asciz "<7>VFP: \str\n"
	56	.balign 4
	57	1: ldmfd sp!, {r0-r3, ip, lr}
	58	#endif
	59	.endm
	60
	61
	62	@ VFP hardware support entry point.
	63	@
	64	@ r0 = faulted instruction
65	@ r2 = faulted PC+4
66	@ r9 = successful return
67	@ r10 = vfp_state union
c6428464	68	@ r11 = CPU number
1da177e4 LT	69	@ lr = failure return
1da177e4 LT	70
93ed3970	71	ENTRY(vfp_support_entry)
1da177e4 LT	72	DBGSTR3 "instr %08x pc %08x state %p", r0, r2, r10
	73
	74	VFPFMRX r1, FPEXC @ Is the VFP enabled?
	75	DBGSTR1 "fpexc %08x", r1
228adef1	76	tst r1, #FPEXC_EN
1da177e4 LT	77	bne look_for_VFP_exceptions @ VFP is already enabled
	78
	79	DBGSTR1 "enable %x", r10
af61bdf0	80	ldr r3, vfp_current_hw_state_address
228adef1	81	orr r1, r1, #FPEXC_EN @ user FPEXC has the enable bit set
af61bdf0	82	ldr r4, [r3, r11, lsl #2] @ vfp_current_hw_state pointer
228adef1	83	bic r5, r1, #FPEXC_EX @ make sure exceptions are disabled
08409c33 RK	84	cmp r4, r10 @ this thread owns the hw context?
08409c33 RK	85	beq vfp_hw_state_valid
1da177e4 LT	86
	87	VFPFMXR FPEXC, r5 @ enable VFP, disable any pending
	88	@ exceptions, so we can get at the
	89	@ rest of it
	90
c6428464	91	#ifndef CONFIG_SMP
1da177e4	92	@ Save out the current registers to the old thread state
c6428464	93	@ No need for SMP since this is not done lazily
1da177e4 LT	94
	95	DBGSTR1 "save old state %p", r4
	96	cmp r4, #0
	97	beq no_old_VFP_process
25ebee02	98	VFPFSTMIA r4, r5 @ save the working registers
1da177e4	99	VFPFMRX r5, FPSCR @ current status
85d6943a	100	#ifndef CONFIG_CPU_FEROCEON
c98929c0	101	tst r1, #FPEXC_EX @ is there additional state to save?
24b647a0 CM	102	beq 1f
	103	VFPFMRX r6, FPINST @ FPINST (only if FPEXC.EX is set)
	104	tst r1, #FPEXC_FP2V @ is there an FPINST2 to read?
	105	beq 1f
	106	VFPFMRX r8, FPINST2 @ FPINST2 if needed (and present)
	107	1:
85d6943a	108	#endif
1da177e4 LT	109	stmia r4, {r1, r5, r6, r8} @ save FPEXC, FPSCR, FPINST, FPINST2
	110	@ and point r4 at the word at the
	111	@ start of the register dump
c6428464	112	#endif
1da177e4 LT	113
	114	no_old_VFP_process:
	115	DBGSTR1 "load state %p", r10
af61bdf0	116	str r10, [r3, r11, lsl #2] @ update the vfp_current_hw_state pointer
1da177e4	117	@ Load the saved state back into the VFP
25ebee02	118	VFPFLDMIA r10, r5 @ reload the working registers while
1da177e4	119	@ FPEXC is in a safe state
80ed3547	120	ldmia r10, {r1, r5, r6, r8} @ load FPEXC, FPSCR, FPINST, FPINST2
85d6943a	121	#ifndef CONFIG_CPU_FEROCEON
c98929c0	122	tst r1, #FPEXC_EX @ is there additional state to restore?
24b647a0 CM	123	beq 1f
	124	VFPFMXR FPINST, r6 @ restore FPINST (only if FPEXC.EX is set)
	125	tst r1, #FPEXC_FP2V @ is there an FPINST2 to write?
	126	beq 1f
	127	VFPFMXR FPINST2, r8 @ FPINST2 if needed (and present)
	128	1:
85d6943a	129	#endif
1da177e4 LT	130	VFPFMXR FPSCR, r5 @ restore status
1da177e4 LT	131
08409c33 RK	132	@ The context stored in the VFP hardware is up to date with this thread
08409c33 RK	133	vfp_hw_state_valid:
228adef1	134	tst r1, #FPEXC_EX
1da177e4 LT	135	bne process_exception @ might as well handle the pending
	136	@ exception before retrying branch
	137	@ out before setting an FPEXC that
	138	@ stops us reading stuff
	139	VFPFMXR FPEXC, r1 @ restore FPEXC last
	140	sub r2, r2, #4
	141	str r2, [sp, #S_PC] @ retry the instruction
f2255be8 GD	142	#ifdef CONFIG_PREEMPT
	143	get_thread_info r10
	144	ldr r4, [r10, #TI_PREEMPT] @ get preempt count
	145	sub r11, r4, #1 @ decrement it
	146	str r11, [r10, #TI_PREEMPT]
	147	#endif
1da177e4 LT	148	mov pc, r9 @ we think we have handled things
	149
	150
	151	look_for_VFP_exceptions:
c98929c0 CM	152	@ Check for synchronous or asynchronous exception
c98929c0 CM	153	tst r1, #FPEXC_EX \| FPEXC_DEX
1da177e4	154	bne process_exception
c98929c0 CM	155	@ On some implementations of the VFP subarch 1, setting FPSCR.IXE
	156	@ causes all the CDP instructions to be bounced synchronously without
	157	@ setting the FPEXC.EX bit
1da177e4	158	VFPFMRX r5, FPSCR
c98929c0	159	tst r5, #FPSCR_IXE
1da177e4 LT	160	bne process_exception
	161
	162	@ Fall into hand on to next handler - appropriate coproc instr
	163	@ not recognised by VFP
	164
	165	DBGSTR "not VFP"
f2255be8 GD	166	#ifdef CONFIG_PREEMPT
	167	get_thread_info r10
	168	ldr r4, [r10, #TI_PREEMPT] @ get preempt count
	169	sub r11, r4, #1 @ decrement it
	170	str r11, [r10, #TI_PREEMPT]
	171	#endif
1da177e4 LT	172	mov pc, lr
	173
	174	process_exception:
	175	DBGSTR "bounce"
1da177e4 LT	176	mov r2, sp @ nothing stacked - regdump is at TOS
	177	mov lr, r9 @ setup for a return to the user code.
	178
	179	@ Now call the C code to package up the bounce to the support code
	180	@ r0 holds the trigger instruction
	181	@ r1 holds the FPEXC value
	182	@ r2 pointer to register dump
c98929c0	183	b VFP_bounce @ we have handled this - the support
1da177e4 LT	184	@ code will raise an exception if
	185	@ required. If not, the user code will
	186	@ retry the faulted instruction
93ed3970	187	ENDPROC(vfp_support_entry)
1da177e4	188
93ed3970	189	ENTRY(vfp_save_state)
c6428464 CM	190	@ Save the current VFP state
	191	@ r0 - save location
	192	@ r1 - FPEXC
	193	DBGSTR1 "save VFP state %p", r0
25ebee02	194	VFPFSTMIA r0, r2 @ save the working registers
c6428464	195	VFPFMRX r2, FPSCR @ current status
c98929c0	196	tst r1, #FPEXC_EX @ is there additional state to save?
24b647a0 CM	197	beq 1f
	198	VFPFMRX r3, FPINST @ FPINST (only if FPEXC.EX is set)
	199	tst r1, #FPEXC_FP2V @ is there an FPINST2 to read?
	200	beq 1f
	201	VFPFMRX r12, FPINST2 @ FPINST2 if needed (and present)
	202	1:
c6428464 CM	203	stmia r0, {r1, r2, r3, r12} @ save FPEXC, FPSCR, FPINST, FPINST2
c6428464 CM	204	mov pc, lr
93ed3970	205	ENDPROC(vfp_save_state)
c6428464	206
7eb25ebe	207	.align
af61bdf0 RK	208	vfp_current_hw_state_address:
af61bdf0 RK	209	.word vfp_current_hw_state
1da177e4	210
07f33a03 CM	211	.macro tbl_branch, base, tmp, shift
	212	#ifdef CONFIG_THUMB2_KERNEL
	213	adr \tmp, 1f
	214	add \tmp, \tmp, \base, lsl \shift
	215	mov pc, \tmp
	216	#else
	217	add pc, pc, \base, lsl \shift
1da177e4	218	mov r0, r0
07f33a03 CM	219	#endif
	220	1:
	221	.endm
	222
	223	ENTRY(vfp_get_float)
	224	tbl_branch r0, r3, #3
1da177e4	225	.irp dr,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15
07f33a03	226	1: mrc p10, 0, r0, c\dr, c0, 0 @ fmrs r0, s0
1da177e4	227	mov pc, lr
07f33a03 CM	228	.org 1b + 8
07f33a03 CM	229	1: mrc p10, 0, r0, c\dr, c0, 4 @ fmrs r0, s1
1da177e4	230	mov pc, lr
07f33a03	231	.org 1b + 8
1da177e4	232	.endr
93ed3970	233	ENDPROC(vfp_get_float)
1da177e4	234
93ed3970	235	ENTRY(vfp_put_float)
07f33a03	236	tbl_branch r1, r3, #3
1da177e4	237	.irp dr,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15
07f33a03	238	1: mcr p10, 0, r0, c\dr, c0, 0 @ fmsr r0, s0
1da177e4	239	mov pc, lr
07f33a03 CM	240	.org 1b + 8
07f33a03 CM	241	1: mcr p10, 0, r0, c\dr, c0, 4 @ fmsr r0, s1
1da177e4	242	mov pc, lr
07f33a03	243	.org 1b + 8
1da177e4	244	.endr
93ed3970	245	ENDPROC(vfp_put_float)
1da177e4	246
93ed3970	247	ENTRY(vfp_get_double)
07f33a03	248	tbl_branch r0, r3, #3
1da177e4	249	.irp dr,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15
07f33a03	250	1: fmrrd r0, r1, d\dr
1da177e4	251	mov pc, lr
07f33a03	252	.org 1b + 8
1da177e4	253	.endr
25ebee02 CM	254	#ifdef CONFIG_VFPv3
	255	@ d16 - d31 registers
	256	.irp dr,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15
07f33a03	257	1: mrrc p11, 3, r0, r1, c\dr @ fmrrd r0, r1, d\dr
25ebee02	258	mov pc, lr
07f33a03	259	.org 1b + 8
25ebee02 CM	260	.endr
25ebee02 CM	261	#endif
1da177e4	262
25ebee02	263	@ virtual register 16 (or 32 if VFPv3) for compare with zero
1da177e4 LT	264	mov r0, #0
	265	mov r1, #0
	266	mov pc, lr
93ed3970	267	ENDPROC(vfp_get_double)
1da177e4	268
93ed3970	269	ENTRY(vfp_put_double)
07f33a03	270	tbl_branch r2, r3, #3
1da177e4	271	.irp dr,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15
07f33a03	272	1: fmdrr d\dr, r0, r1
1da177e4	273	mov pc, lr
07f33a03	274	.org 1b + 8
1da177e4	275	.endr
25ebee02 CM	276	#ifdef CONFIG_VFPv3
	277	@ d16 - d31 registers
	278	.irp dr,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15
138de1c4	279	1: mcrr p11, 3, r0, r1, c\dr @ fmdrr r0, r1, d\dr
25ebee02	280	mov pc, lr
07f33a03	281	.org 1b + 8
25ebee02 CM	282	.endr
25ebee02 CM	283	#endif
93ed3970	284	ENDPROC(vfp_put_double)