[deliverable/linux.git] / arch / arm / vfp / vfphw.S

/*
 *  linux/arch/arm/vfp/vfphw.S
 *
 *  Copyright (C) 2004 ARM Limited.
 *  Written by Deep Blue Solutions Limited.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 *
 * This code is called from the kernel's undefined instruction trap.
 * r9 holds the return address for successful handling.
 * lr holds the return address for unrecognised instructions.
 * r10 points at the start of the private FP workspace in the thread structure
 * sp points to a struct pt_regs (as defined in include/asm/proc/ptrace.h)
 */
#include <asm/thread_info.h>
#include <asm/vfpmacros.h>
#include <linux/kern_levels.h>
#include "../kernel/entry-header.S"

	.macro	DBGSTR, str
#ifdef DEBUG
	stmfd	sp!, {r0-r3, ip, lr}
	add	r0, pc, #4
	bl	printk
	b	1f
	.asciz  KERN_DEBUG "VFP: \str\n"
	.balign 4
1:	ldmfd	sp!, {r0-r3, ip, lr}
#endif
	.endm

	.macro  DBGSTR1, str, arg
#ifdef DEBUG
	stmfd	sp!, {r0-r3, ip, lr}
	mov	r1, \arg
	add	r0, pc, #4
	bl	printk
	b	1f
	.asciz  KERN_DEBUG "VFP: \str\n"
	.balign 4
1:	ldmfd	sp!, {r0-r3, ip, lr}
#endif
	.endm

	.macro  DBGSTR3, str, arg1, arg2, arg3
#ifdef DEBUG
	stmfd	sp!, {r0-r3, ip, lr}
	mov	r3, \arg3
	mov	r2, \arg2
	mov	r1, \arg1
	add	r0, pc, #4
	bl	printk
	b	1f
	.asciz  KERN_DEBUG "VFP: \str\n"
	.balign 4
1:	ldmfd	sp!, {r0-r3, ip, lr}
#endif
	.endm


@ VFP hardware support entry point.
@
@  r0  = faulted instruction
@  r2  = faulted PC+4
@  r9  = successful return
@  r10 = vfp_state union
@  r11 = CPU number
@  lr  = failure return

ENTRY(vfp_support_entry)
	DBGSTR3	"instr %08x pc %08x state %p", r0, r2, r10

	VFPFMRX	r1, FPEXC		@ Is the VFP enabled?
	DBGSTR1	"fpexc %08x", r1
	tst	r1, #FPEXC_EN
	bne	look_for_VFP_exceptions	@ VFP is already enabled

	DBGSTR1 "enable %x", r10
	ldr	r3, vfp_current_hw_state_address
	orr	r1, r1, #FPEXC_EN	@ user FPEXC has the enable bit set
	ldr	r4, [r3, r11, lsl #2]	@ vfp_current_hw_state pointer
	bic	r5, r1, #FPEXC_EX	@ make sure exceptions are disabled
	cmp	r4, r10			@ this thread owns the hw context?
#ifndef CONFIG_SMP
	@ For UP, checking that this thread owns the hw context is
	@ sufficient to determine that the hardware state is valid.
	beq	vfp_hw_state_valid

	@ On UP, we lazily save the VFP context.  As a different
	@ thread wants ownership of the VFP hardware, save the old
	@ state if there was a previous (valid) owner.

	VFPFMXR	FPEXC, r5		@ enable VFP, disable any pending
					@ exceptions, so we can get at the
					@ rest of it

	DBGSTR1	"save old state %p", r4
	cmp	r4, #0			@ if the vfp_current_hw_state is NULL
	beq	vfp_reload_hw		@ then the hw state needs reloading
	VFPFSTMIA r4, r5		@ save the working registers
	VFPFMRX	r5, FPSCR		@ current status
#ifndef CONFIG_CPU_FEROCEON
	tst	r1, #FPEXC_EX		@ is there additional state to save?
	beq	1f
	VFPFMRX	r6, FPINST		@ FPINST (only if FPEXC.EX is set)
	tst	r1, #FPEXC_FP2V		@ is there an FPINST2 to read?
	beq	1f
	VFPFMRX	r8, FPINST2		@ FPINST2 if needed (and present)
1:
#endif
	stmia	r4, {r1, r5, r6, r8}	@ save FPEXC, FPSCR, FPINST, FPINST2
vfp_reload_hw:

#else
	@ For SMP, if this thread does not own the hw context, then we
	@ need to reload it.  No need to save the old state as on SMP,
	@ we always save the state when we switch away from a thread.
	bne	vfp_reload_hw

	@ This thread has ownership of the current hardware context.
	@ However, it may have been migrated to another CPU, in which
	@ case the saved state is newer than the hardware context.
	@ Check this by looking at the CPU number which the state was
	@ last loaded onto.
	ldr	ip, [r10, #VFP_CPU]
	teq	ip, r11
	beq	vfp_hw_state_valid

vfp_reload_hw:
	@ We're loading this threads state into the VFP hardware. Update
	@ the CPU number which contains the most up to date VFP context.
	str	r11, [r10, #VFP_CPU]

	VFPFMXR	FPEXC, r5		@ enable VFP, disable any pending
					@ exceptions, so we can get at the
					@ rest of it
#endif

	DBGSTR1	"load state %p", r10
	str	r10, [r3, r11, lsl #2]	@ update the vfp_current_hw_state pointer
					@ Load the saved state back into the VFP
	VFPFLDMIA r10, r5		@ reload the working registers while
					@ FPEXC is in a safe state
	ldmia	r10, {r1, r5, r6, r8}	@ load FPEXC, FPSCR, FPINST, FPINST2
#ifndef CONFIG_CPU_FEROCEON
	tst	r1, #FPEXC_EX		@ is there additional state to restore?
	beq	1f
	VFPFMXR	FPINST, r6		@ restore FPINST (only if FPEXC.EX is set)
	tst	r1, #FPEXC_FP2V		@ is there an FPINST2 to write?
	beq	1f
	VFPFMXR	FPINST2, r8		@ FPINST2 if needed (and present)
1:
#endif
	VFPFMXR	FPSCR, r5		@ restore status

@ The context stored in the VFP hardware is up to date with this thread
vfp_hw_state_valid:
	tst	r1, #FPEXC_EX
	bne	process_exception	@ might as well handle the pending
					@ exception before retrying branch
					@ out before setting an FPEXC that
					@ stops us reading stuff
	VFPFMXR	FPEXC, r1		@ restore FPEXC last
	sub	r2, r2, #4
	str	r2, [sp, #S_PC]		@ retry the instruction
#ifdef CONFIG_PREEMPT
	get_thread_info	r10
	ldr	r4, [r10, #TI_PREEMPT]	@ get preempt count
	sub	r11, r4, #1		@ decrement it
	str	r11, [r10, #TI_PREEMPT]
#endif
	mov	pc, r9			@ we think we have handled things


look_for_VFP_exceptions:
	@ Check for synchronous or asynchronous exception
	tst	r1, #FPEXC_EX | FPEXC_DEX
	bne	process_exception
	@ On some implementations of the VFP subarch 1, setting FPSCR.IXE
	@ causes all the CDP instructions to be bounced synchronously without
	@ setting the FPEXC.EX bit
	VFPFMRX	r5, FPSCR
	tst	r5, #FPSCR_IXE
	bne	process_exception

	@ Fall into hand on to next handler - appropriate coproc instr
	@ not recognised by VFP

	DBGSTR	"not VFP"
#ifdef CONFIG_PREEMPT
	get_thread_info	r10
	ldr	r4, [r10, #TI_PREEMPT]	@ get preempt count
	sub	r11, r4, #1		@ decrement it
	str	r11, [r10, #TI_PREEMPT]
#endif
	mov	pc, lr

process_exception:
	DBGSTR	"bounce"
	mov	r2, sp			@ nothing stacked - regdump is at TOS
	mov	lr, r9			@ setup for a return to the user code.

	@ Now call the C code to package up the bounce to the support code
	@   r0 holds the trigger instruction
	@   r1 holds the FPEXC value
	@   r2 pointer to register dump
	b	VFP_bounce		@ we have handled this - the support
					@ code will raise an exception if
					@ required. If not, the user code will
					@ retry the faulted instruction
ENDPROC(vfp_support_entry)

ENTRY(vfp_save_state)
	@ Save the current VFP state
	@ r0 - save location
	@ r1 - FPEXC
	DBGSTR1	"save VFP state %p", r0
	VFPFSTMIA r0, r2		@ save the working registers
	VFPFMRX	r2, FPSCR		@ current status
	tst	r1, #FPEXC_EX		@ is there additional state to save?
	beq	1f
	VFPFMRX	r3, FPINST		@ FPINST (only if FPEXC.EX is set)
	tst	r1, #FPEXC_FP2V		@ is there an FPINST2 to read?
	beq	1f
	VFPFMRX	r12, FPINST2		@ FPINST2 if needed (and present)
1:
	stmia	r0, {r1, r2, r3, r12}	@ save FPEXC, FPSCR, FPINST, FPINST2
	mov	pc, lr
ENDPROC(vfp_save_state)

	.align
vfp_current_hw_state_address:
	.word	vfp_current_hw_state

	.macro	tbl_branch, base, tmp, shift
#ifdef CONFIG_THUMB2_KERNEL
	adr	\tmp, 1f
	add	\tmp, \tmp, \base, lsl \shift
	mov	pc, \tmp
#else
	add	pc, pc, \base, lsl \shift
	mov	r0, r0
#endif
1:
	.endm

ENTRY(vfp_get_float)
	tbl_branch r0, r3, #3
	.irp	dr,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15
1:	mrc	p10, 0, r0, c\dr, c0, 0	@ fmrs	r0, s0
	mov	pc, lr
	.org	1b + 8
1:	mrc	p10, 0, r0, c\dr, c0, 4	@ fmrs	r0, s1
	mov	pc, lr
	.org	1b + 8
	.endr
ENDPROC(vfp_get_float)

ENTRY(vfp_put_float)
	tbl_branch r1, r3, #3
	.irp	dr,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15
1:	mcr	p10, 0, r0, c\dr, c0, 0	@ fmsr	r0, s0
	mov	pc, lr
	.org	1b + 8
1:	mcr	p10, 0, r0, c\dr, c0, 4	@ fmsr	r0, s1
	mov	pc, lr
	.org	1b + 8
	.endr
ENDPROC(vfp_put_float)

ENTRY(vfp_get_double)
	tbl_branch r0, r3, #3
	.irp	dr,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15
1:	fmrrd	r0, r1, d\dr
	mov	pc, lr
	.org	1b + 8
	.endr
#ifdef CONFIG_VFPv3
	@ d16 - d31 registers
	.irp	dr,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15
1:	mrrc	p11, 3, r0, r1, c\dr	@ fmrrd	r0, r1, d\dr
	mov	pc, lr
	.org	1b + 8
	.endr
#endif

	@ virtual register 16 (or 32 if VFPv3) for compare with zero
	mov	r0, #0
	mov	r1, #0
	mov	pc, lr
ENDPROC(vfp_get_double)

ENTRY(vfp_put_double)
	tbl_branch r2, r3, #3
	.irp	dr,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15
1:	fmdrr	d\dr, r0, r1
	mov	pc, lr
	.org	1b + 8
	.endr
#ifdef CONFIG_VFPv3
	@ d16 - d31 registers
	.irp	dr,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15
1:	mcrr	p11, 3, r0, r1, c\dr	@ fmdrr	r0, r1, d\dr
	mov	pc, lr
	.org	1b + 8
	.endr
#endif
ENDPROC(vfp_put_double)
Commit	Line	Data
1da177e4 LT	1	/*
	2	* linux/arch/arm/vfp/vfphw.S
	3	*
	4	* Copyright (C) 2004 ARM Limited.
	5	* Written by Deep Blue Solutions Limited.
	6	*
	7	* This program is free software; you can redistribute it and/or modify
	8	* it under the terms of the GNU General Public License version 2 as
	9	* published by the Free Software Foundation.
	10	*
	11	* This code is called from the kernel's undefined instruction trap.
	12	* r9 holds the return address for successful handling.
	13	* lr holds the return address for unrecognised instructions.
	14	* r10 points at the start of the private FP workspace in the thread structure
	15	* sp points to a struct pt_regs (as defined in include/asm/proc/ptrace.h)
	16	*/
	17	#include <asm/thread_info.h>
	18	#include <asm/vfpmacros.h>
0cc41e4a	19	#include <linux/kern_levels.h>
1da177e4 LT	20	#include "../kernel/entry-header.S"
	21
	22	.macro DBGSTR, str
	23	#ifdef DEBUG
	24	stmfd sp!, {r0-r3, ip, lr}
	25	add r0, pc, #4
	26	bl printk
	27	b 1f
0cc41e4a	28	.asciz KERN_DEBUG "VFP: \str\n"
1da177e4 LT	29	.balign 4
	30	1: ldmfd sp!, {r0-r3, ip, lr}
	31	#endif
	32	.endm
	33
	34	.macro DBGSTR1, str, arg
	35	#ifdef DEBUG
	36	stmfd sp!, {r0-r3, ip, lr}
	37	mov r1, \arg
	38	add r0, pc, #4
	39	bl printk
	40	b 1f
0cc41e4a	41	.asciz KERN_DEBUG "VFP: \str\n"
1da177e4 LT	42	.balign 4
	43	1: ldmfd sp!, {r0-r3, ip, lr}
	44	#endif
	45	.endm
	46
	47	.macro DBGSTR3, str, arg1, arg2, arg3
	48	#ifdef DEBUG
	49	stmfd sp!, {r0-r3, ip, lr}
	50	mov r3, \arg3
	51	mov r2, \arg2
	52	mov r1, \arg1
	53	add r0, pc, #4
	54	bl printk
	55	b 1f
0cc41e4a	56	.asciz KERN_DEBUG "VFP: \str\n"
1da177e4 LT	57	.balign 4
	58	1: ldmfd sp!, {r0-r3, ip, lr}
	59	#endif
	60	.endm
	61
	62
	63	@ VFP hardware support entry point.
	64	@
	65	@ r0 = faulted instruction
	66	@ r2 = faulted PC+4
	67	@ r9 = successful return
	68	@ r10 = vfp_state union
c6428464	69	@ r11 = CPU number
1da177e4 LT	70	@ lr = failure return
1da177e4 LT	71
93ed3970	72	ENTRY(vfp_support_entry)
1da177e4 LT	73	DBGSTR3 "instr %08x pc %08x state %p", r0, r2, r10
	74
	75	VFPFMRX r1, FPEXC @ Is the VFP enabled?
	76	DBGSTR1 "fpexc %08x", r1
228adef1	77	tst r1, #FPEXC_EN
1da177e4 LT	78	bne look_for_VFP_exceptions @ VFP is already enabled
	79
	80	DBGSTR1 "enable %x", r10
af61bdf0	81	ldr r3, vfp_current_hw_state_address
228adef1	82	orr r1, r1, #FPEXC_EN @ user FPEXC has the enable bit set
af61bdf0	83	ldr r4, [r3, r11, lsl #2] @ vfp_current_hw_state pointer
228adef1	84	bic r5, r1, #FPEXC_EX @ make sure exceptions are disabled
08409c33	85	cmp r4, r10 @ this thread owns the hw context?
f8f2a852 RK	86	#ifndef CONFIG_SMP
	87	@ For UP, checking that this thread owns the hw context is
	88	@ sufficient to determine that the hardware state is valid.
08409c33	89	beq vfp_hw_state_valid
1da177e4	90
f8f2a852 RK	91	@ On UP, we lazily save the VFP context. As a different
	92	@ thread wants ownership of the VFP hardware, save the old
	93	@ state if there was a previous (valid) owner.
	94
1da177e4 LT	95	VFPFMXR FPEXC, r5 @ enable VFP, disable any pending
	96	@ exceptions, so we can get at the
	97	@ rest of it
	98
1da177e4	99	DBGSTR1 "save old state %p", r4
f8f2a852 RK	100	cmp r4, #0 @ if the vfp_current_hw_state is NULL
f8f2a852 RK	101	beq vfp_reload_hw @ then the hw state needs reloading
25ebee02	102	VFPFSTMIA r4, r5 @ save the working registers
1da177e4	103	VFPFMRX r5, FPSCR @ current status
85d6943a	104	#ifndef CONFIG_CPU_FEROCEON
c98929c0	105	tst r1, #FPEXC_EX @ is there additional state to save?
24b647a0 CM	106	beq 1f
	107	VFPFMRX r6, FPINST @ FPINST (only if FPEXC.EX is set)
	108	tst r1, #FPEXC_FP2V @ is there an FPINST2 to read?
	109	beq 1f
	110	VFPFMRX r8, FPINST2 @ FPINST2 if needed (and present)
	111	1:
85d6943a	112	#endif
1da177e4	113	stmia r4, {r1, r5, r6, r8} @ save FPEXC, FPSCR, FPINST, FPINST2
f8f2a852 RK	114	vfp_reload_hw:
	115
	116	#else
	117	@ For SMP, if this thread does not own the hw context, then we
	118	@ need to reload it. No need to save the old state as on SMP,
	119	@ we always save the state when we switch away from a thread.
	120	bne vfp_reload_hw
	121
	122	@ This thread has ownership of the current hardware context.
	123	@ However, it may have been migrated to another CPU, in which
	124	@ case the saved state is newer than the hardware context.
	125	@ Check this by looking at the CPU number which the state was
	126	@ last loaded onto.
	127	ldr ip, [r10, #VFP_CPU]
	128	teq ip, r11
	129	beq vfp_hw_state_valid
	130
	131	vfp_reload_hw:
	132	@ We're loading this threads state into the VFP hardware. Update
	133	@ the CPU number which contains the most up to date VFP context.
	134	str r11, [r10, #VFP_CPU]
	135
	136	VFPFMXR FPEXC, r5 @ enable VFP, disable any pending
	137	@ exceptions, so we can get at the
	138	@ rest of it
c6428464	139	#endif
1da177e4	140
1da177e4	141	DBGSTR1 "load state %p", r10
af61bdf0	142	str r10, [r3, r11, lsl #2] @ update the vfp_current_hw_state pointer
1da177e4	143	@ Load the saved state back into the VFP
25ebee02	144	VFPFLDMIA r10, r5 @ reload the working registers while
1da177e4	145	@ FPEXC is in a safe state
80ed3547	146	ldmia r10, {r1, r5, r6, r8} @ load FPEXC, FPSCR, FPINST, FPINST2
85d6943a	147	#ifndef CONFIG_CPU_FEROCEON
c98929c0	148	tst r1, #FPEXC_EX @ is there additional state to restore?
24b647a0 CM	149	beq 1f
	150	VFPFMXR FPINST, r6 @ restore FPINST (only if FPEXC.EX is set)
	151	tst r1, #FPEXC_FP2V @ is there an FPINST2 to write?
	152	beq 1f
	153	VFPFMXR FPINST2, r8 @ FPINST2 if needed (and present)
	154	1:
85d6943a	155	#endif
1da177e4 LT	156	VFPFMXR FPSCR, r5 @ restore status
1da177e4 LT	157
08409c33 RK	158	@ The context stored in the VFP hardware is up to date with this thread
08409c33 RK	159	vfp_hw_state_valid:
228adef1	160	tst r1, #FPEXC_EX
1da177e4 LT	161	bne process_exception @ might as well handle the pending
	162	@ exception before retrying branch
	163	@ out before setting an FPEXC that
	164	@ stops us reading stuff
	165	VFPFMXR FPEXC, r1 @ restore FPEXC last
	166	sub r2, r2, #4
	167	str r2, [sp, #S_PC] @ retry the instruction
f2255be8 GD	168	#ifdef CONFIG_PREEMPT
	169	get_thread_info r10
	170	ldr r4, [r10, #TI_PREEMPT] @ get preempt count
	171	sub r11, r4, #1 @ decrement it
	172	str r11, [r10, #TI_PREEMPT]
	173	#endif
1da177e4 LT	174	mov pc, r9 @ we think we have handled things
	175
	176
	177	look_for_VFP_exceptions:
c98929c0 CM	178	@ Check for synchronous or asynchronous exception
c98929c0 CM	179	tst r1, #FPEXC_EX \| FPEXC_DEX
1da177e4	180	bne process_exception
c98929c0 CM	181	@ On some implementations of the VFP subarch 1, setting FPSCR.IXE
	182	@ causes all the CDP instructions to be bounced synchronously without
	183	@ setting the FPEXC.EX bit
1da177e4	184	VFPFMRX r5, FPSCR
c98929c0	185	tst r5, #FPSCR_IXE
1da177e4 LT	186	bne process_exception
	187
	188	@ Fall into hand on to next handler - appropriate coproc instr
	189	@ not recognised by VFP
	190
	191	DBGSTR "not VFP"
f2255be8 GD	192	#ifdef CONFIG_PREEMPT
	193	get_thread_info r10
	194	ldr r4, [r10, #TI_PREEMPT] @ get preempt count
	195	sub r11, r4, #1 @ decrement it
	196	str r11, [r10, #TI_PREEMPT]
	197	#endif
1da177e4 LT	198	mov pc, lr
	199
	200	process_exception:
	201	DBGSTR "bounce"
1da177e4 LT	202	mov r2, sp @ nothing stacked - regdump is at TOS
	203	mov lr, r9 @ setup for a return to the user code.
	204
	205	@ Now call the C code to package up the bounce to the support code
	206	@ r0 holds the trigger instruction
	207	@ r1 holds the FPEXC value
	208	@ r2 pointer to register dump
c98929c0	209	b VFP_bounce @ we have handled this - the support
1da177e4 LT	210	@ code will raise an exception if
	211	@ required. If not, the user code will
	212	@ retry the faulted instruction
93ed3970	213	ENDPROC(vfp_support_entry)
1da177e4	214
93ed3970	215	ENTRY(vfp_save_state)
c6428464 CM	216	@ Save the current VFP state
	217	@ r0 - save location
	218	@ r1 - FPEXC
	219	DBGSTR1 "save VFP state %p", r0
25ebee02	220	VFPFSTMIA r0, r2 @ save the working registers
c6428464	221	VFPFMRX r2, FPSCR @ current status
c98929c0	222	tst r1, #FPEXC_EX @ is there additional state to save?
24b647a0 CM	223	beq 1f
	224	VFPFMRX r3, FPINST @ FPINST (only if FPEXC.EX is set)
	225	tst r1, #FPEXC_FP2V @ is there an FPINST2 to read?
	226	beq 1f
	227	VFPFMRX r12, FPINST2 @ FPINST2 if needed (and present)
	228	1:
c6428464 CM	229	stmia r0, {r1, r2, r3, r12} @ save FPEXC, FPSCR, FPINST, FPINST2
c6428464 CM	230	mov pc, lr
93ed3970	231	ENDPROC(vfp_save_state)
c6428464	232
7eb25ebe	233	.align
af61bdf0 RK	234	vfp_current_hw_state_address:
af61bdf0 RK	235	.word vfp_current_hw_state
1da177e4	236
07f33a03 CM	237	.macro tbl_branch, base, tmp, shift
	238	#ifdef CONFIG_THUMB2_KERNEL
	239	adr \tmp, 1f
	240	add \tmp, \tmp, \base, lsl \shift
	241	mov pc, \tmp
	242	#else
	243	add pc, pc, \base, lsl \shift
1da177e4	244	mov r0, r0
07f33a03 CM	245	#endif
	246	1:
	247	.endm
	248
	249	ENTRY(vfp_get_float)
	250	tbl_branch r0, r3, #3
1da177e4	251	.irp dr,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15
07f33a03	252	1: mrc p10, 0, r0, c\dr, c0, 0 @ fmrs r0, s0
1da177e4	253	mov pc, lr
07f33a03 CM	254	.org 1b + 8
07f33a03 CM	255	1: mrc p10, 0, r0, c\dr, c0, 4 @ fmrs r0, s1
1da177e4	256	mov pc, lr
07f33a03	257	.org 1b + 8
1da177e4	258	.endr
93ed3970	259	ENDPROC(vfp_get_float)
1da177e4	260
93ed3970	261	ENTRY(vfp_put_float)
07f33a03	262	tbl_branch r1, r3, #3
1da177e4	263	.irp dr,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15
07f33a03	264	1: mcr p10, 0, r0, c\dr, c0, 0 @ fmsr r0, s0
1da177e4	265	mov pc, lr
07f33a03 CM	266	.org 1b + 8
07f33a03 CM	267	1: mcr p10, 0, r0, c\dr, c0, 4 @ fmsr r0, s1
1da177e4	268	mov pc, lr
07f33a03	269	.org 1b + 8
1da177e4	270	.endr
93ed3970	271	ENDPROC(vfp_put_float)
1da177e4	272
93ed3970	273	ENTRY(vfp_get_double)
07f33a03	274	tbl_branch r0, r3, #3
1da177e4	275	.irp dr,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15
07f33a03	276	1: fmrrd r0, r1, d\dr
1da177e4	277	mov pc, lr
07f33a03	278	.org 1b + 8
1da177e4	279	.endr
25ebee02 CM	280	#ifdef CONFIG_VFPv3
	281	@ d16 - d31 registers
	282	.irp dr,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15
07f33a03	283	1: mrrc p11, 3, r0, r1, c\dr @ fmrrd r0, r1, d\dr
25ebee02	284	mov pc, lr
07f33a03	285	.org 1b + 8
25ebee02 CM	286	.endr
25ebee02 CM	287	#endif
1da177e4	288
25ebee02	289	@ virtual register 16 (or 32 if VFPv3) for compare with zero
1da177e4 LT	290	mov r0, #0
	291	mov r1, #0
	292	mov pc, lr
93ed3970	293	ENDPROC(vfp_get_double)
1da177e4	294
93ed3970	295	ENTRY(vfp_put_double)
07f33a03	296	tbl_branch r2, r3, #3
1da177e4	297	.irp dr,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15
07f33a03	298	1: fmdrr d\dr, r0, r1
1da177e4	299	mov pc, lr
07f33a03	300	.org 1b + 8
1da177e4	301	.endr
25ebee02 CM	302	#ifdef CONFIG_VFPv3
	303	@ d16 - d31 registers
	304	.irp dr,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15
138de1c4	305	1: mcrr p11, 3, r0, r1, c\dr @ fmdrr r0, r1, d\dr
25ebee02	306	mov pc, lr
07f33a03	307	.org 1b + 8
25ebee02 CM	308	.endr
25ebee02 CM	309	#endif
93ed3970	310	ENDPROC(vfp_put_double)