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1da177e4 LT |
1 | /* |
2 | * linux/arch/arm/vfp/vfphw.S | |
3 | * | |
4 | * Copyright (C) 2004 ARM Limited. | |
5 | * Written by Deep Blue Solutions Limited. | |
6 | * | |
7 | * This program is free software; you can redistribute it and/or modify | |
8 | * it under the terms of the GNU General Public License version 2 as | |
9 | * published by the Free Software Foundation. | |
10 | * | |
11 | * This code is called from the kernel's undefined instruction trap. | |
12 | * r9 holds the return address for successful handling. | |
13 | * lr holds the return address for unrecognised instructions. | |
14 | * r10 points at the start of the private FP workspace in the thread structure | |
15 | * sp points to a struct pt_regs (as defined in include/asm/proc/ptrace.h) | |
16 | */ | |
17 | #include <asm/thread_info.h> | |
18 | #include <asm/vfpmacros.h> | |
19 | #include "../kernel/entry-header.S" | |
20 | ||
21 | .macro DBGSTR, str | |
22 | #ifdef DEBUG | |
23 | stmfd sp!, {r0-r3, ip, lr} | |
24 | add r0, pc, #4 | |
25 | bl printk | |
26 | b 1f | |
27 | .asciz "<7>VFP: \str\n" | |
28 | .balign 4 | |
29 | 1: ldmfd sp!, {r0-r3, ip, lr} | |
30 | #endif | |
31 | .endm | |
32 | ||
33 | .macro DBGSTR1, str, arg | |
34 | #ifdef DEBUG | |
35 | stmfd sp!, {r0-r3, ip, lr} | |
36 | mov r1, \arg | |
37 | add r0, pc, #4 | |
38 | bl printk | |
39 | b 1f | |
40 | .asciz "<7>VFP: \str\n" | |
41 | .balign 4 | |
42 | 1: ldmfd sp!, {r0-r3, ip, lr} | |
43 | #endif | |
44 | .endm | |
45 | ||
46 | .macro DBGSTR3, str, arg1, arg2, arg3 | |
47 | #ifdef DEBUG | |
48 | stmfd sp!, {r0-r3, ip, lr} | |
49 | mov r3, \arg3 | |
50 | mov r2, \arg2 | |
51 | mov r1, \arg1 | |
52 | add r0, pc, #4 | |
53 | bl printk | |
54 | b 1f | |
55 | .asciz "<7>VFP: \str\n" | |
56 | .balign 4 | |
57 | 1: ldmfd sp!, {r0-r3, ip, lr} | |
58 | #endif | |
59 | .endm | |
60 | ||
61 | ||
62 | @ VFP hardware support entry point. | |
63 | @ | |
64 | @ r0 = faulted instruction | |
65 | @ r2 = faulted PC+4 | |
66 | @ r9 = successful return | |
67 | @ r10 = vfp_state union | |
c6428464 | 68 | @ r11 = CPU number |
1da177e4 LT |
69 | @ lr = failure return |
70 | ||
93ed3970 | 71 | ENTRY(vfp_support_entry) |
1da177e4 LT |
72 | DBGSTR3 "instr %08x pc %08x state %p", r0, r2, r10 |
73 | ||
74 | VFPFMRX r1, FPEXC @ Is the VFP enabled? | |
75 | DBGSTR1 "fpexc %08x", r1 | |
228adef1 | 76 | tst r1, #FPEXC_EN |
1da177e4 LT |
77 | bne look_for_VFP_exceptions @ VFP is already enabled |
78 | ||
79 | DBGSTR1 "enable %x", r10 | |
af61bdf0 | 80 | ldr r3, vfp_current_hw_state_address |
228adef1 | 81 | orr r1, r1, #FPEXC_EN @ user FPEXC has the enable bit set |
af61bdf0 | 82 | ldr r4, [r3, r11, lsl #2] @ vfp_current_hw_state pointer |
228adef1 | 83 | bic r5, r1, #FPEXC_EX @ make sure exceptions are disabled |
08409c33 | 84 | cmp r4, r10 @ this thread owns the hw context? |
f8f2a852 RK |
85 | #ifndef CONFIG_SMP |
86 | @ For UP, checking that this thread owns the hw context is | |
87 | @ sufficient to determine that the hardware state is valid. | |
08409c33 | 88 | beq vfp_hw_state_valid |
1da177e4 | 89 | |
f8f2a852 RK |
90 | @ On UP, we lazily save the VFP context. As a different |
91 | @ thread wants ownership of the VFP hardware, save the old | |
92 | @ state if there was a previous (valid) owner. | |
93 | ||
1da177e4 LT |
94 | VFPFMXR FPEXC, r5 @ enable VFP, disable any pending |
95 | @ exceptions, so we can get at the | |
96 | @ rest of it | |
97 | ||
1da177e4 | 98 | DBGSTR1 "save old state %p", r4 |
f8f2a852 RK |
99 | cmp r4, #0 @ if the vfp_current_hw_state is NULL |
100 | beq vfp_reload_hw @ then the hw state needs reloading | |
25ebee02 | 101 | VFPFSTMIA r4, r5 @ save the working registers |
1da177e4 | 102 | VFPFMRX r5, FPSCR @ current status |
85d6943a | 103 | #ifndef CONFIG_CPU_FEROCEON |
c98929c0 | 104 | tst r1, #FPEXC_EX @ is there additional state to save? |
24b647a0 CM |
105 | beq 1f |
106 | VFPFMRX r6, FPINST @ FPINST (only if FPEXC.EX is set) | |
107 | tst r1, #FPEXC_FP2V @ is there an FPINST2 to read? | |
108 | beq 1f | |
109 | VFPFMRX r8, FPINST2 @ FPINST2 if needed (and present) | |
110 | 1: | |
85d6943a | 111 | #endif |
1da177e4 | 112 | stmia r4, {r1, r5, r6, r8} @ save FPEXC, FPSCR, FPINST, FPINST2 |
f8f2a852 RK |
113 | vfp_reload_hw: |
114 | ||
115 | #else | |
116 | @ For SMP, if this thread does not own the hw context, then we | |
117 | @ need to reload it. No need to save the old state as on SMP, | |
118 | @ we always save the state when we switch away from a thread. | |
119 | bne vfp_reload_hw | |
120 | ||
121 | @ This thread has ownership of the current hardware context. | |
122 | @ However, it may have been migrated to another CPU, in which | |
123 | @ case the saved state is newer than the hardware context. | |
124 | @ Check this by looking at the CPU number which the state was | |
125 | @ last loaded onto. | |
126 | ldr ip, [r10, #VFP_CPU] | |
127 | teq ip, r11 | |
128 | beq vfp_hw_state_valid | |
129 | ||
130 | vfp_reload_hw: | |
131 | @ We're loading this threads state into the VFP hardware. Update | |
132 | @ the CPU number which contains the most up to date VFP context. | |
133 | str r11, [r10, #VFP_CPU] | |
134 | ||
135 | VFPFMXR FPEXC, r5 @ enable VFP, disable any pending | |
136 | @ exceptions, so we can get at the | |
137 | @ rest of it | |
c6428464 | 138 | #endif |
1da177e4 | 139 | |
1da177e4 | 140 | DBGSTR1 "load state %p", r10 |
af61bdf0 | 141 | str r10, [r3, r11, lsl #2] @ update the vfp_current_hw_state pointer |
1da177e4 | 142 | @ Load the saved state back into the VFP |
25ebee02 | 143 | VFPFLDMIA r10, r5 @ reload the working registers while |
1da177e4 | 144 | @ FPEXC is in a safe state |
80ed3547 | 145 | ldmia r10, {r1, r5, r6, r8} @ load FPEXC, FPSCR, FPINST, FPINST2 |
85d6943a | 146 | #ifndef CONFIG_CPU_FEROCEON |
c98929c0 | 147 | tst r1, #FPEXC_EX @ is there additional state to restore? |
24b647a0 CM |
148 | beq 1f |
149 | VFPFMXR FPINST, r6 @ restore FPINST (only if FPEXC.EX is set) | |
150 | tst r1, #FPEXC_FP2V @ is there an FPINST2 to write? | |
151 | beq 1f | |
152 | VFPFMXR FPINST2, r8 @ FPINST2 if needed (and present) | |
153 | 1: | |
85d6943a | 154 | #endif |
1da177e4 LT |
155 | VFPFMXR FPSCR, r5 @ restore status |
156 | ||
08409c33 RK |
157 | @ The context stored in the VFP hardware is up to date with this thread |
158 | vfp_hw_state_valid: | |
228adef1 | 159 | tst r1, #FPEXC_EX |
1da177e4 LT |
160 | bne process_exception @ might as well handle the pending |
161 | @ exception before retrying branch | |
162 | @ out before setting an FPEXC that | |
163 | @ stops us reading stuff | |
164 | VFPFMXR FPEXC, r1 @ restore FPEXC last | |
165 | sub r2, r2, #4 | |
166 | str r2, [sp, #S_PC] @ retry the instruction | |
f2255be8 GD |
167 | #ifdef CONFIG_PREEMPT |
168 | get_thread_info r10 | |
169 | ldr r4, [r10, #TI_PREEMPT] @ get preempt count | |
170 | sub r11, r4, #1 @ decrement it | |
171 | str r11, [r10, #TI_PREEMPT] | |
172 | #endif | |
1da177e4 LT |
173 | mov pc, r9 @ we think we have handled things |
174 | ||
175 | ||
176 | look_for_VFP_exceptions: | |
c98929c0 CM |
177 | @ Check for synchronous or asynchronous exception |
178 | tst r1, #FPEXC_EX | FPEXC_DEX | |
1da177e4 | 179 | bne process_exception |
c98929c0 CM |
180 | @ On some implementations of the VFP subarch 1, setting FPSCR.IXE |
181 | @ causes all the CDP instructions to be bounced synchronously without | |
182 | @ setting the FPEXC.EX bit | |
1da177e4 | 183 | VFPFMRX r5, FPSCR |
c98929c0 | 184 | tst r5, #FPSCR_IXE |
1da177e4 LT |
185 | bne process_exception |
186 | ||
187 | @ Fall into hand on to next handler - appropriate coproc instr | |
188 | @ not recognised by VFP | |
189 | ||
190 | DBGSTR "not VFP" | |
f2255be8 GD |
191 | #ifdef CONFIG_PREEMPT |
192 | get_thread_info r10 | |
193 | ldr r4, [r10, #TI_PREEMPT] @ get preempt count | |
194 | sub r11, r4, #1 @ decrement it | |
195 | str r11, [r10, #TI_PREEMPT] | |
196 | #endif | |
1da177e4 LT |
197 | mov pc, lr |
198 | ||
199 | process_exception: | |
200 | DBGSTR "bounce" | |
1da177e4 LT |
201 | mov r2, sp @ nothing stacked - regdump is at TOS |
202 | mov lr, r9 @ setup for a return to the user code. | |
203 | ||
204 | @ Now call the C code to package up the bounce to the support code | |
205 | @ r0 holds the trigger instruction | |
206 | @ r1 holds the FPEXC value | |
207 | @ r2 pointer to register dump | |
c98929c0 | 208 | b VFP_bounce @ we have handled this - the support |
1da177e4 LT |
209 | @ code will raise an exception if |
210 | @ required. If not, the user code will | |
211 | @ retry the faulted instruction | |
93ed3970 | 212 | ENDPROC(vfp_support_entry) |
1da177e4 | 213 | |
93ed3970 | 214 | ENTRY(vfp_save_state) |
c6428464 CM |
215 | @ Save the current VFP state |
216 | @ r0 - save location | |
217 | @ r1 - FPEXC | |
218 | DBGSTR1 "save VFP state %p", r0 | |
25ebee02 | 219 | VFPFSTMIA r0, r2 @ save the working registers |
c6428464 | 220 | VFPFMRX r2, FPSCR @ current status |
c98929c0 | 221 | tst r1, #FPEXC_EX @ is there additional state to save? |
24b647a0 CM |
222 | beq 1f |
223 | VFPFMRX r3, FPINST @ FPINST (only if FPEXC.EX is set) | |
224 | tst r1, #FPEXC_FP2V @ is there an FPINST2 to read? | |
225 | beq 1f | |
226 | VFPFMRX r12, FPINST2 @ FPINST2 if needed (and present) | |
227 | 1: | |
c6428464 CM |
228 | stmia r0, {r1, r2, r3, r12} @ save FPEXC, FPSCR, FPINST, FPINST2 |
229 | mov pc, lr | |
93ed3970 | 230 | ENDPROC(vfp_save_state) |
c6428464 | 231 | |
7eb25ebe | 232 | .align |
af61bdf0 RK |
233 | vfp_current_hw_state_address: |
234 | .word vfp_current_hw_state | |
1da177e4 | 235 | |
07f33a03 CM |
236 | .macro tbl_branch, base, tmp, shift |
237 | #ifdef CONFIG_THUMB2_KERNEL | |
238 | adr \tmp, 1f | |
239 | add \tmp, \tmp, \base, lsl \shift | |
240 | mov pc, \tmp | |
241 | #else | |
242 | add pc, pc, \base, lsl \shift | |
1da177e4 | 243 | mov r0, r0 |
07f33a03 CM |
244 | #endif |
245 | 1: | |
246 | .endm | |
247 | ||
248 | ENTRY(vfp_get_float) | |
249 | tbl_branch r0, r3, #3 | |
1da177e4 | 250 | .irp dr,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15 |
07f33a03 | 251 | 1: mrc p10, 0, r0, c\dr, c0, 0 @ fmrs r0, s0 |
1da177e4 | 252 | mov pc, lr |
07f33a03 CM |
253 | .org 1b + 8 |
254 | 1: mrc p10, 0, r0, c\dr, c0, 4 @ fmrs r0, s1 | |
1da177e4 | 255 | mov pc, lr |
07f33a03 | 256 | .org 1b + 8 |
1da177e4 | 257 | .endr |
93ed3970 | 258 | ENDPROC(vfp_get_float) |
1da177e4 | 259 | |
93ed3970 | 260 | ENTRY(vfp_put_float) |
07f33a03 | 261 | tbl_branch r1, r3, #3 |
1da177e4 | 262 | .irp dr,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15 |
07f33a03 | 263 | 1: mcr p10, 0, r0, c\dr, c0, 0 @ fmsr r0, s0 |
1da177e4 | 264 | mov pc, lr |
07f33a03 CM |
265 | .org 1b + 8 |
266 | 1: mcr p10, 0, r0, c\dr, c0, 4 @ fmsr r0, s1 | |
1da177e4 | 267 | mov pc, lr |
07f33a03 | 268 | .org 1b + 8 |
1da177e4 | 269 | .endr |
93ed3970 | 270 | ENDPROC(vfp_put_float) |
1da177e4 | 271 | |
93ed3970 | 272 | ENTRY(vfp_get_double) |
07f33a03 | 273 | tbl_branch r0, r3, #3 |
1da177e4 | 274 | .irp dr,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15 |
07f33a03 | 275 | 1: fmrrd r0, r1, d\dr |
1da177e4 | 276 | mov pc, lr |
07f33a03 | 277 | .org 1b + 8 |
1da177e4 | 278 | .endr |
25ebee02 CM |
279 | #ifdef CONFIG_VFPv3 |
280 | @ d16 - d31 registers | |
281 | .irp dr,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15 | |
07f33a03 | 282 | 1: mrrc p11, 3, r0, r1, c\dr @ fmrrd r0, r1, d\dr |
25ebee02 | 283 | mov pc, lr |
07f33a03 | 284 | .org 1b + 8 |
25ebee02 CM |
285 | .endr |
286 | #endif | |
1da177e4 | 287 | |
25ebee02 | 288 | @ virtual register 16 (or 32 if VFPv3) for compare with zero |
1da177e4 LT |
289 | mov r0, #0 |
290 | mov r1, #0 | |
291 | mov pc, lr | |
93ed3970 | 292 | ENDPROC(vfp_get_double) |
1da177e4 | 293 | |
93ed3970 | 294 | ENTRY(vfp_put_double) |
07f33a03 | 295 | tbl_branch r2, r3, #3 |
1da177e4 | 296 | .irp dr,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15 |
07f33a03 | 297 | 1: fmdrr d\dr, r0, r1 |
1da177e4 | 298 | mov pc, lr |
07f33a03 | 299 | .org 1b + 8 |
1da177e4 | 300 | .endr |
25ebee02 CM |
301 | #ifdef CONFIG_VFPv3 |
302 | @ d16 - d31 registers | |
303 | .irp dr,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15 | |
138de1c4 | 304 | 1: mcrr p11, 3, r0, r1, c\dr @ fmdrr r0, r1, d\dr |
25ebee02 | 305 | mov pc, lr |
07f33a03 | 306 | .org 1b + 8 |
25ebee02 CM |
307 | .endr |
308 | #endif | |
93ed3970 | 309 | ENDPROC(vfp_put_double) |