Commit | Line | Data |
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1da177e4 LT |
1 | /* |
2 | * linux/arch/arm/vfp/vfpmodule.c | |
3 | * | |
4 | * Copyright (C) 2004 ARM Limited. | |
5 | * Written by Deep Blue Solutions Limited. | |
6 | * | |
7 | * This program is free software; you can redistribute it and/or modify | |
8 | * it under the terms of the GNU General Public License version 2 as | |
9 | * published by the Free Software Foundation. | |
10 | */ | |
1da177e4 | 11 | #include <linux/types.h> |
90b44199 | 12 | #include <linux/cpu.h> |
746a9d19 | 13 | #include <linux/cpu_pm.h> |
998de4ac | 14 | #include <linux/hardirq.h> |
1da177e4 | 15 | #include <linux/kernel.h> |
90b44199 | 16 | #include <linux/notifier.h> |
1da177e4 LT |
17 | #include <linux/signal.h> |
18 | #include <linux/sched.h> | |
90b44199 | 19 | #include <linux/smp.h> |
1da177e4 | 20 | #include <linux/init.h> |
2498814f WD |
21 | #include <linux/uaccess.h> |
22 | #include <linux/user.h> | |
73c132c1 | 23 | #include <linux/export.h> |
d6551e88 | 24 | |
15d07dc9 | 25 | #include <asm/cp15.h> |
5aaf2544 | 26 | #include <asm/cputype.h> |
9f97da78 | 27 | #include <asm/system_info.h> |
d6551e88 | 28 | #include <asm/thread_notify.h> |
1da177e4 LT |
29 | #include <asm/vfp.h> |
30 | ||
31 | #include "vfpinstr.h" | |
32 | #include "vfp.h" | |
33 | ||
34 | /* | |
35 | * Our undef handlers (in entry.S) | |
36 | */ | |
37 | void vfp_testing_entry(void); | |
38 | void vfp_support_entry(void); | |
5d4cae5f | 39 | void vfp_null_entry(void); |
1da177e4 | 40 | |
5d4cae5f | 41 | void (*vfp_vector)(void) = vfp_null_entry; |
af61bdf0 | 42 | |
f8f2a852 RK |
43 | /* |
44 | * Dual-use variable. | |
45 | * Used in startup: set to non-zero if VFP checks fail | |
46 | * After startup, holds VFP architecture | |
47 | */ | |
48 | unsigned int VFP_arch; | |
49 | ||
af61bdf0 RK |
50 | /* |
51 | * The pointer to the vfpstate structure of the thread which currently | |
52 | * owns the context held in the VFP hardware, or NULL if the hardware | |
53 | * context is invalid. | |
f8f2a852 RK |
54 | * |
55 | * For UP, this is sufficient to tell which thread owns the VFP context. | |
56 | * However, for SMP, we also need to check the CPU number stored in the | |
57 | * saved state too to catch migrations. | |
af61bdf0 RK |
58 | */ |
59 | union vfp_state *vfp_current_hw_state[NR_CPUS]; | |
1da177e4 LT |
60 | |
61 | /* | |
f8f2a852 RK |
62 | * Is 'thread's most up to date state stored in this CPUs hardware? |
63 | * Must be called from non-preemptible context. | |
1da177e4 | 64 | */ |
f8f2a852 RK |
65 | static bool vfp_state_in_hw(unsigned int cpu, struct thread_info *thread) |
66 | { | |
67 | #ifdef CONFIG_SMP | |
68 | if (thread->vfpstate.hard.cpu != cpu) | |
69 | return false; | |
70 | #endif | |
71 | return vfp_current_hw_state[cpu] == &thread->vfpstate; | |
72 | } | |
73 | ||
74 | /* | |
75 | * Force a reload of the VFP context from the thread structure. We do | |
76 | * this by ensuring that access to the VFP hardware is disabled, and | |
48af9fea | 77 | * clear vfp_current_hw_state. Must be called from non-preemptible context. |
f8f2a852 RK |
78 | */ |
79 | static void vfp_force_reload(unsigned int cpu, struct thread_info *thread) | |
80 | { | |
81 | if (vfp_state_in_hw(cpu, thread)) { | |
82 | fmxr(FPEXC, fmrx(FPEXC) & ~FPEXC_EN); | |
83 | vfp_current_hw_state[cpu] = NULL; | |
84 | } | |
85 | #ifdef CONFIG_SMP | |
86 | thread->vfpstate.hard.cpu = NR_CPUS; | |
87 | #endif | |
88 | } | |
1da177e4 | 89 | |
0d782dc4 RK |
90 | /* |
91 | * Per-thread VFP initialization. | |
92 | */ | |
93 | static void vfp_thread_flush(struct thread_info *thread) | |
94 | { | |
95 | union vfp_state *vfp = &thread->vfpstate; | |
96 | unsigned int cpu; | |
97 | ||
0d782dc4 RK |
98 | /* |
99 | * Disable VFP to ensure we initialize it first. We must ensure | |
19dad35f RK |
100 | * that the modification of vfp_current_hw_state[] and hardware |
101 | * disable are done for the same CPU and without preemption. | |
102 | * | |
103 | * Do this first to ensure that preemption won't overwrite our | |
104 | * state saving should access to the VFP be enabled at this point. | |
0d782dc4 RK |
105 | */ |
106 | cpu = get_cpu(); | |
af61bdf0 RK |
107 | if (vfp_current_hw_state[cpu] == vfp) |
108 | vfp_current_hw_state[cpu] = NULL; | |
0d782dc4 RK |
109 | fmxr(FPEXC, fmrx(FPEXC) & ~FPEXC_EN); |
110 | put_cpu(); | |
19dad35f RK |
111 | |
112 | memset(vfp, 0, sizeof(union vfp_state)); | |
113 | ||
114 | vfp->hard.fpexc = FPEXC_EN; | |
115 | vfp->hard.fpscr = FPSCR_ROUND_NEAREST; | |
116 | #ifdef CONFIG_SMP | |
117 | vfp->hard.cpu = NR_CPUS; | |
118 | #endif | |
0d782dc4 RK |
119 | } |
120 | ||
797245f5 | 121 | static void vfp_thread_exit(struct thread_info *thread) |
0d782dc4 RK |
122 | { |
123 | /* release case: Per-thread VFP cleanup. */ | |
124 | union vfp_state *vfp = &thread->vfpstate; | |
797245f5 | 125 | unsigned int cpu = get_cpu(); |
0d782dc4 | 126 | |
af61bdf0 RK |
127 | if (vfp_current_hw_state[cpu] == vfp) |
128 | vfp_current_hw_state[cpu] = NULL; | |
797245f5 | 129 | put_cpu(); |
0d782dc4 RK |
130 | } |
131 | ||
c98c0977 CM |
132 | static void vfp_thread_copy(struct thread_info *thread) |
133 | { | |
134 | struct thread_info *parent = current_thread_info(); | |
135 | ||
136 | vfp_sync_hwstate(parent); | |
137 | thread->vfpstate = parent->vfpstate; | |
f8f2a852 RK |
138 | #ifdef CONFIG_SMP |
139 | thread->vfpstate.hard.cpu = NR_CPUS; | |
140 | #endif | |
c98c0977 CM |
141 | } |
142 | ||
0d782dc4 RK |
143 | /* |
144 | * When this function is called with the following 'cmd's, the following | |
145 | * is true while this function is being run: | |
146 | * THREAD_NOFTIFY_SWTICH: | |
147 | * - the previously running thread will not be scheduled onto another CPU. | |
148 | * - the next thread to be run (v) will not be running on another CPU. | |
149 | * - thread->cpu is the local CPU number | |
150 | * - not preemptible as we're called in the middle of a thread switch | |
151 | * THREAD_NOTIFY_FLUSH: | |
152 | * - the thread (v) will be running on the local CPU, so | |
153 | * v === current_thread_info() | |
154 | * - thread->cpu is the local CPU number at the time it is accessed, | |
155 | * but may change at any time. | |
156 | * - we could be preempted if tree preempt rcu is enabled, so | |
157 | * it is unsafe to use thread->cpu. | |
797245f5 RK |
158 | * THREAD_NOTIFY_EXIT |
159 | * - the thread (v) will be running on the local CPU, so | |
160 | * v === current_thread_info() | |
161 | * - thread->cpu is the local CPU number at the time it is accessed, | |
162 | * but may change at any time. | |
163 | * - we could be preempted if tree preempt rcu is enabled, so | |
164 | * it is unsafe to use thread->cpu. | |
0d782dc4 | 165 | */ |
d6551e88 | 166 | static int vfp_notifier(struct notifier_block *self, unsigned long cmd, void *v) |
1da177e4 | 167 | { |
d6551e88 | 168 | struct thread_info *thread = v; |
2e82669a CM |
169 | u32 fpexc; |
170 | #ifdef CONFIG_SMP | |
171 | unsigned int cpu; | |
172 | #endif | |
1da177e4 | 173 | |
2e82669a CM |
174 | switch (cmd) { |
175 | case THREAD_NOTIFY_SWITCH: | |
176 | fpexc = fmrx(FPEXC); | |
c6428464 CM |
177 | |
178 | #ifdef CONFIG_SMP | |
2e82669a | 179 | cpu = thread->cpu; |
0d782dc4 | 180 | |
c6428464 CM |
181 | /* |
182 | * On SMP, if VFP is enabled, save the old state in | |
183 | * case the thread migrates to a different CPU. The | |
184 | * restoring is done lazily. | |
185 | */ | |
f8f2a852 | 186 | if ((fpexc & FPEXC_EN) && vfp_current_hw_state[cpu]) |
af61bdf0 | 187 | vfp_save_state(vfp_current_hw_state[cpu], fpexc); |
c6428464 CM |
188 | #endif |
189 | ||
681a4991 RK |
190 | /* |
191 | * Always disable VFP so we can lazily save/restore the | |
192 | * old state. | |
193 | */ | |
228adef1 | 194 | fmxr(FPEXC, fpexc & ~FPEXC_EN); |
2e82669a | 195 | break; |
681a4991 | 196 | |
2e82669a | 197 | case THREAD_NOTIFY_FLUSH: |
0d782dc4 | 198 | vfp_thread_flush(thread); |
2e82669a CM |
199 | break; |
200 | ||
201 | case THREAD_NOTIFY_EXIT: | |
797245f5 | 202 | vfp_thread_exit(thread); |
c98c0977 CM |
203 | break; |
204 | ||
205 | case THREAD_NOTIFY_COPY: | |
206 | vfp_thread_copy(thread); | |
2e82669a CM |
207 | break; |
208 | } | |
681a4991 | 209 | |
d6551e88 | 210 | return NOTIFY_DONE; |
1da177e4 LT |
211 | } |
212 | ||
d6551e88 RK |
213 | static struct notifier_block vfp_notifier_block = { |
214 | .notifier_call = vfp_notifier, | |
215 | }; | |
216 | ||
1da177e4 LT |
217 | /* |
218 | * Raise a SIGFPE for the current process. | |
219 | * sicode describes the signal being raised. | |
220 | */ | |
2bbd7e9b | 221 | static void vfp_raise_sigfpe(unsigned int sicode, struct pt_regs *regs) |
1da177e4 LT |
222 | { |
223 | siginfo_t info; | |
224 | ||
225 | memset(&info, 0, sizeof(info)); | |
226 | ||
227 | info.si_signo = SIGFPE; | |
228 | info.si_code = sicode; | |
35d59fc5 | 229 | info.si_addr = (void __user *)(instruction_pointer(regs) - 4); |
1da177e4 LT |
230 | |
231 | /* | |
232 | * This is the same as NWFPE, because it's not clear what | |
233 | * this is used for | |
234 | */ | |
235 | current->thread.error_code = 0; | |
236 | current->thread.trap_no = 6; | |
237 | ||
da41119a | 238 | send_sig_info(SIGFPE, &info, current); |
1da177e4 LT |
239 | } |
240 | ||
c98929c0 | 241 | static void vfp_panic(char *reason, u32 inst) |
1da177e4 LT |
242 | { |
243 | int i; | |
244 | ||
dc457078 NP |
245 | pr_err("VFP: Error: %s\n", reason); |
246 | pr_err("VFP: EXC 0x%08x SCR 0x%08x INST 0x%08x\n", | |
c98929c0 | 247 | fmrx(FPEXC), fmrx(FPSCR), inst); |
1da177e4 | 248 | for (i = 0; i < 32; i += 2) |
dc457078 | 249 | pr_err("VFP: s%2u: 0x%08x s%2u: 0x%08x\n", |
1da177e4 LT |
250 | i, vfp_get_float(i), i+1, vfp_get_float(i+1)); |
251 | } | |
252 | ||
253 | /* | |
254 | * Process bitmask of exception conditions. | |
255 | */ | |
256 | static void vfp_raise_exceptions(u32 exceptions, u32 inst, u32 fpscr, struct pt_regs *regs) | |
257 | { | |
258 | int si_code = 0; | |
259 | ||
260 | pr_debug("VFP: raising exceptions %08x\n", exceptions); | |
261 | ||
7c6f2514 | 262 | if (exceptions == VFP_EXCEPTION_ERROR) { |
c98929c0 | 263 | vfp_panic("unhandled bounce", inst); |
1da177e4 LT |
264 | vfp_raise_sigfpe(0, regs); |
265 | return; | |
266 | } | |
267 | ||
268 | /* | |
dbead405 | 269 | * If any of the status flags are set, update the FPSCR. |
1da177e4 LT |
270 | * Comparison instructions always return at least one of |
271 | * these flags set. | |
272 | */ | |
dbead405 CM |
273 | if (exceptions & (FPSCR_N|FPSCR_Z|FPSCR_C|FPSCR_V)) |
274 | fpscr &= ~(FPSCR_N|FPSCR_Z|FPSCR_C|FPSCR_V); | |
275 | ||
1da177e4 LT |
276 | fpscr |= exceptions; |
277 | ||
278 | fmxr(FPSCR, fpscr); | |
279 | ||
280 | #define RAISE(stat,en,sig) \ | |
281 | if (exceptions & stat && fpscr & en) \ | |
282 | si_code = sig; | |
283 | ||
284 | /* | |
285 | * These are arranged in priority order, least to highest. | |
286 | */ | |
e0f205d9 | 287 | RAISE(FPSCR_DZC, FPSCR_DZE, FPE_FLTDIV); |
1da177e4 LT |
288 | RAISE(FPSCR_IXC, FPSCR_IXE, FPE_FLTRES); |
289 | RAISE(FPSCR_UFC, FPSCR_UFE, FPE_FLTUND); | |
290 | RAISE(FPSCR_OFC, FPSCR_OFE, FPE_FLTOVF); | |
291 | RAISE(FPSCR_IOC, FPSCR_IOE, FPE_FLTINV); | |
292 | ||
293 | if (si_code) | |
294 | vfp_raise_sigfpe(si_code, regs); | |
295 | } | |
296 | ||
297 | /* | |
298 | * Emulate a VFP instruction. | |
299 | */ | |
300 | static u32 vfp_emulate_instruction(u32 inst, u32 fpscr, struct pt_regs *regs) | |
301 | { | |
7c6f2514 | 302 | u32 exceptions = VFP_EXCEPTION_ERROR; |
1da177e4 LT |
303 | |
304 | pr_debug("VFP: emulate: INST=0x%08x SCR=0x%08x\n", inst, fpscr); | |
305 | ||
306 | if (INST_CPRTDO(inst)) { | |
307 | if (!INST_CPRT(inst)) { | |
308 | /* | |
309 | * CPDO | |
310 | */ | |
311 | if (vfp_single(inst)) { | |
312 | exceptions = vfp_single_cpdo(inst, fpscr); | |
313 | } else { | |
314 | exceptions = vfp_double_cpdo(inst, fpscr); | |
315 | } | |
316 | } else { | |
317 | /* | |
318 | * A CPRT instruction can not appear in FPINST2, nor | |
319 | * can it cause an exception. Therefore, we do not | |
320 | * have to emulate it. | |
321 | */ | |
322 | } | |
323 | } else { | |
324 | /* | |
325 | * A CPDT instruction can not appear in FPINST2, nor can | |
326 | * it cause an exception. Therefore, we do not have to | |
327 | * emulate it. | |
328 | */ | |
329 | } | |
928bd1b4 | 330 | return exceptions & ~VFP_NAN_FLAG; |
1da177e4 LT |
331 | } |
332 | ||
333 | /* | |
334 | * Package up a bounce condition. | |
335 | */ | |
c98929c0 | 336 | void VFP_bounce(u32 trigger, u32 fpexc, struct pt_regs *regs) |
1da177e4 | 337 | { |
c98929c0 | 338 | u32 fpscr, orig_fpscr, fpsid, exceptions; |
1da177e4 LT |
339 | |
340 | pr_debug("VFP: bounce: trigger %08x fpexc %08x\n", trigger, fpexc); | |
341 | ||
342 | /* | |
c98929c0 CM |
343 | * At this point, FPEXC can have the following configuration: |
344 | * | |
345 | * EX DEX IXE | |
346 | * 0 1 x - synchronous exception | |
347 | * 1 x 0 - asynchronous exception | |
348 | * 1 x 1 - sychronous on VFP subarch 1 and asynchronous on later | |
349 | * 0 0 1 - synchronous on VFP9 (non-standard subarch 1 | |
350 | * implementation), undefined otherwise | |
351 | * | |
352 | * Clear various bits and enable access to the VFP so we can | |
353 | * handle the bounce. | |
1da177e4 | 354 | */ |
c98929c0 | 355 | fmxr(FPEXC, fpexc & ~(FPEXC_EX|FPEXC_DEX|FPEXC_FP2V|FPEXC_VV|FPEXC_TRAP_MASK)); |
1da177e4 | 356 | |
c98929c0 | 357 | fpsid = fmrx(FPSID); |
1da177e4 LT |
358 | orig_fpscr = fpscr = fmrx(FPSCR); |
359 | ||
360 | /* | |
c98929c0 | 361 | * Check for the special VFP subarch 1 and FPSCR.IXE bit case |
1da177e4 | 362 | */ |
c98929c0 CM |
363 | if ((fpsid & FPSID_ARCH_MASK) == (1 << FPSID_ARCH_BIT) |
364 | && (fpscr & FPSCR_IXE)) { | |
365 | /* | |
366 | * Synchronous exception, emulate the trigger instruction | |
367 | */ | |
1da177e4 LT |
368 | goto emulate; |
369 | } | |
370 | ||
c98929c0 | 371 | if (fpexc & FPEXC_EX) { |
85d6943a | 372 | #ifndef CONFIG_CPU_FEROCEON |
c98929c0 CM |
373 | /* |
374 | * Asynchronous exception. The instruction is read from FPINST | |
375 | * and the interrupted instruction has to be restarted. | |
376 | */ | |
377 | trigger = fmrx(FPINST); | |
378 | regs->ARM_pc -= 4; | |
85d6943a | 379 | #endif |
c98929c0 CM |
380 | } else if (!(fpexc & FPEXC_DEX)) { |
381 | /* | |
382 | * Illegal combination of bits. It can be caused by an | |
383 | * unallocated VFP instruction but with FPSCR.IXE set and not | |
384 | * on VFP subarch 1. | |
385 | */ | |
386 | vfp_raise_exceptions(VFP_EXCEPTION_ERROR, trigger, fpscr, regs); | |
f2255be8 | 387 | goto exit; |
c98929c0 | 388 | } |
1da177e4 LT |
389 | |
390 | /* | |
c98929c0 CM |
391 | * Modify fpscr to indicate the number of iterations remaining. |
392 | * If FPEXC.EX is 0, FPEXC.DEX is 1 and the FPEXC.VV bit indicates | |
393 | * whether FPEXC.VECITR or FPSCR.LEN is used. | |
1da177e4 | 394 | */ |
c98929c0 | 395 | if (fpexc & (FPEXC_EX | FPEXC_VV)) { |
1da177e4 LT |
396 | u32 len; |
397 | ||
398 | len = fpexc + (1 << FPEXC_LENGTH_BIT); | |
399 | ||
400 | fpscr &= ~FPSCR_LENGTH_MASK; | |
401 | fpscr |= (len & FPEXC_LENGTH_MASK) << (FPSCR_LENGTH_BIT - FPEXC_LENGTH_BIT); | |
402 | } | |
403 | ||
404 | /* | |
405 | * Handle the first FP instruction. We used to take note of the | |
406 | * FPEXC bounce reason, but this appears to be unreliable. | |
407 | * Emulate the bounced instruction instead. | |
408 | */ | |
c98929c0 | 409 | exceptions = vfp_emulate_instruction(trigger, fpscr, regs); |
1da177e4 | 410 | if (exceptions) |
c98929c0 | 411 | vfp_raise_exceptions(exceptions, trigger, orig_fpscr, regs); |
1da177e4 LT |
412 | |
413 | /* | |
c98929c0 CM |
414 | * If there isn't a second FP instruction, exit now. Note that |
415 | * the FPEXC.FP2V bit is valid only if FPEXC.EX is 1. | |
1da177e4 | 416 | */ |
5e4ba617 | 417 | if ((fpexc & (FPEXC_EX | FPEXC_FP2V)) != (FPEXC_EX | FPEXC_FP2V)) |
f2255be8 | 418 | goto exit; |
1da177e4 LT |
419 | |
420 | /* | |
421 | * The barrier() here prevents fpinst2 being read | |
422 | * before the condition above. | |
423 | */ | |
424 | barrier(); | |
425 | trigger = fmrx(FPINST2); | |
1da177e4 LT |
426 | |
427 | emulate: | |
c98929c0 | 428 | exceptions = vfp_emulate_instruction(trigger, orig_fpscr, regs); |
1da177e4 LT |
429 | if (exceptions) |
430 | vfp_raise_exceptions(exceptions, trigger, orig_fpscr, regs); | |
f2255be8 GD |
431 | exit: |
432 | preempt_enable(); | |
1da177e4 | 433 | } |
efe90d27 | 434 | |
8e140362 RK |
435 | static void vfp_enable(void *unused) |
436 | { | |
998de4ac WD |
437 | u32 access; |
438 | ||
439 | BUG_ON(preemptible()); | |
440 | access = get_copro_access(); | |
8e140362 RK |
441 | |
442 | /* | |
443 | * Enable full access to VFP (cp10 and cp11) | |
444 | */ | |
445 | set_copro_access(access | CPACC_FULL(10) | CPACC_FULL(11)); | |
446 | } | |
447 | ||
7d7d7a41 FF |
448 | /* Called by platforms on which we want to disable VFP because it may not be |
449 | * present on all CPUs within a SMP complex. Needs to be called prior to | |
450 | * vfp_init(). | |
451 | */ | |
452 | void vfp_disable(void) | |
453 | { | |
454 | if (VFP_arch) { | |
455 | pr_debug("%s: should be called prior to vfp_init\n", __func__); | |
456 | return; | |
457 | } | |
458 | VFP_arch = 1; | |
459 | } | |
460 | ||
746a9d19 | 461 | #ifdef CONFIG_CPU_PM |
328f5cc3 | 462 | static int vfp_pm_suspend(void) |
fc0b7a20 BD |
463 | { |
464 | struct thread_info *ti = current_thread_info(); | |
465 | u32 fpexc = fmrx(FPEXC); | |
466 | ||
467 | /* if vfp is on, then save state for resumption */ | |
468 | if (fpexc & FPEXC_EN) { | |
dc457078 | 469 | pr_debug("%s: saving vfp state\n", __func__); |
fc0b7a20 BD |
470 | vfp_save_state(&ti->vfpstate, fpexc); |
471 | ||
472 | /* disable, just in case */ | |
473 | fmxr(FPEXC, fmrx(FPEXC) & ~FPEXC_EN); | |
24b35521 CC |
474 | } else if (vfp_current_hw_state[ti->cpu]) { |
475 | #ifndef CONFIG_SMP | |
476 | fmxr(FPEXC, fpexc | FPEXC_EN); | |
477 | vfp_save_state(vfp_current_hw_state[ti->cpu], fpexc); | |
478 | fmxr(FPEXC, fpexc); | |
479 | #endif | |
fc0b7a20 BD |
480 | } |
481 | ||
482 | /* clear any information we had about last context state */ | |
a84b895a | 483 | vfp_current_hw_state[ti->cpu] = NULL; |
fc0b7a20 BD |
484 | |
485 | return 0; | |
486 | } | |
487 | ||
328f5cc3 | 488 | static void vfp_pm_resume(void) |
fc0b7a20 BD |
489 | { |
490 | /* ensure we have access to the vfp */ | |
491 | vfp_enable(NULL); | |
492 | ||
493 | /* and disable it to ensure the next usage restores the state */ | |
494 | fmxr(FPEXC, fmrx(FPEXC) & ~FPEXC_EN); | |
fc0b7a20 BD |
495 | } |
496 | ||
746a9d19 CC |
497 | static int vfp_cpu_pm_notifier(struct notifier_block *self, unsigned long cmd, |
498 | void *v) | |
499 | { | |
500 | switch (cmd) { | |
501 | case CPU_PM_ENTER: | |
502 | vfp_pm_suspend(); | |
503 | break; | |
504 | case CPU_PM_ENTER_FAILED: | |
505 | case CPU_PM_EXIT: | |
506 | vfp_pm_resume(); | |
507 | break; | |
508 | } | |
509 | return NOTIFY_OK; | |
510 | } | |
511 | ||
512 | static struct notifier_block vfp_cpu_pm_notifier_block = { | |
513 | .notifier_call = vfp_cpu_pm_notifier, | |
fc0b7a20 BD |
514 | }; |
515 | ||
fc0b7a20 BD |
516 | static void vfp_pm_init(void) |
517 | { | |
746a9d19 | 518 | cpu_pm_register_notifier(&vfp_cpu_pm_notifier_block); |
fc0b7a20 BD |
519 | } |
520 | ||
fc0b7a20 BD |
521 | #else |
522 | static inline void vfp_pm_init(void) { } | |
746a9d19 | 523 | #endif /* CONFIG_CPU_PM */ |
fc0b7a20 | 524 | |
f8f2a852 RK |
525 | /* |
526 | * Ensure that the VFP state stored in 'thread->vfpstate' is up to date | |
527 | * with the hardware state. | |
528 | */ | |
ad187f95 | 529 | void vfp_sync_hwstate(struct thread_info *thread) |
3d1228ea CM |
530 | { |
531 | unsigned int cpu = get_cpu(); | |
3d1228ea | 532 | |
f8f2a852 | 533 | if (vfp_state_in_hw(cpu, thread)) { |
54cb3dbb | 534 | u32 fpexc = fmrx(FPEXC); |
3d1228ea | 535 | |
54cb3dbb RK |
536 | /* |
537 | * Save the last VFP state on this CPU. | |
538 | */ | |
539 | fmxr(FPEXC, fpexc | FPEXC_EN); | |
540 | vfp_save_state(&thread->vfpstate, fpexc | FPEXC_EN); | |
ad187f95 RK |
541 | fmxr(FPEXC, fpexc); |
542 | } | |
3d1228ea | 543 | |
ad187f95 RK |
544 | put_cpu(); |
545 | } | |
546 | ||
f8f2a852 | 547 | /* Ensure that the thread reloads the hardware VFP state on the next use. */ |
ad187f95 RK |
548 | void vfp_flush_hwstate(struct thread_info *thread) |
549 | { | |
550 | unsigned int cpu = get_cpu(); | |
3d1228ea | 551 | |
f8f2a852 | 552 | vfp_force_reload(cpu, thread); |
ad187f95 | 553 | |
3d1228ea CM |
554 | put_cpu(); |
555 | } | |
3d1228ea | 556 | |
2498814f WD |
557 | /* |
558 | * Save the current VFP state into the provided structures and prepare | |
559 | * for entry into a new function (signal handler). | |
560 | */ | |
561 | int vfp_preserve_user_clear_hwstate(struct user_vfp __user *ufp, | |
562 | struct user_vfp_exc __user *ufp_exc) | |
563 | { | |
564 | struct thread_info *thread = current_thread_info(); | |
565 | struct vfp_hard_struct *hwstate = &thread->vfpstate.hard; | |
566 | int err = 0; | |
567 | ||
568 | /* Ensure that the saved hwstate is up-to-date. */ | |
569 | vfp_sync_hwstate(thread); | |
570 | ||
571 | /* | |
572 | * Copy the floating point registers. There can be unused | |
573 | * registers see asm/hwcap.h for details. | |
574 | */ | |
575 | err |= __copy_to_user(&ufp->fpregs, &hwstate->fpregs, | |
576 | sizeof(hwstate->fpregs)); | |
577 | /* | |
578 | * Copy the status and control register. | |
579 | */ | |
580 | __put_user_error(hwstate->fpscr, &ufp->fpscr, err); | |
581 | ||
582 | /* | |
583 | * Copy the exception registers. | |
584 | */ | |
585 | __put_user_error(hwstate->fpexc, &ufp_exc->fpexc, err); | |
586 | __put_user_error(hwstate->fpinst, &ufp_exc->fpinst, err); | |
587 | __put_user_error(hwstate->fpinst2, &ufp_exc->fpinst2, err); | |
588 | ||
589 | if (err) | |
590 | return -EFAULT; | |
ff9a184c WD |
591 | |
592 | /* Ensure that VFP is disabled. */ | |
593 | vfp_flush_hwstate(thread); | |
594 | ||
595 | /* | |
596 | * As per the PCS, clear the length and stride bits for function | |
597 | * entry. | |
598 | */ | |
599 | hwstate->fpscr &= ~(FPSCR_LENGTH_MASK | FPSCR_STRIDE_MASK); | |
2498814f WD |
600 | return 0; |
601 | } | |
602 | ||
603 | /* Sanitise and restore the current VFP state from the provided structures. */ | |
604 | int vfp_restore_user_hwstate(struct user_vfp __user *ufp, | |
605 | struct user_vfp_exc __user *ufp_exc) | |
606 | { | |
607 | struct thread_info *thread = current_thread_info(); | |
608 | struct vfp_hard_struct *hwstate = &thread->vfpstate.hard; | |
609 | unsigned long fpexc; | |
610 | int err = 0; | |
611 | ||
56cb2484 WD |
612 | /* Disable VFP to avoid corrupting the new thread state. */ |
613 | vfp_flush_hwstate(thread); | |
2498814f WD |
614 | |
615 | /* | |
616 | * Copy the floating point registers. There can be unused | |
617 | * registers see asm/hwcap.h for details. | |
618 | */ | |
619 | err |= __copy_from_user(&hwstate->fpregs, &ufp->fpregs, | |
620 | sizeof(hwstate->fpregs)); | |
621 | /* | |
622 | * Copy the status and control register. | |
623 | */ | |
624 | __get_user_error(hwstate->fpscr, &ufp->fpscr, err); | |
625 | ||
626 | /* | |
627 | * Sanitise and restore the exception registers. | |
628 | */ | |
629 | __get_user_error(fpexc, &ufp_exc->fpexc, err); | |
630 | ||
631 | /* Ensure the VFP is enabled. */ | |
632 | fpexc |= FPEXC_EN; | |
633 | ||
634 | /* Ensure FPINST2 is invalid and the exception flag is cleared. */ | |
635 | fpexc &= ~(FPEXC_EX | FPEXC_FP2V); | |
636 | hwstate->fpexc = fpexc; | |
637 | ||
638 | __get_user_error(hwstate->fpinst, &ufp_exc->fpinst, err); | |
639 | __get_user_error(hwstate->fpinst2, &ufp_exc->fpinst2, err); | |
640 | ||
641 | return err ? -EFAULT : 0; | |
642 | } | |
643 | ||
90b44199 RK |
644 | /* |
645 | * VFP hardware can lose all context when a CPU goes offline. | |
74c25bee RK |
646 | * As we will be running in SMP mode with CPU hotplug, we will save the |
647 | * hardware state at every thread switch. We clear our held state when | |
648 | * a CPU has been killed, indicating that the VFP hardware doesn't contain | |
649 | * a threads VFP state. When a CPU starts up, we re-enable access to the | |
650 | * VFP hardware. | |
90b44199 RK |
651 | * |
652 | * Both CPU_DYING and CPU_STARTING are called on the CPU which | |
653 | * is being offlined/onlined. | |
654 | */ | |
655 | static int vfp_hotplug(struct notifier_block *b, unsigned long action, | |
656 | void *hcpu) | |
657 | { | |
384b38b6 YZ |
658 | if (action == CPU_DYING || action == CPU_DYING_FROZEN) |
659 | vfp_current_hw_state[(long)hcpu] = NULL; | |
660 | else if (action == CPU_STARTING || action == CPU_STARTING_FROZEN) | |
90b44199 RK |
661 | vfp_enable(NULL); |
662 | return NOTIFY_OK; | |
663 | } | |
8e140362 | 664 | |
ab3da156 AB |
665 | void vfp_kmode_exception(void) |
666 | { | |
667 | /* | |
668 | * If we reach this point, a floating point exception has been raised | |
669 | * while running in kernel mode. If the NEON/VFP unit was enabled at the | |
670 | * time, it means a VFP instruction has been issued that requires | |
671 | * software assistance to complete, something which is not currently | |
672 | * supported in kernel mode. | |
673 | * If the NEON/VFP unit was disabled, and the location pointed to below | |
674 | * is properly preceded by a call to kernel_neon_begin(), something has | |
675 | * caused the task to be scheduled out and back in again. In this case, | |
676 | * rebuilding and running with CONFIG_DEBUG_ATOMIC_SLEEP enabled should | |
677 | * be helpful in localizing the problem. | |
678 | */ | |
679 | if (fmrx(FPEXC) & FPEXC_EN) | |
680 | pr_crit("BUG: unsupported FP instruction in kernel mode\n"); | |
681 | else | |
682 | pr_crit("BUG: FP instruction issued in kernel mode with FP unit disabled\n"); | |
683 | } | |
684 | ||
73c132c1 AB |
685 | #ifdef CONFIG_KERNEL_MODE_NEON |
686 | ||
687 | /* | |
688 | * Kernel-side NEON support functions | |
689 | */ | |
690 | void kernel_neon_begin(void) | |
691 | { | |
692 | struct thread_info *thread = current_thread_info(); | |
693 | unsigned int cpu; | |
694 | u32 fpexc; | |
695 | ||
696 | /* | |
697 | * Kernel mode NEON is only allowed outside of interrupt context | |
698 | * with preemption disabled. This will make sure that the kernel | |
699 | * mode NEON register contents never need to be preserved. | |
700 | */ | |
701 | BUG_ON(in_interrupt()); | |
702 | cpu = get_cpu(); | |
703 | ||
704 | fpexc = fmrx(FPEXC) | FPEXC_EN; | |
705 | fmxr(FPEXC, fpexc); | |
706 | ||
707 | /* | |
708 | * Save the userland NEON/VFP state. Under UP, | |
709 | * the owner could be a task other than 'current' | |
710 | */ | |
711 | if (vfp_state_in_hw(cpu, thread)) | |
712 | vfp_save_state(&thread->vfpstate, fpexc); | |
713 | #ifndef CONFIG_SMP | |
714 | else if (vfp_current_hw_state[cpu] != NULL) | |
715 | vfp_save_state(vfp_current_hw_state[cpu], fpexc); | |
716 | #endif | |
717 | vfp_current_hw_state[cpu] = NULL; | |
718 | } | |
719 | EXPORT_SYMBOL(kernel_neon_begin); | |
720 | ||
721 | void kernel_neon_end(void) | |
722 | { | |
723 | /* Disable the NEON/VFP unit. */ | |
724 | fmxr(FPEXC, fmrx(FPEXC) & ~FPEXC_EN); | |
725 | put_cpu(); | |
726 | } | |
727 | EXPORT_SYMBOL(kernel_neon_end); | |
728 | ||
729 | #endif /* CONFIG_KERNEL_MODE_NEON */ | |
730 | ||
1da177e4 LT |
731 | /* |
732 | * VFP support code initialisation. | |
733 | */ | |
734 | static int __init vfp_init(void) | |
735 | { | |
736 | unsigned int vfpsid; | |
efe90d27 | 737 | unsigned int cpu_arch = cpu_architecture(); |
efe90d27 | 738 | |
c98929c0 | 739 | if (cpu_arch >= CPU_ARCH_ARMv6) |
998de4ac | 740 | on_each_cpu(vfp_enable, NULL, 1); |
1da177e4 LT |
741 | |
742 | /* | |
743 | * First check that there is a VFP that we can use. | |
744 | * The handler is already setup to just log calls, so | |
745 | * we just need to read the VFPSID register. | |
746 | */ | |
5d4cae5f | 747 | vfp_vector = vfp_testing_entry; |
b9338a78 | 748 | barrier(); |
1da177e4 | 749 | vfpsid = fmrx(FPSID); |
8e140362 | 750 | barrier(); |
5d4cae5f | 751 | vfp_vector = vfp_null_entry; |
1da177e4 | 752 | |
dc457078 | 753 | pr_info("VFP support v0.3: "); |
6c96a4a6 | 754 | if (VFP_arch) { |
dc457078 | 755 | pr_cont("not present\n"); |
6c96a4a6 SB |
756 | return 0; |
757 | /* Extract the architecture on CPUID scheme */ | |
758 | } else if ((read_cpuid_id() & 0x000f0000) == 0x000f0000) { | |
759 | VFP_arch = vfpsid & FPSID_CPUID_ARCH_MASK; | |
760 | VFP_arch >>= FPSID_ARCH_BIT; | |
efe90d27 | 761 | /* |
6c96a4a6 SB |
762 | * Check for the presence of the Advanced SIMD |
763 | * load/store instructions, integer and single | |
764 | * precision floating point operations. Only check | |
765 | * for NEON if the hardware has the MVFR registers. | |
efe90d27 | 766 | */ |
2b94fe2a SB |
767 | if (IS_ENABLED(CONFIG_NEON) && |
768 | (fmrx(MVFR1) & 0x000fff00) == 0x00011100) | |
6c96a4a6 | 769 | elf_hwcap |= HWCAP_NEON; |
6c96a4a6 | 770 | |
2b94fe2a SB |
771 | if (IS_ENABLED(CONFIG_VFPv3)) { |
772 | u32 mvfr0 = fmrx(MVFR0); | |
773 | if (((mvfr0 & MVFR0_DP_MASK) >> MVFR0_DP_BIT) == 0x2 || | |
774 | ((mvfr0 & MVFR0_SP_MASK) >> MVFR0_SP_BIT) == 0x2) { | |
775 | elf_hwcap |= HWCAP_VFPv3; | |
776 | /* | |
777 | * Check for VFPv3 D16 and VFPv4 D16. CPUs in | |
778 | * this configuration only have 16 x 64bit | |
779 | * registers. | |
780 | */ | |
781 | if ((mvfr0 & MVFR0_A_SIMD_MASK) == 1) | |
782 | /* also v4-D16 */ | |
783 | elf_hwcap |= HWCAP_VFPv3D16; | |
784 | else | |
785 | elf_hwcap |= HWCAP_VFPD32; | |
786 | } | |
787 | ||
788 | if ((fmrx(MVFR1) & 0xf0000000) == 0x10000000) | |
789 | elf_hwcap |= HWCAP_VFPv4; | |
790 | } | |
6c96a4a6 SB |
791 | /* Extract the architecture version on pre-cpuid scheme */ |
792 | } else { | |
793 | if (vfpsid & FPSID_NODOUBLE) { | |
794 | pr_cont("no double precision support\n"); | |
795 | return 0; | |
18b9dc13 | 796 | } |
6c96a4a6 SB |
797 | |
798 | VFP_arch = (vfpsid & FPSID_ARCH_MASK) >> FPSID_ARCH_BIT; | |
1da177e4 | 799 | } |
6c96a4a6 SB |
800 | |
801 | hotcpu_notifier(vfp_hotplug, 0); | |
802 | ||
803 | vfp_vector = vfp_support_entry; | |
804 | ||
805 | thread_register_notifier(&vfp_notifier_block); | |
806 | vfp_pm_init(); | |
807 | ||
808 | /* | |
809 | * We detected VFP, and the support code is | |
810 | * in place; report VFP support to userspace. | |
811 | */ | |
812 | elf_hwcap |= HWCAP_VFP; | |
813 | ||
814 | pr_cont("implementor %02x architecture %d part %02x variant %x rev %x\n", | |
815 | (vfpsid & FPSID_IMPLEMENTER_MASK) >> FPSID_IMPLEMENTER_BIT, | |
816 | VFP_arch, | |
817 | (vfpsid & FPSID_PART_MASK) >> FPSID_PART_BIT, | |
818 | (vfpsid & FPSID_VARIANT_MASK) >> FPSID_VARIANT_BIT, | |
819 | (vfpsid & FPSID_REV_MASK) >> FPSID_REV_BIT); | |
820 | ||
1da177e4 LT |
821 | return 0; |
822 | } | |
823 | ||
0773d73d | 824 | core_initcall(vfp_init); |