[deliverable/linux.git] / arch / arm / vfp / vfpmodule.c

/*
 *  linux/arch/arm/vfp/vfpmodule.c
 *
 *  Copyright (C) 2004 ARM Limited.
 *  Written by Deep Blue Solutions Limited.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */
#include <linux/module.h>
#include <linux/types.h>
#include <linux/kernel.h>
#include <linux/signal.h>
#include <linux/sched.h>
#include <linux/init.h>

#include <asm/thread_notify.h>
#include <asm/vfp.h>

#include "vfpinstr.h"
#include "vfp.h"

/*
 * Our undef handlers (in entry.S)
 */
void vfp_testing_entry(void);
void vfp_support_entry(void);
void vfp_null_entry(void);

void (*vfp_vector)(void) = vfp_null_entry;
union vfp_state *last_VFP_context[NR_CPUS];

/*
 * Dual-use variable.
 * Used in startup: set to non-zero if VFP checks fail
 * After startup, holds VFP architecture
 */
unsigned int VFP_arch;

static int vfp_notifier(struct notifier_block *self, unsigned long cmd, void *v)
{
	struct thread_info *thread = v;
	union vfp_state *vfp;
	__u32 cpu = thread->cpu;

	if (likely(cmd == THREAD_NOTIFY_SWITCH)) {
		u32 fpexc = fmrx(FPEXC);

#ifdef CONFIG_SMP
		/*
		 * On SMP, if VFP is enabled, save the old state in
		 * case the thread migrates to a different CPU. The
		 * restoring is done lazily.
		 */
		if ((fpexc & FPEXC_EN) && last_VFP_context[cpu]) {
			vfp_save_state(last_VFP_context[cpu], fpexc);
			last_VFP_context[cpu]->hard.cpu = cpu;
		}
		/*
		 * Thread migration, just force the reloading of the
		 * state on the new CPU in case the VFP registers
		 * contain stale data.
		 */
		if (thread->vfpstate.hard.cpu != cpu)
			last_VFP_context[cpu] = NULL;
#endif

		/*
		 * Always disable VFP so we can lazily save/restore the
		 * old state.
		 */
		fmxr(FPEXC, fpexc & ~FPEXC_EN);
		return NOTIFY_DONE;
	}

	vfp = &thread->vfpstate;
	if (cmd == THREAD_NOTIFY_FLUSH) {
		/*
		 * Per-thread VFP initialisation.
		 */
		memset(vfp, 0, sizeof(union vfp_state));

		vfp->hard.fpexc = FPEXC_EN;
		vfp->hard.fpscr = FPSCR_ROUND_NEAREST;

		/*
		 * Disable VFP to ensure we initialise it first.
		 */
		fmxr(FPEXC, fmrx(FPEXC) & ~FPEXC_EN);
	}

	/* flush and release case: Per-thread VFP cleanup. */
	if (last_VFP_context[cpu] == vfp)
		last_VFP_context[cpu] = NULL;

	return NOTIFY_DONE;
}

static struct notifier_block vfp_notifier_block = {
	.notifier_call	= vfp_notifier,
};

/*
 * Raise a SIGFPE for the current process.
 * sicode describes the signal being raised.
 */
void vfp_raise_sigfpe(unsigned int sicode, struct pt_regs *regs)
{
	siginfo_t info;

	memset(&info, 0, sizeof(info));

	info.si_signo = SIGFPE;
	info.si_code = sicode;
	info.si_addr = (void __user *)(instruction_pointer(regs) - 4);

	/*
	 * This is the same as NWFPE, because it's not clear what
	 * this is used for
	 */
	current->thread.error_code = 0;
	current->thread.trap_no = 6;

	send_sig_info(SIGFPE, &info, current);
}

static void vfp_panic(char *reason)
{
	int i;

	printk(KERN_ERR "VFP: Error: %s\n", reason);
	printk(KERN_ERR "VFP: EXC 0x%08x SCR 0x%08x INST 0x%08x\n",
		fmrx(FPEXC), fmrx(FPSCR), fmrx(FPINST));
	for (i = 0; i < 32; i += 2)
		printk(KERN_ERR "VFP: s%2u: 0x%08x s%2u: 0x%08x\n",
		       i, vfp_get_float(i), i+1, vfp_get_float(i+1));
}

/*
 * Process bitmask of exception conditions.
 */
static void vfp_raise_exceptions(u32 exceptions, u32 inst, u32 fpscr, struct pt_regs *regs)
{
	int si_code = 0;

	pr_debug("VFP: raising exceptions %08x\n", exceptions);

	if (exceptions == VFP_EXCEPTION_ERROR) {
		vfp_panic("unhandled bounce");
		vfp_raise_sigfpe(0, regs);
		return;
	}

	/*
	 * If any of the status flags are set, update the FPSCR.
	 * Comparison instructions always return at least one of
	 * these flags set.
	 */
	if (exceptions & (FPSCR_N|FPSCR_Z|FPSCR_C|FPSCR_V))
		fpscr &= ~(FPSCR_N|FPSCR_Z|FPSCR_C|FPSCR_V);

	fpscr |= exceptions;

	fmxr(FPSCR, fpscr);

#define RAISE(stat,en,sig)				\
	if (exceptions & stat && fpscr & en)		\
		si_code = sig;

	/*
	 * These are arranged in priority order, least to highest.
	 */
	RAISE(FPSCR_DZC, FPSCR_DZE, FPE_FLTDIV);
	RAISE(FPSCR_IXC, FPSCR_IXE, FPE_FLTRES);
	RAISE(FPSCR_UFC, FPSCR_UFE, FPE_FLTUND);
	RAISE(FPSCR_OFC, FPSCR_OFE, FPE_FLTOVF);
	RAISE(FPSCR_IOC, FPSCR_IOE, FPE_FLTINV);

	if (si_code)
		vfp_raise_sigfpe(si_code, regs);
}

/*
 * Emulate a VFP instruction.
 */
static u32 vfp_emulate_instruction(u32 inst, u32 fpscr, struct pt_regs *regs)
{
	u32 exceptions = VFP_EXCEPTION_ERROR;

	pr_debug("VFP: emulate: INST=0x%08x SCR=0x%08x\n", inst, fpscr);

	if (INST_CPRTDO(inst)) {
		if (!INST_CPRT(inst)) {
			/*
			 * CPDO
			 */
			if (vfp_single(inst)) {
				exceptions = vfp_single_cpdo(inst, fpscr);
			} else {
				exceptions = vfp_double_cpdo(inst, fpscr);
			}
		} else {
			/*
			 * A CPRT instruction can not appear in FPINST2, nor
			 * can it cause an exception.  Therefore, we do not
			 * have to emulate it.
			 */
		}
	} else {
		/*
		 * A CPDT instruction can not appear in FPINST2, nor can
		 * it cause an exception.  Therefore, we do not have to
		 * emulate it.
		 */
	}
	return exceptions & ~VFP_NAN_FLAG;
}

/*
 * Package up a bounce condition.
 */
void VFP9_bounce(u32 trigger, u32 fpexc, struct pt_regs *regs)
{
	u32 fpscr, orig_fpscr, exceptions, inst;

	pr_debug("VFP: bounce: trigger %08x fpexc %08x\n", trigger, fpexc);

	/*
	 * Enable access to the VFP so we can handle the bounce.
	 */
	fmxr(FPEXC, fpexc & ~(FPEXC_EX|FPEXC_INV|FPEXC_UFC|FPEXC_IOC));

	orig_fpscr = fpscr = fmrx(FPSCR);

	/*
	 * If we are running with inexact exceptions enabled, we need to
	 * emulate the trigger instruction.  Note that as we're emulating
	 * the trigger instruction, we need to increment PC.
	 */
	if (fpscr & FPSCR_IXE) {
		regs->ARM_pc += 4;
		goto emulate;
	}

	barrier();

	/*
	 * Modify fpscr to indicate the number of iterations remaining
	 */
	if (fpexc & FPEXC_EX) {
		u32 len;

		len = fpexc + (1 << FPEXC_LENGTH_BIT);

		fpscr &= ~FPSCR_LENGTH_MASK;
		fpscr |= (len & FPEXC_LENGTH_MASK) << (FPSCR_LENGTH_BIT - FPEXC_LENGTH_BIT);
	}

	/*
	 * Handle the first FP instruction.  We used to take note of the
	 * FPEXC bounce reason, but this appears to be unreliable.
	 * Emulate the bounced instruction instead.
	 */
	inst = fmrx(FPINST);
	exceptions = vfp_emulate_instruction(inst, fpscr, regs);
	if (exceptions)
		vfp_raise_exceptions(exceptions, inst, orig_fpscr, regs);

	/*
	 * If there isn't a second FP instruction, exit now.
	 */
	if (!(fpexc & FPEXC_FPV2))
		return;

	/*
	 * The barrier() here prevents fpinst2 being read
	 * before the condition above.
	 */
	barrier();
	trigger = fmrx(FPINST2);
	orig_fpscr = fpscr = fmrx(FPSCR);

 emulate:
	exceptions = vfp_emulate_instruction(trigger, fpscr, regs);
	if (exceptions)
		vfp_raise_exceptions(exceptions, trigger, orig_fpscr, regs);
}

static void vfp_enable(void *unused)
{
	u32 access = get_copro_access();

	/*
	 * Enable full access to VFP (cp10 and cp11)
	 */
	set_copro_access(access | CPACC_FULL(10) | CPACC_FULL(11));
}

#include <linux/smp.h>

/*
 * VFP support code initialisation.
 */
static int __init vfp_init(void)
{
	unsigned int vfpsid;
	unsigned int cpu_arch = cpu_architecture();
	u32 access = 0;

	if (cpu_arch >= CPU_ARCH_ARMv6) {
		access = get_copro_access();

		/*
		 * Enable full access to VFP (cp10 and cp11)
		 */
		set_copro_access(access | CPACC_FULL(10) | CPACC_FULL(11));
	}

	/*
	 * First check that there is a VFP that we can use.
	 * The handler is already setup to just log calls, so
	 * we just need to read the VFPSID register.
	 */
	vfp_vector = vfp_testing_entry;
	vfpsid = fmrx(FPSID);
	barrier();
	vfp_vector = vfp_null_entry;

	printk(KERN_INFO "VFP support v0.3: ");
	if (VFP_arch) {
		printk("not present\n");

		/*
		 * Restore the copro access register.
		 */
		if (cpu_arch >= CPU_ARCH_ARMv6)
			set_copro_access(access);
	} else if (vfpsid & FPSID_NODOUBLE) {
		printk("no double precision support\n");
	} else {
		smp_call_function(vfp_enable, NULL, 1, 1);

		VFP_arch = (vfpsid & FPSID_ARCH_MASK) >> FPSID_ARCH_BIT;  /* Extract the architecture version */
		printk("implementor %02x architecture %d part %02x variant %x rev %x\n",
			(vfpsid & FPSID_IMPLEMENTER_MASK) >> FPSID_IMPLEMENTER_BIT,
			(vfpsid & FPSID_ARCH_MASK) >> FPSID_ARCH_BIT,
			(vfpsid & FPSID_PART_MASK) >> FPSID_PART_BIT,
			(vfpsid & FPSID_VARIANT_MASK) >> FPSID_VARIANT_BIT,
			(vfpsid & FPSID_REV_MASK) >> FPSID_REV_BIT);

		vfp_vector = vfp_support_entry;

		thread_register_notifier(&vfp_notifier_block);

		/*
		 * We detected VFP, and the support code is
		 * in place; report VFP support to userspace.
		 */
		elf_hwcap |= HWCAP_VFP;
	}
	return 0;
}

late_initcall(vfp_init);
Commit	Line	Data
1da177e4 LT	1	/*
	2	* linux/arch/arm/vfp/vfpmodule.c
	3	*
	4	* Copyright (C) 2004 ARM Limited.
	5	* Written by Deep Blue Solutions Limited.
	6	*
	7	* This program is free software; you can redistribute it and/or modify
	8	* it under the terms of the GNU General Public License version 2 as
	9	* published by the Free Software Foundation.
	10	*/
	11	#include <linux/module.h>
1da177e4 LT	12	#include <linux/types.h>
	13	#include <linux/kernel.h>
	14	#include <linux/signal.h>
	15	#include <linux/sched.h>
	16	#include <linux/init.h>
d6551e88 RK	17
d6551e88 RK	18	#include <asm/thread_notify.h>
1da177e4 LT	19	#include <asm/vfp.h>
	20
	21	#include "vfpinstr.h"
	22	#include "vfp.h"
	23
	24	/*
	25	* Our undef handlers (in entry.S)
	26	*/
	27	void vfp_testing_entry(void);
	28	void vfp_support_entry(void);
5d4cae5f	29	void vfp_null_entry(void);
1da177e4	30
5d4cae5f	31	void (*vfp_vector)(void) = vfp_null_entry;
c6428464	32	union vfp_state *last_VFP_context[NR_CPUS];
1da177e4 LT	33
	34	/*
	35	* Dual-use variable.
	36	* Used in startup: set to non-zero if VFP checks fail
	37	* After startup, holds VFP architecture
	38	*/
	39	unsigned int VFP_arch;
	40
d6551e88	41	static int vfp_notifier(struct notifier_block self, unsigned long cmd, void v)
1da177e4	42	{
d6551e88	43	struct thread_info *thread = v;
681a4991	44	union vfp_state *vfp;
c6428464	45	__u32 cpu = thread->cpu;
1da177e4	46
681a4991	47	if (likely(cmd == THREAD_NOTIFY_SWITCH)) {
c6428464 CM	48	u32 fpexc = fmrx(FPEXC);
	49
	50	#ifdef CONFIG_SMP
	51	/*
	52	* On SMP, if VFP is enabled, save the old state in
	53	* case the thread migrates to a different CPU. The
	54	* restoring is done lazily.
	55	*/
228adef1	56	if ((fpexc & FPEXC_EN) && last_VFP_context[cpu]) {
c6428464 CM	57	vfp_save_state(last_VFP_context[cpu], fpexc);
	58	last_VFP_context[cpu]->hard.cpu = cpu;
	59	}
	60	/*
	61	* Thread migration, just force the reloading of the
	62	* state on the new CPU in case the VFP registers
	63	* contain stale data.
	64	*/
	65	if (thread->vfpstate.hard.cpu != cpu)
	66	last_VFP_context[cpu] = NULL;
	67	#endif
	68
681a4991 RK	69	/*
	70	* Always disable VFP so we can lazily save/restore the
	71	* old state.
	72	*/
228adef1	73	fmxr(FPEXC, fpexc & ~FPEXC_EN);
681a4991 RK	74	return NOTIFY_DONE;
	75	}
	76
	77	vfp = &thread->vfpstate;
	78	if (cmd == THREAD_NOTIFY_FLUSH) {
d6551e88 RK	79	/*
	80	* Per-thread VFP initialisation.
	81	*/
	82	memset(vfp, 0, sizeof(union vfp_state));
1da177e4	83
228adef1	84	vfp->hard.fpexc = FPEXC_EN;
d6551e88	85	vfp->hard.fpscr = FPSCR_ROUND_NEAREST;
1da177e4	86
d6551e88 RK	87	/*
	88	* Disable VFP to ensure we initialise it first.
	89	*/
228adef1	90	fmxr(FPEXC, fmrx(FPEXC) & ~FPEXC_EN);
d6551e88 RK	91	}
d6551e88 RK	92
681a4991	93	/* flush and release case: Per-thread VFP cleanup. */
c6428464 CM	94	if (last_VFP_context[cpu] == vfp)
c6428464 CM	95	last_VFP_context[cpu] = NULL;
681a4991	96
d6551e88	97	return NOTIFY_DONE;
1da177e4 LT	98	}
1da177e4 LT	99
d6551e88 RK	100	static struct notifier_block vfp_notifier_block = {
	101	.notifier_call = vfp_notifier,
	102	};
	103
1da177e4 LT	104	/*
	105	* Raise a SIGFPE for the current process.
	106	* sicode describes the signal being raised.
	107	*/
	108	void vfp_raise_sigfpe(unsigned int sicode, struct pt_regs *regs)
	109	{
	110	siginfo_t info;
	111
	112	memset(&info, 0, sizeof(info));
	113
	114	info.si_signo = SIGFPE;
	115	info.si_code = sicode;
35d59fc5	116	info.si_addr = (void __user *)(instruction_pointer(regs) - 4);
1da177e4 LT	117
	118	/*
	119	* This is the same as NWFPE, because it's not clear what
	120	* this is used for
	121	*/
	122	current->thread.error_code = 0;
	123	current->thread.trap_no = 6;
	124
da41119a	125	send_sig_info(SIGFPE, &info, current);
1da177e4 LT	126	}
	127
	128	static void vfp_panic(char *reason)
	129	{
	130	int i;
	131
	132	printk(KERN_ERR "VFP: Error: %s\n", reason);
	133	printk(KERN_ERR "VFP: EXC 0x%08x SCR 0x%08x INST 0x%08x\n",
	134	fmrx(FPEXC), fmrx(FPSCR), fmrx(FPINST));
	135	for (i = 0; i < 32; i += 2)
	136	printk(KERN_ERR "VFP: s%2u: 0x%08x s%2u: 0x%08x\n",
	137	i, vfp_get_float(i), i+1, vfp_get_float(i+1));
	138	}
	139
	140	/*
	141	* Process bitmask of exception conditions.
	142	*/
	143	static void vfp_raise_exceptions(u32 exceptions, u32 inst, u32 fpscr, struct pt_regs *regs)
	144	{
	145	int si_code = 0;
	146
	147	pr_debug("VFP: raising exceptions %08x\n", exceptions);
	148
7c6f2514	149	if (exceptions == VFP_EXCEPTION_ERROR) {
1da177e4 LT	150	vfp_panic("unhandled bounce");
	151	vfp_raise_sigfpe(0, regs);
	152	return;
	153	}
	154
	155	/*
	156	* If any of the status flags are set, update the FPSCR.
	157	* Comparison instructions always return at least one of
	158	* these flags set.
	159	*/
	160	if (exceptions & (FPSCR_N\|FPSCR_Z\|FPSCR_C\|FPSCR_V))
	161	fpscr &= ~(FPSCR_N\|FPSCR_Z\|FPSCR_C\|FPSCR_V);
	162
	163	fpscr \|= exceptions;
	164
	165	fmxr(FPSCR, fpscr);
	166
	167	#define RAISE(stat,en,sig) \
	168	if (exceptions & stat && fpscr & en) \
	169	si_code = sig;
	170
	171	/*
	172	* These are arranged in priority order, least to highest.
	173	*/
e0f205d9	174	RAISE(FPSCR_DZC, FPSCR_DZE, FPE_FLTDIV);
1da177e4 LT	175	RAISE(FPSCR_IXC, FPSCR_IXE, FPE_FLTRES);
	176	RAISE(FPSCR_UFC, FPSCR_UFE, FPE_FLTUND);
	177	RAISE(FPSCR_OFC, FPSCR_OFE, FPE_FLTOVF);
	178	RAISE(FPSCR_IOC, FPSCR_IOE, FPE_FLTINV);
	179
	180	if (si_code)
	181	vfp_raise_sigfpe(si_code, regs);
	182	}
	183
	184	/*
	185	* Emulate a VFP instruction.
	186	*/
	187	static u32 vfp_emulate_instruction(u32 inst, u32 fpscr, struct pt_regs *regs)
	188	{
7c6f2514	189	u32 exceptions = VFP_EXCEPTION_ERROR;
1da177e4 LT	190
	191	pr_debug("VFP: emulate: INST=0x%08x SCR=0x%08x\n", inst, fpscr);
	192
	193	if (INST_CPRTDO(inst)) {
	194	if (!INST_CPRT(inst)) {
	195	/*
	196	* CPDO
	197	*/
	198	if (vfp_single(inst)) {
	199	exceptions = vfp_single_cpdo(inst, fpscr);
	200	} else {
	201	exceptions = vfp_double_cpdo(inst, fpscr);
	202	}
	203	} else {
	204	/*
	205	* A CPRT instruction can not appear in FPINST2, nor
	206	* can it cause an exception. Therefore, we do not
	207	* have to emulate it.
	208	*/
	209	}
	210	} else {
	211	/*
	212	* A CPDT instruction can not appear in FPINST2, nor can
	213	* it cause an exception. Therefore, we do not have to
	214	* emulate it.
	215	*/
	216	}
928bd1b4	217	return exceptions & ~VFP_NAN_FLAG;
1da177e4 LT	218	}
	219
	220	/*
	221	* Package up a bounce condition.
	222	*/
	223	void VFP9_bounce(u32 trigger, u32 fpexc, struct pt_regs *regs)
	224	{
	225	u32 fpscr, orig_fpscr, exceptions, inst;
	226
	227	pr_debug("VFP: bounce: trigger %08x fpexc %08x\n", trigger, fpexc);
	228
	229	/*
	230	* Enable access to the VFP so we can handle the bounce.
	231	*/
228adef1	232	fmxr(FPEXC, fpexc & ~(FPEXC_EX\|FPEXC_INV\|FPEXC_UFC\|FPEXC_IOC));
1da177e4 LT	233
	234	orig_fpscr = fpscr = fmrx(FPSCR);
	235
	236	/*
	237	* If we are running with inexact exceptions enabled, we need to
	238	* emulate the trigger instruction. Note that as we're emulating
	239	* the trigger instruction, we need to increment PC.
	240	*/
	241	if (fpscr & FPSCR_IXE) {
	242	regs->ARM_pc += 4;
	243	goto emulate;
	244	}
	245
	246	barrier();
	247
	248	/*
	249	* Modify fpscr to indicate the number of iterations remaining
	250	*/
228adef1	251	if (fpexc & FPEXC_EX) {
1da177e4 LT	252	u32 len;
	253
	254	len = fpexc + (1 << FPEXC_LENGTH_BIT);
	255
	256	fpscr &= ~FPSCR_LENGTH_MASK;
	257	fpscr \|= (len & FPEXC_LENGTH_MASK) << (FPSCR_LENGTH_BIT - FPEXC_LENGTH_BIT);
	258	}
	259
	260	/*
	261	* Handle the first FP instruction. We used to take note of the
	262	* FPEXC bounce reason, but this appears to be unreliable.
	263	* Emulate the bounced instruction instead.
	264	*/
	265	inst = fmrx(FPINST);
	266	exceptions = vfp_emulate_instruction(inst, fpscr, regs);
	267	if (exceptions)
	268	vfp_raise_exceptions(exceptions, inst, orig_fpscr, regs);
	269
	270	/*
	271	* If there isn't a second FP instruction, exit now.
	272	*/
	273	if (!(fpexc & FPEXC_FPV2))
	274	return;
	275
	276	/*
	277	* The barrier() here prevents fpinst2 being read
	278	* before the condition above.
	279	*/
	280	barrier();
	281	trigger = fmrx(FPINST2);
b7d7ef87	282	orig_fpscr = fpscr = fmrx(FPSCR);
1da177e4 LT	283
	284	emulate:
	285	exceptions = vfp_emulate_instruction(trigger, fpscr, regs);
	286	if (exceptions)
	287	vfp_raise_exceptions(exceptions, trigger, orig_fpscr, regs);
	288	}
efe90d27	289
8e140362 RK	290	static void vfp_enable(void *unused)
	291	{
	292	u32 access = get_copro_access();
	293
	294	/*
	295	* Enable full access to VFP (cp10 and cp11)
	296	*/
	297	set_copro_access(access \| CPACC_FULL(10) \| CPACC_FULL(11));
	298	}
	299
	300	#include <linux/smp.h>
	301
1da177e4 LT	302	/*
	303	* VFP support code initialisation.
	304	*/
	305	static int __init vfp_init(void)
	306	{
	307	unsigned int vfpsid;
efe90d27 RK	308	unsigned int cpu_arch = cpu_architecture();
	309	u32 access = 0;
	310
	311	if (cpu_arch >= CPU_ARCH_ARMv6) {
	312	access = get_copro_access();
	313
	314	/*
	315	* Enable full access to VFP (cp10 and cp11)
	316	*/
	317	set_copro_access(access \| CPACC_FULL(10) \| CPACC_FULL(11));
	318	}
1da177e4 LT	319
	320	/*
	321	* First check that there is a VFP that we can use.
	322	* The handler is already setup to just log calls, so
	323	* we just need to read the VFPSID register.
	324	*/
5d4cae5f	325	vfp_vector = vfp_testing_entry;
1da177e4	326	vfpsid = fmrx(FPSID);
8e140362	327	barrier();
5d4cae5f	328	vfp_vector = vfp_null_entry;
1da177e4 LT	329
	330	printk(KERN_INFO "VFP support v0.3: ");
	331	if (VFP_arch) {
	332	printk("not present\n");
efe90d27 RK	333
	334	/*
	335	* Restore the copro access register.
	336	*/
	337	if (cpu_arch >= CPU_ARCH_ARMv6)
	338	set_copro_access(access);
1da177e4 LT	339	} else if (vfpsid & FPSID_NODOUBLE) {
	340	printk("no double precision support\n");
	341	} else {
8e140362 RK	342	smp_call_function(vfp_enable, NULL, 1, 1);
8e140362 RK	343
1da177e4 LT	344	VFP_arch = (vfpsid & FPSID_ARCH_MASK) >> FPSID_ARCH_BIT; /* Extract the architecture version */
	345	printk("implementor %02x architecture %d part %02x variant %x rev %x\n",
	346	(vfpsid & FPSID_IMPLEMENTER_MASK) >> FPSID_IMPLEMENTER_BIT,
	347	(vfpsid & FPSID_ARCH_MASK) >> FPSID_ARCH_BIT,
	348	(vfpsid & FPSID_PART_MASK) >> FPSID_PART_BIT,
	349	(vfpsid & FPSID_VARIANT_MASK) >> FPSID_VARIANT_BIT,
	350	(vfpsid & FPSID_REV_MASK) >> FPSID_REV_BIT);
efe90d27	351
1da177e4	352	vfp_vector = vfp_support_entry;
d6551e88 RK	353
d6551e88 RK	354	thread_register_notifier(&vfp_notifier_block);
efe90d27 RK	355
	356	/*
	357	* We detected VFP, and the support code is
	358	* in place; report VFP support to userspace.
	359	*/
	360	elf_hwcap \|= HWCAP_VFP;
1da177e4 LT	361	}
	362	return 0;
	363	}
	364
	365	late_initcall(vfp_init);