Commit | Line | Data |
---|---|---|
8c2c3df3 CM |
1 | config ARM64 |
2 | def_bool y | |
b6197b93 | 3 | select ACPI_CCA_REQUIRED if ACPI |
d8f4f161 | 4 | select ACPI_GENERIC_GSI if ACPI |
6933de0c | 5 | select ACPI_REDUCED_HARDWARE_ONLY if ACPI |
8c2c3df3 | 6 | select ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE |
2b68f6ca | 7 | select ARCH_HAS_ELF_RANDOMIZE |
957e3fac | 8 | select ARCH_HAS_GCOV_PROFILE_ALL |
308c09f1 | 9 | select ARCH_HAS_SG_CHAIN |
1f85008e | 10 | select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST |
c63c8700 | 11 | select ARCH_USE_CMPXCHG_LOCKREF |
4badad35 | 12 | select ARCH_SUPPORTS_ATOMIC_RMW |
9170100e | 13 | select ARCH_WANT_OPTIONAL_GPIOLIB |
6212a512 | 14 | select ARCH_WANT_COMPAT_IPC_PARSE_VERSION |
b6f35981 | 15 | select ARCH_WANT_FRAME_POINTERS |
25c92a37 | 16 | select ARM_AMBA |
1aee5d7a | 17 | select ARM_ARCH_TIMER |
c4188edc | 18 | select ARM_GIC |
875cbf3e | 19 | select AUDIT_ARCH_COMPAT_GENERIC |
853a33ce | 20 | select ARM_GIC_V2M if PCI_MSI |
021f6537 | 21 | select ARM_GIC_V3 |
19812729 | 22 | select ARM_GIC_V3_ITS if PCI_MSI |
bff60792 | 23 | select ARM_PSCI_FW |
adace895 | 24 | select BUILDTIME_EXTABLE_SORT |
db2789b5 | 25 | select CLONE_BACKWARDS |
7ca2ef33 | 26 | select COMMON_CLK |
166936ba | 27 | select CPU_PM if (SUSPEND || CPU_IDLE) |
7bc13fd3 | 28 | select DCACHE_WORD_ACCESS |
ef37566c | 29 | select EDAC_SUPPORT |
d4932f9e | 30 | select GENERIC_ALLOCATOR |
8c2c3df3 | 31 | select GENERIC_CLOCKEVENTS |
4b3dc967 | 32 | select GENERIC_CLOCKEVENTS_BROADCAST |
3be1a5c4 | 33 | select GENERIC_CPU_AUTOPROBE |
bf4b558e | 34 | select GENERIC_EARLY_IOREMAP |
8c2c3df3 CM |
35 | select GENERIC_IRQ_PROBE |
36 | select GENERIC_IRQ_SHOW | |
6544e67b | 37 | select GENERIC_IRQ_SHOW_LEVEL |
cb61f676 | 38 | select GENERIC_PCI_IOMAP |
65cd4f6c | 39 | select GENERIC_SCHED_CLOCK |
8c2c3df3 | 40 | select GENERIC_SMP_IDLE_THREAD |
12a0ef7b WD |
41 | select GENERIC_STRNCPY_FROM_USER |
42 | select GENERIC_STRNLEN_USER | |
8c2c3df3 | 43 | select GENERIC_TIME_VSYSCALL |
a1ddc74a | 44 | select HANDLE_DOMAIN_IRQ |
8c2c3df3 | 45 | select HARDIRQS_SW_RESEND |
5284e1b4 | 46 | select HAVE_ALIGNED_STRUCT_PAGE if SLUB |
875cbf3e | 47 | select HAVE_ARCH_AUDITSYSCALL |
8e7a4cef | 48 | select HAVE_ARCH_BITREVERSE |
9732cafd | 49 | select HAVE_ARCH_JUMP_LABEL |
9529247d | 50 | select HAVE_ARCH_KGDB |
a1ae65b2 | 51 | select HAVE_ARCH_SECCOMP_FILTER |
8c2c3df3 | 52 | select HAVE_ARCH_TRACEHOOK |
e54bcde3 | 53 | select HAVE_BPF_JIT |
af64d2aa | 54 | select HAVE_C_RECORDMCOUNT |
c0c264ae | 55 | select HAVE_CC_STACKPROTECTOR |
5284e1b4 | 56 | select HAVE_CMPXCHG_DOUBLE |
95eff6b2 | 57 | select HAVE_CMPXCHG_LOCAL |
9b2a60c4 | 58 | select HAVE_DEBUG_BUGVERBOSE |
b69ec42b | 59 | select HAVE_DEBUG_KMEMLEAK |
8c2c3df3 CM |
60 | select HAVE_DMA_API_DEBUG |
61 | select HAVE_DMA_ATTRS | |
6ac2104d | 62 | select HAVE_DMA_CONTIGUOUS |
bd7d38db | 63 | select HAVE_DYNAMIC_FTRACE |
50afc33a | 64 | select HAVE_EFFICIENT_UNALIGNED_ACCESS |
af64d2aa | 65 | select HAVE_FTRACE_MCOUNT_RECORD |
819e50e2 AT |
66 | select HAVE_FUNCTION_TRACER |
67 | select HAVE_FUNCTION_GRAPH_TRACER | |
8c2c3df3 | 68 | select HAVE_GENERIC_DMA_COHERENT |
8c2c3df3 | 69 | select HAVE_HW_BREAKPOINT if PERF_EVENTS |
8c2c3df3 | 70 | select HAVE_MEMBLOCK |
55834a77 | 71 | select HAVE_PATA_PLATFORM |
8c2c3df3 | 72 | select HAVE_PERF_EVENTS |
2ee0d7fd JP |
73 | select HAVE_PERF_REGS |
74 | select HAVE_PERF_USER_STACK_DUMP | |
5e5f6dc1 | 75 | select HAVE_RCU_TABLE_FREE |
055b1212 | 76 | select HAVE_SYSCALL_TRACEPOINTS |
8c2c3df3 | 77 | select IRQ_DOMAIN |
e8557d1f | 78 | select IRQ_FORCED_THREADING |
fea2acaa | 79 | select MODULES_USE_ELF_RELA |
8c2c3df3 CM |
80 | select NO_BOOTMEM |
81 | select OF | |
82 | select OF_EARLY_FLATTREE | |
9bf14b7c | 83 | select OF_RESERVED_MEM |
8c2c3df3 | 84 | select PERF_USE_VMALLOC |
aa1e8ec1 CM |
85 | select POWER_RESET |
86 | select POWER_SUPPLY | |
8c2c3df3 CM |
87 | select RTC_LIB |
88 | select SPARSE_IRQ | |
7ac57a89 | 89 | select SYSCTL_EXCEPTION_TRACE |
6c81fe79 | 90 | select HAVE_CONTEXT_TRACKING |
8c2c3df3 CM |
91 | help |
92 | ARM 64-bit (AArch64) Linux support. | |
93 | ||
94 | config 64BIT | |
95 | def_bool y | |
96 | ||
97 | config ARCH_PHYS_ADDR_T_64BIT | |
98 | def_bool y | |
99 | ||
100 | config MMU | |
101 | def_bool y | |
102 | ||
ce816fa8 | 103 | config NO_IOPORT_MAP |
d1e6dc91 | 104 | def_bool y if !PCI |
8c2c3df3 CM |
105 | |
106 | config STACKTRACE_SUPPORT | |
107 | def_bool y | |
108 | ||
bf0c4e04 JVS |
109 | config ILLEGAL_POINTER_VALUE |
110 | hex | |
111 | default 0xdead000000000000 | |
112 | ||
8c2c3df3 CM |
113 | config LOCKDEP_SUPPORT |
114 | def_bool y | |
115 | ||
116 | config TRACE_IRQFLAGS_SUPPORT | |
117 | def_bool y | |
118 | ||
c209f799 | 119 | config RWSEM_XCHGADD_ALGORITHM |
8c2c3df3 CM |
120 | def_bool y |
121 | ||
9fb7410f DM |
122 | config GENERIC_BUG |
123 | def_bool y | |
124 | depends on BUG | |
125 | ||
126 | config GENERIC_BUG_RELATIVE_POINTERS | |
127 | def_bool y | |
128 | depends on GENERIC_BUG | |
129 | ||
8c2c3df3 CM |
130 | config GENERIC_HWEIGHT |
131 | def_bool y | |
132 | ||
133 | config GENERIC_CSUM | |
134 | def_bool y | |
135 | ||
136 | config GENERIC_CALIBRATE_DELAY | |
137 | def_bool y | |
138 | ||
19e7640d | 139 | config ZONE_DMA |
8c2c3df3 CM |
140 | def_bool y |
141 | ||
29e56940 SC |
142 | config HAVE_GENERIC_RCU_GUP |
143 | def_bool y | |
144 | ||
8c2c3df3 CM |
145 | config ARCH_DMA_ADDR_T_64BIT |
146 | def_bool y | |
147 | ||
148 | config NEED_DMA_MAP_STATE | |
149 | def_bool y | |
150 | ||
151 | config NEED_SG_DMA_LENGTH | |
152 | def_bool y | |
153 | ||
4b3dc967 WD |
154 | config SMP |
155 | def_bool y | |
156 | ||
8c2c3df3 CM |
157 | config SWIOTLB |
158 | def_bool y | |
159 | ||
160 | config IOMMU_HELPER | |
161 | def_bool SWIOTLB | |
162 | ||
4cfb3613 AB |
163 | config KERNEL_MODE_NEON |
164 | def_bool y | |
165 | ||
92cc15fc RH |
166 | config FIX_EARLYCON_MEM |
167 | def_bool y | |
168 | ||
9f25e6ad KS |
169 | config PGTABLE_LEVELS |
170 | int | |
171 | default 2 if ARM64_64K_PAGES && ARM64_VA_BITS_42 | |
172 | default 3 if ARM64_64K_PAGES && ARM64_VA_BITS_48 | |
173 | default 3 if ARM64_4K_PAGES && ARM64_VA_BITS_39 | |
174 | default 4 if ARM64_4K_PAGES && ARM64_VA_BITS_48 | |
175 | ||
8c2c3df3 CM |
176 | source "init/Kconfig" |
177 | ||
178 | source "kernel/Kconfig.freezer" | |
179 | ||
6a377491 | 180 | source "arch/arm64/Kconfig.platforms" |
8c2c3df3 CM |
181 | |
182 | menu "Bus support" | |
183 | ||
d1e6dc91 LD |
184 | config PCI |
185 | bool "PCI support" | |
186 | help | |
187 | This feature enables support for PCI bus system. If you say Y | |
188 | here, the kernel will include drivers and infrastructure code | |
189 | to support PCI bus devices. | |
190 | ||
191 | config PCI_DOMAINS | |
192 | def_bool PCI | |
193 | ||
194 | config PCI_DOMAINS_GENERIC | |
195 | def_bool PCI | |
196 | ||
197 | config PCI_SYSCALL | |
198 | def_bool PCI | |
199 | ||
200 | source "drivers/pci/Kconfig" | |
201 | source "drivers/pci/pcie/Kconfig" | |
202 | source "drivers/pci/hotplug/Kconfig" | |
203 | ||
8c2c3df3 CM |
204 | endmenu |
205 | ||
206 | menu "Kernel Features" | |
207 | ||
c0a01b84 AP |
208 | menu "ARM errata workarounds via the alternatives framework" |
209 | ||
210 | config ARM64_ERRATUM_826319 | |
211 | bool "Cortex-A53: 826319: System might deadlock if a write cannot complete until read data is accepted" | |
212 | default y | |
213 | help | |
214 | This option adds an alternative code sequence to work around ARM | |
215 | erratum 826319 on Cortex-A53 parts up to r0p2 with an AMBA 4 ACE or | |
216 | AXI master interface and an L2 cache. | |
217 | ||
218 | If a Cortex-A53 uses an AMBA AXI4 ACE interface to other processors | |
219 | and is unable to accept a certain write via this interface, it will | |
220 | not progress on read data presented on the read data channel and the | |
221 | system can deadlock. | |
222 | ||
223 | The workaround promotes data cache clean instructions to | |
224 | data cache clean-and-invalidate. | |
225 | Please note that this does not necessarily enable the workaround, | |
226 | as it depends on the alternative framework, which will only patch | |
227 | the kernel if an affected CPU is detected. | |
228 | ||
229 | If unsure, say Y. | |
230 | ||
231 | config ARM64_ERRATUM_827319 | |
232 | bool "Cortex-A53: 827319: Data cache clean instructions might cause overlapping transactions to the interconnect" | |
233 | default y | |
234 | help | |
235 | This option adds an alternative code sequence to work around ARM | |
236 | erratum 827319 on Cortex-A53 parts up to r0p2 with an AMBA 5 CHI | |
237 | master interface and an L2 cache. | |
238 | ||
239 | Under certain conditions this erratum can cause a clean line eviction | |
240 | to occur at the same time as another transaction to the same address | |
241 | on the AMBA 5 CHI interface, which can cause data corruption if the | |
242 | interconnect reorders the two transactions. | |
243 | ||
244 | The workaround promotes data cache clean instructions to | |
245 | data cache clean-and-invalidate. | |
246 | Please note that this does not necessarily enable the workaround, | |
247 | as it depends on the alternative framework, which will only patch | |
248 | the kernel if an affected CPU is detected. | |
249 | ||
250 | If unsure, say Y. | |
251 | ||
252 | config ARM64_ERRATUM_824069 | |
253 | bool "Cortex-A53: 824069: Cache line might not be marked as clean after a CleanShared snoop" | |
254 | default y | |
255 | help | |
256 | This option adds an alternative code sequence to work around ARM | |
257 | erratum 824069 on Cortex-A53 parts up to r0p2 when it is connected | |
258 | to a coherent interconnect. | |
259 | ||
260 | If a Cortex-A53 processor is executing a store or prefetch for | |
261 | write instruction at the same time as a processor in another | |
262 | cluster is executing a cache maintenance operation to the same | |
263 | address, then this erratum might cause a clean cache line to be | |
264 | incorrectly marked as dirty. | |
265 | ||
266 | The workaround promotes data cache clean instructions to | |
267 | data cache clean-and-invalidate. | |
268 | Please note that this option does not necessarily enable the | |
269 | workaround, as it depends on the alternative framework, which will | |
270 | only patch the kernel if an affected CPU is detected. | |
271 | ||
272 | If unsure, say Y. | |
273 | ||
274 | config ARM64_ERRATUM_819472 | |
275 | bool "Cortex-A53: 819472: Store exclusive instructions might cause data corruption" | |
276 | default y | |
277 | help | |
278 | This option adds an alternative code sequence to work around ARM | |
279 | erratum 819472 on Cortex-A53 parts up to r0p1 with an L2 cache | |
280 | present when it is connected to a coherent interconnect. | |
281 | ||
282 | If the processor is executing a load and store exclusive sequence at | |
283 | the same time as a processor in another cluster is executing a cache | |
284 | maintenance operation to the same address, then this erratum might | |
285 | cause data corruption. | |
286 | ||
287 | The workaround promotes data cache clean instructions to | |
288 | data cache clean-and-invalidate. | |
289 | Please note that this does not necessarily enable the workaround, | |
290 | as it depends on the alternative framework, which will only patch | |
291 | the kernel if an affected CPU is detected. | |
292 | ||
293 | If unsure, say Y. | |
294 | ||
295 | config ARM64_ERRATUM_832075 | |
296 | bool "Cortex-A57: 832075: possible deadlock on mixing exclusive memory accesses with device loads" | |
297 | default y | |
298 | help | |
299 | This option adds an alternative code sequence to work around ARM | |
300 | erratum 832075 on Cortex-A57 parts up to r1p2. | |
301 | ||
302 | Affected Cortex-A57 parts might deadlock when exclusive load/store | |
303 | instructions to Write-Back memory are mixed with Device loads. | |
304 | ||
305 | The workaround is to promote device loads to use Load-Acquire | |
306 | semantics. | |
307 | Please note that this does not necessarily enable the workaround, | |
308 | as it depends on the alternative framework, which will only patch | |
309 | the kernel if an affected CPU is detected. | |
310 | ||
311 | If unsure, say Y. | |
312 | ||
905e8c5d WD |
313 | config ARM64_ERRATUM_845719 |
314 | bool "Cortex-A53: 845719: a load might read incorrect data" | |
315 | depends on COMPAT | |
316 | default y | |
317 | help | |
318 | This option adds an alternative code sequence to work around ARM | |
319 | erratum 845719 on Cortex-A53 parts up to r0p4. | |
320 | ||
321 | When running a compat (AArch32) userspace on an affected Cortex-A53 | |
322 | part, a load at EL0 from a virtual address that matches the bottom 32 | |
323 | bits of the virtual address used by a recent load at (AArch64) EL1 | |
324 | might return incorrect data. | |
325 | ||
326 | The workaround is to write the contextidr_el1 register on exception | |
327 | return to a 32-bit task. | |
328 | Please note that this does not necessarily enable the workaround, | |
329 | as it depends on the alternative framework, which will only patch | |
330 | the kernel if an affected CPU is detected. | |
331 | ||
332 | If unsure, say Y. | |
333 | ||
c0a01b84 AP |
334 | endmenu |
335 | ||
336 | ||
e41ceed0 JL |
337 | choice |
338 | prompt "Page size" | |
339 | default ARM64_4K_PAGES | |
340 | help | |
341 | Page size (translation granule) configuration. | |
342 | ||
343 | config ARM64_4K_PAGES | |
344 | bool "4KB" | |
345 | help | |
346 | This feature enables 4KB pages support. | |
347 | ||
8c2c3df3 | 348 | config ARM64_64K_PAGES |
e41ceed0 | 349 | bool "64KB" |
8c2c3df3 CM |
350 | help |
351 | This feature enables 64KB pages support (4KB by default) | |
352 | allowing only two levels of page tables and faster TLB | |
353 | look-up. AArch32 emulation is not available when this feature | |
354 | is enabled. | |
355 | ||
e41ceed0 JL |
356 | endchoice |
357 | ||
358 | choice | |
359 | prompt "Virtual address space size" | |
360 | default ARM64_VA_BITS_39 if ARM64_4K_PAGES | |
361 | default ARM64_VA_BITS_42 if ARM64_64K_PAGES | |
362 | help | |
363 | Allows choosing one of multiple possible virtual address | |
364 | space sizes. The level of translation table is determined by | |
365 | a combination of page size and virtual address space size. | |
366 | ||
367 | config ARM64_VA_BITS_39 | |
368 | bool "39-bit" | |
369 | depends on ARM64_4K_PAGES | |
370 | ||
371 | config ARM64_VA_BITS_42 | |
372 | bool "42-bit" | |
373 | depends on ARM64_64K_PAGES | |
374 | ||
c79b954b JL |
375 | config ARM64_VA_BITS_48 |
376 | bool "48-bit" | |
c79b954b | 377 | |
e41ceed0 JL |
378 | endchoice |
379 | ||
380 | config ARM64_VA_BITS | |
381 | int | |
382 | default 39 if ARM64_VA_BITS_39 | |
383 | default 42 if ARM64_VA_BITS_42 | |
c79b954b | 384 | default 48 if ARM64_VA_BITS_48 |
e41ceed0 | 385 | |
a872013d WD |
386 | config CPU_BIG_ENDIAN |
387 | bool "Build big-endian kernel" | |
388 | help | |
389 | Say Y if you plan on running a kernel in big-endian mode. | |
390 | ||
f6e763b9 MB |
391 | config SCHED_MC |
392 | bool "Multi-core scheduler support" | |
f6e763b9 MB |
393 | help |
394 | Multi-core scheduler support improves the CPU scheduler's decision | |
395 | making when dealing with multi-core CPU chips at a cost of slightly | |
396 | increased overhead in some places. If unsure say N here. | |
397 | ||
398 | config SCHED_SMT | |
399 | bool "SMT scheduler support" | |
f6e763b9 MB |
400 | help |
401 | Improves the CPU scheduler's decision making when dealing with | |
402 | MultiThreading at a cost of slightly increased overhead in some | |
403 | places. If unsure say N here. | |
404 | ||
8c2c3df3 | 405 | config NR_CPUS |
62aa9655 GK |
406 | int "Maximum number of CPUs (2-4096)" |
407 | range 2 4096 | |
15942853 | 408 | # These have to remain sorted largest to smallest |
e3672649 | 409 | default "64" |
8c2c3df3 | 410 | |
9327e2c6 MR |
411 | config HOTPLUG_CPU |
412 | bool "Support for hot-pluggable CPUs" | |
9327e2c6 MR |
413 | help |
414 | Say Y here to experiment with turning CPUs off and on. CPUs | |
415 | can be controlled through /sys/devices/system/cpu. | |
416 | ||
8c2c3df3 CM |
417 | source kernel/Kconfig.preempt |
418 | ||
419 | config HZ | |
420 | int | |
421 | default 100 | |
422 | ||
423 | config ARCH_HAS_HOLES_MEMORYMODEL | |
424 | def_bool y if SPARSEMEM | |
425 | ||
426 | config ARCH_SPARSEMEM_ENABLE | |
427 | def_bool y | |
428 | select SPARSEMEM_VMEMMAP_ENABLE | |
429 | ||
430 | config ARCH_SPARSEMEM_DEFAULT | |
431 | def_bool ARCH_SPARSEMEM_ENABLE | |
432 | ||
433 | config ARCH_SELECT_MEMORY_MODEL | |
434 | def_bool ARCH_SPARSEMEM_ENABLE | |
435 | ||
436 | config HAVE_ARCH_PFN_VALID | |
437 | def_bool ARCH_HAS_HOLES_MEMORYMODEL || !SPARSEMEM | |
438 | ||
439 | config HW_PERF_EVENTS | |
440 | bool "Enable hardware performance counter support for perf events" | |
441 | depends on PERF_EVENTS | |
442 | default y | |
443 | help | |
444 | Enable hardware performance counter support for perf events. If | |
445 | disabled, perf events will use software events only. | |
446 | ||
084bd298 SC |
447 | config SYS_SUPPORTS_HUGETLBFS |
448 | def_bool y | |
449 | ||
450 | config ARCH_WANT_GENERAL_HUGETLB | |
451 | def_bool y | |
452 | ||
453 | config ARCH_WANT_HUGE_PMD_SHARE | |
454 | def_bool y if !ARM64_64K_PAGES | |
455 | ||
af074848 SC |
456 | config HAVE_ARCH_TRANSPARENT_HUGEPAGE |
457 | def_bool y | |
458 | ||
a41dc0e8 CM |
459 | config ARCH_HAS_CACHE_LINE_SIZE |
460 | def_bool y | |
461 | ||
8c2c3df3 CM |
462 | source "mm/Kconfig" |
463 | ||
a1ae65b2 AT |
464 | config SECCOMP |
465 | bool "Enable seccomp to safely compute untrusted bytecode" | |
466 | ---help--- | |
467 | This kernel feature is useful for number crunching applications | |
468 | that may need to compute untrusted bytecode during their | |
469 | execution. By using pipes or other transports made available to | |
470 | the process as file descriptors supporting the read/write | |
471 | syscalls, it's possible to isolate those applications in | |
472 | their own address space using seccomp. Once seccomp is | |
473 | enabled via prctl(PR_SET_SECCOMP), it cannot be disabled | |
474 | and the task is only allowed to execute a few safe syscalls | |
475 | defined by each seccomp mode. | |
476 | ||
aa42aa13 SS |
477 | config XEN_DOM0 |
478 | def_bool y | |
479 | depends on XEN | |
480 | ||
481 | config XEN | |
c2ba1f7d | 482 | bool "Xen guest support on ARM64" |
aa42aa13 | 483 | depends on ARM64 && OF |
83862ccf | 484 | select SWIOTLB_XEN |
aa42aa13 SS |
485 | help |
486 | Say Y if you want to run Linux in a Virtual Machine on Xen on ARM64. | |
487 | ||
d03bb145 SC |
488 | config FORCE_MAX_ZONEORDER |
489 | int | |
490 | default "14" if (ARM64_64K_PAGES && TRANSPARENT_HUGEPAGE) | |
491 | default "11" | |
492 | ||
1b907f46 WD |
493 | menuconfig ARMV8_DEPRECATED |
494 | bool "Emulate deprecated/obsolete ARMv8 instructions" | |
495 | depends on COMPAT | |
496 | help | |
497 | Legacy software support may require certain instructions | |
498 | that have been deprecated or obsoleted in the architecture. | |
499 | ||
500 | Enable this config to enable selective emulation of these | |
501 | features. | |
502 | ||
503 | If unsure, say Y | |
504 | ||
505 | if ARMV8_DEPRECATED | |
506 | ||
507 | config SWP_EMULATION | |
508 | bool "Emulate SWP/SWPB instructions" | |
509 | help | |
510 | ARMv8 obsoletes the use of A32 SWP/SWPB instructions such that | |
511 | they are always undefined. Say Y here to enable software | |
512 | emulation of these instructions for userspace using LDXR/STXR. | |
513 | ||
514 | In some older versions of glibc [<=2.8] SWP is used during futex | |
515 | trylock() operations with the assumption that the code will not | |
516 | be preempted. This invalid assumption may be more likely to fail | |
517 | with SWP emulation enabled, leading to deadlock of the user | |
518 | application. | |
519 | ||
520 | NOTE: when accessing uncached shared regions, LDXR/STXR rely | |
521 | on an external transaction monitoring block called a global | |
522 | monitor to maintain update atomicity. If your system does not | |
523 | implement a global monitor, this option can cause programs that | |
524 | perform SWP operations to uncached memory to deadlock. | |
525 | ||
526 | If unsure, say Y | |
527 | ||
528 | config CP15_BARRIER_EMULATION | |
529 | bool "Emulate CP15 Barrier instructions" | |
530 | help | |
531 | The CP15 barrier instructions - CP15ISB, CP15DSB, and | |
532 | CP15DMB - are deprecated in ARMv8 (and ARMv7). It is | |
533 | strongly recommended to use the ISB, DSB, and DMB | |
534 | instructions instead. | |
535 | ||
536 | Say Y here to enable software emulation of these | |
537 | instructions for AArch32 userspace code. When this option is | |
538 | enabled, CP15 barrier usage is traced which can help | |
539 | identify software that needs updating. | |
540 | ||
541 | If unsure, say Y | |
542 | ||
2d888f48 SP |
543 | config SETEND_EMULATION |
544 | bool "Emulate SETEND instruction" | |
545 | help | |
546 | The SETEND instruction alters the data-endianness of the | |
547 | AArch32 EL0, and is deprecated in ARMv8. | |
548 | ||
549 | Say Y here to enable software emulation of the instruction | |
550 | for AArch32 userspace code. | |
551 | ||
552 | Note: All the cpus on the system must have mixed endian support at EL0 | |
553 | for this feature to be enabled. If a new CPU - which doesn't support mixed | |
554 | endian - is hotplugged in after this feature has been enabled, there could | |
555 | be unexpected results in the applications. | |
556 | ||
557 | If unsure, say Y | |
1b907f46 WD |
558 | endif |
559 | ||
0e4a0709 WD |
560 | menu "ARMv8.1 architectural features" |
561 | ||
562 | config ARM64_HW_AFDBM | |
563 | bool "Support for hardware updates of the Access and Dirty page flags" | |
564 | default y | |
565 | help | |
566 | The ARMv8.1 architecture extensions introduce support for | |
567 | hardware updates of the access and dirty information in page | |
568 | table entries. When enabled in TCR_EL1 (HA and HD bits) on | |
569 | capable processors, accesses to pages with PTE_AF cleared will | |
570 | set this bit instead of raising an access flag fault. | |
571 | Similarly, writes to read-only pages with the DBM bit set will | |
572 | clear the read-only bit (AP[2]) instead of raising a | |
573 | permission fault. | |
574 | ||
575 | Kernels built with this configuration option enabled continue | |
576 | to work on pre-ARMv8.1 hardware and the performance impact is | |
577 | minimal. If unsure, say Y. | |
578 | ||
579 | config ARM64_PAN | |
580 | bool "Enable support for Privileged Access Never (PAN)" | |
581 | default y | |
582 | help | |
583 | Privileged Access Never (PAN; part of the ARMv8.1 Extensions) | |
584 | prevents the kernel or hypervisor from accessing user-space (EL0) | |
585 | memory directly. | |
586 | ||
587 | Choosing this option will cause any unprotected (not using | |
588 | copy_to_user et al) memory access to fail with a permission fault. | |
589 | ||
590 | The feature is detected at runtime, and will remain as a 'nop' | |
591 | instruction if the cpu does not implement the feature. | |
592 | ||
593 | config ARM64_LSE_ATOMICS | |
594 | bool "Atomic instructions" | |
595 | help | |
596 | As part of the Large System Extensions, ARMv8.1 introduces new | |
597 | atomic instructions that are designed specifically to scale in | |
598 | very large systems. | |
599 | ||
600 | Say Y here to make use of these instructions for the in-kernel | |
601 | atomic routines. This incurs a small overhead on CPUs that do | |
602 | not support these instructions and requires the kernel to be | |
603 | built with binutils >= 2.25. | |
604 | ||
605 | endmenu | |
606 | ||
8c2c3df3 CM |
607 | endmenu |
608 | ||
609 | menu "Boot options" | |
610 | ||
611 | config CMDLINE | |
612 | string "Default kernel command string" | |
613 | default "" | |
614 | help | |
615 | Provide a set of default command-line options at build time by | |
616 | entering them here. As a minimum, you should specify the the | |
617 | root device (e.g. root=/dev/nfs). | |
618 | ||
619 | config CMDLINE_FORCE | |
620 | bool "Always use the default kernel command string" | |
621 | help | |
622 | Always use the default kernel command string, even if the boot | |
623 | loader passes other arguments to the kernel. | |
624 | This is useful if you cannot or don't want to change the | |
625 | command-line options your boot loader passes to the kernel. | |
626 | ||
f4f75ad5 AB |
627 | config EFI_STUB |
628 | bool | |
629 | ||
f84d0275 MS |
630 | config EFI |
631 | bool "UEFI runtime support" | |
632 | depends on OF && !CPU_BIG_ENDIAN | |
633 | select LIBFDT | |
634 | select UCS2_STRING | |
635 | select EFI_PARAMS_FROM_FDT | |
e15dd494 | 636 | select EFI_RUNTIME_WRAPPERS |
f4f75ad5 AB |
637 | select EFI_STUB |
638 | select EFI_ARMSTUB | |
f84d0275 MS |
639 | default y |
640 | help | |
641 | This option provides support for runtime services provided | |
642 | by UEFI firmware (such as non-volatile variables, realtime | |
3c7f2550 MS |
643 | clock, and platform reset). A UEFI stub is also provided to |
644 | allow the kernel to be booted as an EFI application. This | |
645 | is only useful on systems that have UEFI firmware. | |
f84d0275 | 646 | |
d1ae8c00 YL |
647 | config DMI |
648 | bool "Enable support for SMBIOS (DMI) tables" | |
649 | depends on EFI | |
650 | default y | |
651 | help | |
652 | This enables SMBIOS/DMI feature for systems. | |
653 | ||
654 | This option is only useful on systems that have UEFI firmware. | |
655 | However, even with this option, the resultant kernel should | |
656 | continue to boot on existing non-UEFI platforms. | |
657 | ||
8c2c3df3 CM |
658 | endmenu |
659 | ||
660 | menu "Userspace binary formats" | |
661 | ||
662 | source "fs/Kconfig.binfmt" | |
663 | ||
664 | config COMPAT | |
665 | bool "Kernel support for 32-bit EL0" | |
a8fcd8b1 | 666 | depends on !ARM64_64K_PAGES || EXPERT |
8c2c3df3 | 667 | select COMPAT_BINFMT_ELF |
af1839eb | 668 | select HAVE_UID16 |
84b9e9b4 | 669 | select OLD_SIGSUSPEND3 |
51682036 | 670 | select COMPAT_OLD_SIGACTION |
8c2c3df3 CM |
671 | help |
672 | This option enables support for a 32-bit EL0 running under a 64-bit | |
673 | kernel at EL1. AArch32-specific components such as system calls, | |
674 | the user helper functions, VFP support and the ptrace interface are | |
675 | handled appropriately by the kernel. | |
676 | ||
a8fcd8b1 AG |
677 | If you also enabled CONFIG_ARM64_64K_PAGES, please be aware that you |
678 | will only be able to execute AArch32 binaries that were compiled with | |
679 | 64k aligned segments. | |
680 | ||
8c2c3df3 CM |
681 | If you want to execute 32-bit userspace applications, say Y. |
682 | ||
683 | config SYSVIPC_COMPAT | |
684 | def_bool y | |
685 | depends on COMPAT && SYSVIPC | |
686 | ||
687 | endmenu | |
688 | ||
166936ba LP |
689 | menu "Power management options" |
690 | ||
691 | source "kernel/power/Kconfig" | |
692 | ||
693 | config ARCH_SUSPEND_POSSIBLE | |
694 | def_bool y | |
695 | ||
166936ba LP |
696 | endmenu |
697 | ||
1307220d LP |
698 | menu "CPU Power Management" |
699 | ||
700 | source "drivers/cpuidle/Kconfig" | |
701 | ||
52e7e816 RH |
702 | source "drivers/cpufreq/Kconfig" |
703 | ||
704 | endmenu | |
705 | ||
8c2c3df3 CM |
706 | source "net/Kconfig" |
707 | ||
708 | source "drivers/Kconfig" | |
709 | ||
f84d0275 MS |
710 | source "drivers/firmware/Kconfig" |
711 | ||
b6a02173 GG |
712 | source "drivers/acpi/Kconfig" |
713 | ||
8c2c3df3 CM |
714 | source "fs/Kconfig" |
715 | ||
c3eb5b14 MZ |
716 | source "arch/arm64/kvm/Kconfig" |
717 | ||
8c2c3df3 CM |
718 | source "arch/arm64/Kconfig.debug" |
719 | ||
720 | source "security/Kconfig" | |
721 | ||
722 | source "crypto/Kconfig" | |
2c98833a AB |
723 | if CRYPTO |
724 | source "arch/arm64/crypto/Kconfig" | |
725 | endif | |
8c2c3df3 CM |
726 | |
727 | source "lib/Kconfig" |