Commit | Line | Data |
---|---|---|
8c2c3df3 CM |
1 | config ARM64 |
2 | def_bool y | |
d8f4f161 | 3 | select ACPI_GENERIC_GSI if ACPI |
6933de0c | 4 | select ACPI_REDUCED_HARDWARE_ONLY if ACPI |
8c2c3df3 | 5 | select ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE |
2b68f6ca | 6 | select ARCH_HAS_ELF_RANDOMIZE |
957e3fac | 7 | select ARCH_HAS_GCOV_PROFILE_ALL |
308c09f1 | 8 | select ARCH_HAS_SG_CHAIN |
1f85008e | 9 | select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST |
c63c8700 | 10 | select ARCH_USE_CMPXCHG_LOCKREF |
4badad35 | 11 | select ARCH_SUPPORTS_ATOMIC_RMW |
9170100e | 12 | select ARCH_WANT_OPTIONAL_GPIOLIB |
6212a512 | 13 | select ARCH_WANT_COMPAT_IPC_PARSE_VERSION |
b6f35981 | 14 | select ARCH_WANT_FRAME_POINTERS |
25c92a37 | 15 | select ARM_AMBA |
1aee5d7a | 16 | select ARM_ARCH_TIMER |
c4188edc | 17 | select ARM_GIC |
875cbf3e | 18 | select AUDIT_ARCH_COMPAT_GENERIC |
853a33ce | 19 | select ARM_GIC_V2M if PCI_MSI |
021f6537 | 20 | select ARM_GIC_V3 |
19812729 | 21 | select ARM_GIC_V3_ITS if PCI_MSI |
adace895 | 22 | select BUILDTIME_EXTABLE_SORT |
db2789b5 | 23 | select CLONE_BACKWARDS |
7ca2ef33 | 24 | select COMMON_CLK |
166936ba | 25 | select CPU_PM if (SUSPEND || CPU_IDLE) |
7bc13fd3 | 26 | select DCACHE_WORD_ACCESS |
d4932f9e | 27 | select GENERIC_ALLOCATOR |
8c2c3df3 | 28 | select GENERIC_CLOCKEVENTS |
1f85008e | 29 | select GENERIC_CLOCKEVENTS_BROADCAST if SMP |
3be1a5c4 | 30 | select GENERIC_CPU_AUTOPROBE |
bf4b558e | 31 | select GENERIC_EARLY_IOREMAP |
8c2c3df3 CM |
32 | select GENERIC_IRQ_PROBE |
33 | select GENERIC_IRQ_SHOW | |
6544e67b | 34 | select GENERIC_IRQ_SHOW_LEVEL |
cb61f676 | 35 | select GENERIC_PCI_IOMAP |
65cd4f6c | 36 | select GENERIC_SCHED_CLOCK |
8c2c3df3 | 37 | select GENERIC_SMP_IDLE_THREAD |
12a0ef7b WD |
38 | select GENERIC_STRNCPY_FROM_USER |
39 | select GENERIC_STRNLEN_USER | |
8c2c3df3 | 40 | select GENERIC_TIME_VSYSCALL |
a1ddc74a | 41 | select HANDLE_DOMAIN_IRQ |
8c2c3df3 | 42 | select HARDIRQS_SW_RESEND |
5284e1b4 | 43 | select HAVE_ALIGNED_STRUCT_PAGE if SLUB |
875cbf3e | 44 | select HAVE_ARCH_AUDITSYSCALL |
8e7a4cef | 45 | select HAVE_ARCH_BITREVERSE |
9732cafd | 46 | select HAVE_ARCH_JUMP_LABEL |
9529247d | 47 | select HAVE_ARCH_KGDB |
a1ae65b2 | 48 | select HAVE_ARCH_SECCOMP_FILTER |
8c2c3df3 | 49 | select HAVE_ARCH_TRACEHOOK |
e54bcde3 | 50 | select HAVE_BPF_JIT |
af64d2aa | 51 | select HAVE_C_RECORDMCOUNT |
c0c264ae | 52 | select HAVE_CC_STACKPROTECTOR |
5284e1b4 | 53 | select HAVE_CMPXCHG_DOUBLE |
9b2a60c4 | 54 | select HAVE_DEBUG_BUGVERBOSE |
b69ec42b | 55 | select HAVE_DEBUG_KMEMLEAK |
8c2c3df3 CM |
56 | select HAVE_DMA_API_DEBUG |
57 | select HAVE_DMA_ATTRS | |
6ac2104d | 58 | select HAVE_DMA_CONTIGUOUS |
bd7d38db | 59 | select HAVE_DYNAMIC_FTRACE |
50afc33a | 60 | select HAVE_EFFICIENT_UNALIGNED_ACCESS |
af64d2aa | 61 | select HAVE_FTRACE_MCOUNT_RECORD |
819e50e2 AT |
62 | select HAVE_FUNCTION_TRACER |
63 | select HAVE_FUNCTION_GRAPH_TRACER | |
8c2c3df3 | 64 | select HAVE_GENERIC_DMA_COHERENT |
8c2c3df3 | 65 | select HAVE_HW_BREAKPOINT if PERF_EVENTS |
8c2c3df3 | 66 | select HAVE_MEMBLOCK |
55834a77 | 67 | select HAVE_PATA_PLATFORM |
8c2c3df3 | 68 | select HAVE_PERF_EVENTS |
2ee0d7fd JP |
69 | select HAVE_PERF_REGS |
70 | select HAVE_PERF_USER_STACK_DUMP | |
5e5f6dc1 | 71 | select HAVE_RCU_TABLE_FREE |
055b1212 | 72 | select HAVE_SYSCALL_TRACEPOINTS |
8c2c3df3 | 73 | select IRQ_DOMAIN |
e8557d1f | 74 | select IRQ_FORCED_THREADING |
fea2acaa | 75 | select MODULES_USE_ELF_RELA |
8c2c3df3 CM |
76 | select NO_BOOTMEM |
77 | select OF | |
78 | select OF_EARLY_FLATTREE | |
9bf14b7c | 79 | select OF_RESERVED_MEM |
8c2c3df3 | 80 | select PERF_USE_VMALLOC |
aa1e8ec1 CM |
81 | select POWER_RESET |
82 | select POWER_SUPPLY | |
8c2c3df3 CM |
83 | select RTC_LIB |
84 | select SPARSE_IRQ | |
7ac57a89 | 85 | select SYSCTL_EXCEPTION_TRACE |
6c81fe79 | 86 | select HAVE_CONTEXT_TRACKING |
8c2c3df3 CM |
87 | help |
88 | ARM 64-bit (AArch64) Linux support. | |
89 | ||
90 | config 64BIT | |
91 | def_bool y | |
92 | ||
93 | config ARCH_PHYS_ADDR_T_64BIT | |
94 | def_bool y | |
95 | ||
96 | config MMU | |
97 | def_bool y | |
98 | ||
ce816fa8 | 99 | config NO_IOPORT_MAP |
d1e6dc91 | 100 | def_bool y if !PCI |
8c2c3df3 CM |
101 | |
102 | config STACKTRACE_SUPPORT | |
103 | def_bool y | |
104 | ||
105 | config LOCKDEP_SUPPORT | |
106 | def_bool y | |
107 | ||
108 | config TRACE_IRQFLAGS_SUPPORT | |
109 | def_bool y | |
110 | ||
c209f799 | 111 | config RWSEM_XCHGADD_ALGORITHM |
8c2c3df3 CM |
112 | def_bool y |
113 | ||
114 | config GENERIC_HWEIGHT | |
115 | def_bool y | |
116 | ||
117 | config GENERIC_CSUM | |
118 | def_bool y | |
119 | ||
120 | config GENERIC_CALIBRATE_DELAY | |
121 | def_bool y | |
122 | ||
19e7640d | 123 | config ZONE_DMA |
8c2c3df3 CM |
124 | def_bool y |
125 | ||
29e56940 SC |
126 | config HAVE_GENERIC_RCU_GUP |
127 | def_bool y | |
128 | ||
8c2c3df3 CM |
129 | config ARCH_DMA_ADDR_T_64BIT |
130 | def_bool y | |
131 | ||
132 | config NEED_DMA_MAP_STATE | |
133 | def_bool y | |
134 | ||
135 | config NEED_SG_DMA_LENGTH | |
136 | def_bool y | |
137 | ||
138 | config SWIOTLB | |
139 | def_bool y | |
140 | ||
141 | config IOMMU_HELPER | |
142 | def_bool SWIOTLB | |
143 | ||
4cfb3613 AB |
144 | config KERNEL_MODE_NEON |
145 | def_bool y | |
146 | ||
92cc15fc RH |
147 | config FIX_EARLYCON_MEM |
148 | def_bool y | |
149 | ||
9f25e6ad KS |
150 | config PGTABLE_LEVELS |
151 | int | |
152 | default 2 if ARM64_64K_PAGES && ARM64_VA_BITS_42 | |
153 | default 3 if ARM64_64K_PAGES && ARM64_VA_BITS_48 | |
154 | default 3 if ARM64_4K_PAGES && ARM64_VA_BITS_39 | |
155 | default 4 if ARM64_4K_PAGES && ARM64_VA_BITS_48 | |
156 | ||
8c2c3df3 CM |
157 | source "init/Kconfig" |
158 | ||
159 | source "kernel/Kconfig.freezer" | |
160 | ||
1ae90e79 CM |
161 | menu "Platform selection" |
162 | ||
6f56eef1 AA |
163 | config ARCH_EXYNOS |
164 | bool | |
165 | help | |
166 | This enables support for Samsung Exynos SoC family | |
167 | ||
168 | config ARCH_EXYNOS7 | |
169 | bool "ARMv8 based Samsung Exynos7" | |
170 | select ARCH_EXYNOS | |
171 | select COMMON_CLK_SAMSUNG | |
172 | select HAVE_S3C2410_WATCHDOG if WATCHDOG | |
173 | select HAVE_S3C_RTC if RTC_CLASS | |
174 | select PINCTRL | |
175 | select PINCTRL_EXYNOS | |
176 | ||
177 | help | |
178 | This enables support for Samsung Exynos7 SoC family | |
179 | ||
5118a6a3 OJ |
180 | config ARCH_FSL_LS2085A |
181 | bool "Freescale LS2085A SOC" | |
182 | help | |
183 | This enables support for Freescale LS2085A SOC. | |
184 | ||
4727a6f6 EH |
185 | config ARCH_MEDIATEK |
186 | bool "Mediatek MT65xx & MT81xx ARMv8 SoC" | |
187 | select ARM_GIC | |
0a233cdf | 188 | select PINCTRL |
4727a6f6 EH |
189 | help |
190 | Support for Mediatek MT65xx & MT81xx ARMv8 SoCs | |
191 | ||
d7f64a44 AK |
192 | config ARCH_QCOM |
193 | bool "Qualcomm Platforms" | |
194 | select PINCTRL | |
195 | help | |
196 | This enables support for the ARMv8 based Qualcomm chipsets. | |
197 | ||
41904360 SS |
198 | config ARCH_SEATTLE |
199 | bool "AMD Seattle SoC Family" | |
200 | help | |
201 | This enables support for AMD Seattle SOC Family | |
202 | ||
d035fdfa PW |
203 | config ARCH_TEGRA |
204 | bool "NVIDIA Tegra SoC Family" | |
205 | select ARCH_HAS_RESET_CONTROLLER | |
206 | select ARCH_REQUIRE_GPIOLIB | |
207 | select CLKDEV_LOOKUP | |
208 | select CLKSRC_MMIO | |
209 | select CLKSRC_OF | |
210 | select GENERIC_CLOCKEVENTS | |
211 | select HAVE_CLK | |
d035fdfa PW |
212 | select PINCTRL |
213 | select RESET_CONTROLLER | |
214 | help | |
215 | This enables support for the NVIDIA Tegra SoC family. | |
216 | ||
217 | config ARCH_TEGRA_132_SOC | |
218 | bool "NVIDIA Tegra132 SoC" | |
219 | depends on ARCH_TEGRA | |
220 | select PINCTRL_TEGRA124 | |
d035fdfa PW |
221 | select USB_ULPI if USB_PHY |
222 | select USB_ULPI_VIEWPORT if USB_PHY | |
223 | help | |
224 | Enable support for NVIDIA Tegra132 SoC, based on the Denver | |
225 | ARMv8 CPU. The Tegra132 SoC is similar to the Tegra124 SoC, | |
226 | but contains an NVIDIA Denver CPU complex in place of | |
227 | Tegra124's "4+1" Cortex-A15 CPU complex. | |
228 | ||
c4bb7995 ZZ |
229 | config ARCH_SPRD |
230 | bool "Spreadtrum SoC platform" | |
231 | help | |
232 | Support for Spreadtrum ARM based SoCs | |
233 | ||
28f7420d RMC |
234 | config ARCH_THUNDER |
235 | bool "Cavium Inc. Thunder SoC Family" | |
236 | help | |
237 | This enables support for Cavium's Thunder Family of SoCs. | |
238 | ||
1ae90e79 CM |
239 | config ARCH_VEXPRESS |
240 | bool "ARMv8 software model (Versatile Express)" | |
241 | select ARCH_REQUIRE_GPIOLIB | |
242 | select COMMON_CLK_VERSATILE | |
aa1e8ec1 | 243 | select POWER_RESET_VEXPRESS |
1ae90e79 CM |
244 | select VEXPRESS_CONFIG |
245 | help | |
246 | This enables support for the ARMv8 software model (Versatile | |
247 | Express). | |
8c2c3df3 | 248 | |
15942853 VK |
249 | config ARCH_XGENE |
250 | bool "AppliedMicro X-Gene SOC Family" | |
251 | help | |
252 | This enables support for AppliedMicro X-Gene SOC Family | |
253 | ||
5d1b79d2 MS |
254 | config ARCH_ZYNQMP |
255 | bool "Xilinx ZynqMP Family" | |
256 | help | |
257 | This enables support for Xilinx ZynqMP Family | |
258 | ||
8c2c3df3 CM |
259 | endmenu |
260 | ||
261 | menu "Bus support" | |
262 | ||
d1e6dc91 LD |
263 | config PCI |
264 | bool "PCI support" | |
265 | help | |
266 | This feature enables support for PCI bus system. If you say Y | |
267 | here, the kernel will include drivers and infrastructure code | |
268 | to support PCI bus devices. | |
269 | ||
270 | config PCI_DOMAINS | |
271 | def_bool PCI | |
272 | ||
273 | config PCI_DOMAINS_GENERIC | |
274 | def_bool PCI | |
275 | ||
276 | config PCI_SYSCALL | |
277 | def_bool PCI | |
278 | ||
279 | source "drivers/pci/Kconfig" | |
280 | source "drivers/pci/pcie/Kconfig" | |
281 | source "drivers/pci/hotplug/Kconfig" | |
282 | ||
8c2c3df3 CM |
283 | endmenu |
284 | ||
285 | menu "Kernel Features" | |
286 | ||
c0a01b84 AP |
287 | menu "ARM errata workarounds via the alternatives framework" |
288 | ||
289 | config ARM64_ERRATUM_826319 | |
290 | bool "Cortex-A53: 826319: System might deadlock if a write cannot complete until read data is accepted" | |
291 | default y | |
292 | help | |
293 | This option adds an alternative code sequence to work around ARM | |
294 | erratum 826319 on Cortex-A53 parts up to r0p2 with an AMBA 4 ACE or | |
295 | AXI master interface and an L2 cache. | |
296 | ||
297 | If a Cortex-A53 uses an AMBA AXI4 ACE interface to other processors | |
298 | and is unable to accept a certain write via this interface, it will | |
299 | not progress on read data presented on the read data channel and the | |
300 | system can deadlock. | |
301 | ||
302 | The workaround promotes data cache clean instructions to | |
303 | data cache clean-and-invalidate. | |
304 | Please note that this does not necessarily enable the workaround, | |
305 | as it depends on the alternative framework, which will only patch | |
306 | the kernel if an affected CPU is detected. | |
307 | ||
308 | If unsure, say Y. | |
309 | ||
310 | config ARM64_ERRATUM_827319 | |
311 | bool "Cortex-A53: 827319: Data cache clean instructions might cause overlapping transactions to the interconnect" | |
312 | default y | |
313 | help | |
314 | This option adds an alternative code sequence to work around ARM | |
315 | erratum 827319 on Cortex-A53 parts up to r0p2 with an AMBA 5 CHI | |
316 | master interface and an L2 cache. | |
317 | ||
318 | Under certain conditions this erratum can cause a clean line eviction | |
319 | to occur at the same time as another transaction to the same address | |
320 | on the AMBA 5 CHI interface, which can cause data corruption if the | |
321 | interconnect reorders the two transactions. | |
322 | ||
323 | The workaround promotes data cache clean instructions to | |
324 | data cache clean-and-invalidate. | |
325 | Please note that this does not necessarily enable the workaround, | |
326 | as it depends on the alternative framework, which will only patch | |
327 | the kernel if an affected CPU is detected. | |
328 | ||
329 | If unsure, say Y. | |
330 | ||
331 | config ARM64_ERRATUM_824069 | |
332 | bool "Cortex-A53: 824069: Cache line might not be marked as clean after a CleanShared snoop" | |
333 | default y | |
334 | help | |
335 | This option adds an alternative code sequence to work around ARM | |
336 | erratum 824069 on Cortex-A53 parts up to r0p2 when it is connected | |
337 | to a coherent interconnect. | |
338 | ||
339 | If a Cortex-A53 processor is executing a store or prefetch for | |
340 | write instruction at the same time as a processor in another | |
341 | cluster is executing a cache maintenance operation to the same | |
342 | address, then this erratum might cause a clean cache line to be | |
343 | incorrectly marked as dirty. | |
344 | ||
345 | The workaround promotes data cache clean instructions to | |
346 | data cache clean-and-invalidate. | |
347 | Please note that this option does not necessarily enable the | |
348 | workaround, as it depends on the alternative framework, which will | |
349 | only patch the kernel if an affected CPU is detected. | |
350 | ||
351 | If unsure, say Y. | |
352 | ||
353 | config ARM64_ERRATUM_819472 | |
354 | bool "Cortex-A53: 819472: Store exclusive instructions might cause data corruption" | |
355 | default y | |
356 | help | |
357 | This option adds an alternative code sequence to work around ARM | |
358 | erratum 819472 on Cortex-A53 parts up to r0p1 with an L2 cache | |
359 | present when it is connected to a coherent interconnect. | |
360 | ||
361 | If the processor is executing a load and store exclusive sequence at | |
362 | the same time as a processor in another cluster is executing a cache | |
363 | maintenance operation to the same address, then this erratum might | |
364 | cause data corruption. | |
365 | ||
366 | The workaround promotes data cache clean instructions to | |
367 | data cache clean-and-invalidate. | |
368 | Please note that this does not necessarily enable the workaround, | |
369 | as it depends on the alternative framework, which will only patch | |
370 | the kernel if an affected CPU is detected. | |
371 | ||
372 | If unsure, say Y. | |
373 | ||
374 | config ARM64_ERRATUM_832075 | |
375 | bool "Cortex-A57: 832075: possible deadlock on mixing exclusive memory accesses with device loads" | |
376 | default y | |
377 | help | |
378 | This option adds an alternative code sequence to work around ARM | |
379 | erratum 832075 on Cortex-A57 parts up to r1p2. | |
380 | ||
381 | Affected Cortex-A57 parts might deadlock when exclusive load/store | |
382 | instructions to Write-Back memory are mixed with Device loads. | |
383 | ||
384 | The workaround is to promote device loads to use Load-Acquire | |
385 | semantics. | |
386 | Please note that this does not necessarily enable the workaround, | |
387 | as it depends on the alternative framework, which will only patch | |
388 | the kernel if an affected CPU is detected. | |
389 | ||
390 | If unsure, say Y. | |
391 | ||
905e8c5d WD |
392 | config ARM64_ERRATUM_845719 |
393 | bool "Cortex-A53: 845719: a load might read incorrect data" | |
394 | depends on COMPAT | |
395 | default y | |
396 | help | |
397 | This option adds an alternative code sequence to work around ARM | |
398 | erratum 845719 on Cortex-A53 parts up to r0p4. | |
399 | ||
400 | When running a compat (AArch32) userspace on an affected Cortex-A53 | |
401 | part, a load at EL0 from a virtual address that matches the bottom 32 | |
402 | bits of the virtual address used by a recent load at (AArch64) EL1 | |
403 | might return incorrect data. | |
404 | ||
405 | The workaround is to write the contextidr_el1 register on exception | |
406 | return to a 32-bit task. | |
407 | Please note that this does not necessarily enable the workaround, | |
408 | as it depends on the alternative framework, which will only patch | |
409 | the kernel if an affected CPU is detected. | |
410 | ||
411 | If unsure, say Y. | |
412 | ||
c0a01b84 AP |
413 | endmenu |
414 | ||
415 | ||
e41ceed0 JL |
416 | choice |
417 | prompt "Page size" | |
418 | default ARM64_4K_PAGES | |
419 | help | |
420 | Page size (translation granule) configuration. | |
421 | ||
422 | config ARM64_4K_PAGES | |
423 | bool "4KB" | |
424 | help | |
425 | This feature enables 4KB pages support. | |
426 | ||
8c2c3df3 | 427 | config ARM64_64K_PAGES |
e41ceed0 | 428 | bool "64KB" |
8c2c3df3 CM |
429 | help |
430 | This feature enables 64KB pages support (4KB by default) | |
431 | allowing only two levels of page tables and faster TLB | |
432 | look-up. AArch32 emulation is not available when this feature | |
433 | is enabled. | |
434 | ||
e41ceed0 JL |
435 | endchoice |
436 | ||
437 | choice | |
438 | prompt "Virtual address space size" | |
439 | default ARM64_VA_BITS_39 if ARM64_4K_PAGES | |
440 | default ARM64_VA_BITS_42 if ARM64_64K_PAGES | |
441 | help | |
442 | Allows choosing one of multiple possible virtual address | |
443 | space sizes. The level of translation table is determined by | |
444 | a combination of page size and virtual address space size. | |
445 | ||
446 | config ARM64_VA_BITS_39 | |
447 | bool "39-bit" | |
448 | depends on ARM64_4K_PAGES | |
449 | ||
450 | config ARM64_VA_BITS_42 | |
451 | bool "42-bit" | |
452 | depends on ARM64_64K_PAGES | |
453 | ||
c79b954b JL |
454 | config ARM64_VA_BITS_48 |
455 | bool "48-bit" | |
c79b954b | 456 | |
e41ceed0 JL |
457 | endchoice |
458 | ||
459 | config ARM64_VA_BITS | |
460 | int | |
461 | default 39 if ARM64_VA_BITS_39 | |
462 | default 42 if ARM64_VA_BITS_42 | |
c79b954b | 463 | default 48 if ARM64_VA_BITS_48 |
e41ceed0 | 464 | |
a872013d WD |
465 | config CPU_BIG_ENDIAN |
466 | bool "Build big-endian kernel" | |
467 | help | |
468 | Say Y if you plan on running a kernel in big-endian mode. | |
469 | ||
8c2c3df3 CM |
470 | config SMP |
471 | bool "Symmetric Multi-Processing" | |
8c2c3df3 CM |
472 | help |
473 | This enables support for systems with more than one CPU. If | |
474 | you say N here, the kernel will run on single and | |
475 | multiprocessor machines, but will use only one CPU of a | |
476 | multiprocessor machine. If you say Y here, the kernel will run | |
477 | on many, but not all, single processor machines. On a single | |
478 | processor machine, the kernel will run faster if you say N | |
479 | here. | |
480 | ||
481 | If you don't know what to do here, say N. | |
482 | ||
f6e763b9 MB |
483 | config SCHED_MC |
484 | bool "Multi-core scheduler support" | |
485 | depends on SMP | |
486 | help | |
487 | Multi-core scheduler support improves the CPU scheduler's decision | |
488 | making when dealing with multi-core CPU chips at a cost of slightly | |
489 | increased overhead in some places. If unsure say N here. | |
490 | ||
491 | config SCHED_SMT | |
492 | bool "SMT scheduler support" | |
493 | depends on SMP | |
494 | help | |
495 | Improves the CPU scheduler's decision making when dealing with | |
496 | MultiThreading at a cost of slightly increased overhead in some | |
497 | places. If unsure say N here. | |
498 | ||
8c2c3df3 | 499 | config NR_CPUS |
62aa9655 GK |
500 | int "Maximum number of CPUs (2-4096)" |
501 | range 2 4096 | |
8c2c3df3 | 502 | depends on SMP |
15942853 | 503 | # These have to remain sorted largest to smallest |
e3672649 | 504 | default "64" |
8c2c3df3 | 505 | |
9327e2c6 MR |
506 | config HOTPLUG_CPU |
507 | bool "Support for hot-pluggable CPUs" | |
508 | depends on SMP | |
509 | help | |
510 | Say Y here to experiment with turning CPUs off and on. CPUs | |
511 | can be controlled through /sys/devices/system/cpu. | |
512 | ||
8c2c3df3 CM |
513 | source kernel/Kconfig.preempt |
514 | ||
137650aa MR |
515 | config UP_LATE_INIT |
516 | def_bool y | |
517 | depends on !SMP | |
518 | ||
8c2c3df3 CM |
519 | config HZ |
520 | int | |
521 | default 100 | |
522 | ||
523 | config ARCH_HAS_HOLES_MEMORYMODEL | |
524 | def_bool y if SPARSEMEM | |
525 | ||
526 | config ARCH_SPARSEMEM_ENABLE | |
527 | def_bool y | |
528 | select SPARSEMEM_VMEMMAP_ENABLE | |
529 | ||
530 | config ARCH_SPARSEMEM_DEFAULT | |
531 | def_bool ARCH_SPARSEMEM_ENABLE | |
532 | ||
533 | config ARCH_SELECT_MEMORY_MODEL | |
534 | def_bool ARCH_SPARSEMEM_ENABLE | |
535 | ||
536 | config HAVE_ARCH_PFN_VALID | |
537 | def_bool ARCH_HAS_HOLES_MEMORYMODEL || !SPARSEMEM | |
538 | ||
539 | config HW_PERF_EVENTS | |
540 | bool "Enable hardware performance counter support for perf events" | |
541 | depends on PERF_EVENTS | |
542 | default y | |
543 | help | |
544 | Enable hardware performance counter support for perf events. If | |
545 | disabled, perf events will use software events only. | |
546 | ||
084bd298 SC |
547 | config SYS_SUPPORTS_HUGETLBFS |
548 | def_bool y | |
549 | ||
550 | config ARCH_WANT_GENERAL_HUGETLB | |
551 | def_bool y | |
552 | ||
553 | config ARCH_WANT_HUGE_PMD_SHARE | |
554 | def_bool y if !ARM64_64K_PAGES | |
555 | ||
af074848 SC |
556 | config HAVE_ARCH_TRANSPARENT_HUGEPAGE |
557 | def_bool y | |
558 | ||
a41dc0e8 CM |
559 | config ARCH_HAS_CACHE_LINE_SIZE |
560 | def_bool y | |
561 | ||
8c2c3df3 CM |
562 | source "mm/Kconfig" |
563 | ||
a1ae65b2 AT |
564 | config SECCOMP |
565 | bool "Enable seccomp to safely compute untrusted bytecode" | |
566 | ---help--- | |
567 | This kernel feature is useful for number crunching applications | |
568 | that may need to compute untrusted bytecode during their | |
569 | execution. By using pipes or other transports made available to | |
570 | the process as file descriptors supporting the read/write | |
571 | syscalls, it's possible to isolate those applications in | |
572 | their own address space using seccomp. Once seccomp is | |
573 | enabled via prctl(PR_SET_SECCOMP), it cannot be disabled | |
574 | and the task is only allowed to execute a few safe syscalls | |
575 | defined by each seccomp mode. | |
576 | ||
aa42aa13 SS |
577 | config XEN_DOM0 |
578 | def_bool y | |
579 | depends on XEN | |
580 | ||
581 | config XEN | |
c2ba1f7d | 582 | bool "Xen guest support on ARM64" |
aa42aa13 | 583 | depends on ARM64 && OF |
83862ccf | 584 | select SWIOTLB_XEN |
aa42aa13 SS |
585 | help |
586 | Say Y if you want to run Linux in a Virtual Machine on Xen on ARM64. | |
587 | ||
d03bb145 SC |
588 | config FORCE_MAX_ZONEORDER |
589 | int | |
590 | default "14" if (ARM64_64K_PAGES && TRANSPARENT_HUGEPAGE) | |
591 | default "11" | |
592 | ||
1b907f46 WD |
593 | menuconfig ARMV8_DEPRECATED |
594 | bool "Emulate deprecated/obsolete ARMv8 instructions" | |
595 | depends on COMPAT | |
596 | help | |
597 | Legacy software support may require certain instructions | |
598 | that have been deprecated or obsoleted in the architecture. | |
599 | ||
600 | Enable this config to enable selective emulation of these | |
601 | features. | |
602 | ||
603 | If unsure, say Y | |
604 | ||
605 | if ARMV8_DEPRECATED | |
606 | ||
607 | config SWP_EMULATION | |
608 | bool "Emulate SWP/SWPB instructions" | |
609 | help | |
610 | ARMv8 obsoletes the use of A32 SWP/SWPB instructions such that | |
611 | they are always undefined. Say Y here to enable software | |
612 | emulation of these instructions for userspace using LDXR/STXR. | |
613 | ||
614 | In some older versions of glibc [<=2.8] SWP is used during futex | |
615 | trylock() operations with the assumption that the code will not | |
616 | be preempted. This invalid assumption may be more likely to fail | |
617 | with SWP emulation enabled, leading to deadlock of the user | |
618 | application. | |
619 | ||
620 | NOTE: when accessing uncached shared regions, LDXR/STXR rely | |
621 | on an external transaction monitoring block called a global | |
622 | monitor to maintain update atomicity. If your system does not | |
623 | implement a global monitor, this option can cause programs that | |
624 | perform SWP operations to uncached memory to deadlock. | |
625 | ||
626 | If unsure, say Y | |
627 | ||
628 | config CP15_BARRIER_EMULATION | |
629 | bool "Emulate CP15 Barrier instructions" | |
630 | help | |
631 | The CP15 barrier instructions - CP15ISB, CP15DSB, and | |
632 | CP15DMB - are deprecated in ARMv8 (and ARMv7). It is | |
633 | strongly recommended to use the ISB, DSB, and DMB | |
634 | instructions instead. | |
635 | ||
636 | Say Y here to enable software emulation of these | |
637 | instructions for AArch32 userspace code. When this option is | |
638 | enabled, CP15 barrier usage is traced which can help | |
639 | identify software that needs updating. | |
640 | ||
641 | If unsure, say Y | |
642 | ||
2d888f48 SP |
643 | config SETEND_EMULATION |
644 | bool "Emulate SETEND instruction" | |
645 | help | |
646 | The SETEND instruction alters the data-endianness of the | |
647 | AArch32 EL0, and is deprecated in ARMv8. | |
648 | ||
649 | Say Y here to enable software emulation of the instruction | |
650 | for AArch32 userspace code. | |
651 | ||
652 | Note: All the cpus on the system must have mixed endian support at EL0 | |
653 | for this feature to be enabled. If a new CPU - which doesn't support mixed | |
654 | endian - is hotplugged in after this feature has been enabled, there could | |
655 | be unexpected results in the applications. | |
656 | ||
657 | If unsure, say Y | |
1b907f46 WD |
658 | endif |
659 | ||
8c2c3df3 CM |
660 | endmenu |
661 | ||
662 | menu "Boot options" | |
663 | ||
664 | config CMDLINE | |
665 | string "Default kernel command string" | |
666 | default "" | |
667 | help | |
668 | Provide a set of default command-line options at build time by | |
669 | entering them here. As a minimum, you should specify the the | |
670 | root device (e.g. root=/dev/nfs). | |
671 | ||
672 | config CMDLINE_FORCE | |
673 | bool "Always use the default kernel command string" | |
674 | help | |
675 | Always use the default kernel command string, even if the boot | |
676 | loader passes other arguments to the kernel. | |
677 | This is useful if you cannot or don't want to change the | |
678 | command-line options your boot loader passes to the kernel. | |
679 | ||
f4f75ad5 AB |
680 | config EFI_STUB |
681 | bool | |
682 | ||
f84d0275 MS |
683 | config EFI |
684 | bool "UEFI runtime support" | |
685 | depends on OF && !CPU_BIG_ENDIAN | |
686 | select LIBFDT | |
687 | select UCS2_STRING | |
688 | select EFI_PARAMS_FROM_FDT | |
e15dd494 | 689 | select EFI_RUNTIME_WRAPPERS |
f4f75ad5 AB |
690 | select EFI_STUB |
691 | select EFI_ARMSTUB | |
f84d0275 MS |
692 | default y |
693 | help | |
694 | This option provides support for runtime services provided | |
695 | by UEFI firmware (such as non-volatile variables, realtime | |
3c7f2550 MS |
696 | clock, and platform reset). A UEFI stub is also provided to |
697 | allow the kernel to be booted as an EFI application. This | |
698 | is only useful on systems that have UEFI firmware. | |
f84d0275 | 699 | |
d1ae8c00 YL |
700 | config DMI |
701 | bool "Enable support for SMBIOS (DMI) tables" | |
702 | depends on EFI | |
703 | default y | |
704 | help | |
705 | This enables SMBIOS/DMI feature for systems. | |
706 | ||
707 | This option is only useful on systems that have UEFI firmware. | |
708 | However, even with this option, the resultant kernel should | |
709 | continue to boot on existing non-UEFI platforms. | |
710 | ||
8c2c3df3 CM |
711 | endmenu |
712 | ||
713 | menu "Userspace binary formats" | |
714 | ||
715 | source "fs/Kconfig.binfmt" | |
716 | ||
717 | config COMPAT | |
718 | bool "Kernel support for 32-bit EL0" | |
a8fcd8b1 | 719 | depends on !ARM64_64K_PAGES || EXPERT |
8c2c3df3 | 720 | select COMPAT_BINFMT_ELF |
af1839eb | 721 | select HAVE_UID16 |
84b9e9b4 | 722 | select OLD_SIGSUSPEND3 |
51682036 | 723 | select COMPAT_OLD_SIGACTION |
8c2c3df3 CM |
724 | help |
725 | This option enables support for a 32-bit EL0 running under a 64-bit | |
726 | kernel at EL1. AArch32-specific components such as system calls, | |
727 | the user helper functions, VFP support and the ptrace interface are | |
728 | handled appropriately by the kernel. | |
729 | ||
a8fcd8b1 AG |
730 | If you also enabled CONFIG_ARM64_64K_PAGES, please be aware that you |
731 | will only be able to execute AArch32 binaries that were compiled with | |
732 | 64k aligned segments. | |
733 | ||
8c2c3df3 CM |
734 | If you want to execute 32-bit userspace applications, say Y. |
735 | ||
736 | config SYSVIPC_COMPAT | |
737 | def_bool y | |
738 | depends on COMPAT && SYSVIPC | |
739 | ||
740 | endmenu | |
741 | ||
166936ba LP |
742 | menu "Power management options" |
743 | ||
744 | source "kernel/power/Kconfig" | |
745 | ||
746 | config ARCH_SUSPEND_POSSIBLE | |
747 | def_bool y | |
748 | ||
166936ba LP |
749 | endmenu |
750 | ||
1307220d LP |
751 | menu "CPU Power Management" |
752 | ||
753 | source "drivers/cpuidle/Kconfig" | |
754 | ||
52e7e816 RH |
755 | source "drivers/cpufreq/Kconfig" |
756 | ||
757 | endmenu | |
758 | ||
8c2c3df3 CM |
759 | source "net/Kconfig" |
760 | ||
761 | source "drivers/Kconfig" | |
762 | ||
f84d0275 MS |
763 | source "drivers/firmware/Kconfig" |
764 | ||
b6a02173 GG |
765 | source "drivers/acpi/Kconfig" |
766 | ||
8c2c3df3 CM |
767 | source "fs/Kconfig" |
768 | ||
c3eb5b14 MZ |
769 | source "arch/arm64/kvm/Kconfig" |
770 | ||
8c2c3df3 CM |
771 | source "arch/arm64/Kconfig.debug" |
772 | ||
773 | source "security/Kconfig" | |
774 | ||
775 | source "crypto/Kconfig" | |
2c98833a AB |
776 | if CRYPTO |
777 | source "arch/arm64/crypto/Kconfig" | |
778 | endif | |
8c2c3df3 CM |
779 | |
780 | source "lib/Kconfig" |