Commit | Line | Data |
---|---|---|
eed6b3eb OJ |
1 | menu "Platform selection" |
2 | ||
36b7c583 RJ |
3 | config ARCH_BCM_IPROC |
4 | bool "Broadcom iProc SoC Family" | |
5 | help | |
6 | This enables support for Broadcom iProc based SoCs | |
7 | ||
dd40fd92 JZ |
8 | config ARCH_BERLIN |
9 | bool "Marvell Berlin SoC Family" | |
10 | select DW_APB_ICTL | |
11 | help | |
12 | This enables support for Marvell Berlin SoC Family | |
13 | ||
eed6b3eb OJ |
14 | config ARCH_EXYNOS |
15 | bool | |
16 | help | |
17 | This enables support for Samsung Exynos SoC family | |
18 | ||
19 | config ARCH_EXYNOS7 | |
20 | bool "ARMv8 based Samsung Exynos7" | |
21 | select ARCH_EXYNOS | |
22 | select COMMON_CLK_SAMSUNG | |
23 | select HAVE_S3C2410_WATCHDOG if WATCHDOG | |
24 | select HAVE_S3C_RTC if RTC_CLASS | |
25 | select PINCTRL | |
26 | select PINCTRL_EXYNOS | |
27 | ||
28 | help | |
29 | This enables support for Samsung Exynos7 SoC family | |
30 | ||
31 | config ARCH_FSL_LS2085A | |
32 | bool "Freescale LS2085A SOC" | |
33 | help | |
34 | This enables support for Freescale LS2085A SOC. | |
35 | ||
36 | config ARCH_HISI | |
37 | bool "Hisilicon SoC Family" | |
38 | help | |
39 | This enables support for Hisilicon ARMv8 SoC family | |
40 | ||
41 | config ARCH_MEDIATEK | |
42 | bool "Mediatek MT65xx & MT81xx ARMv8 SoC" | |
43 | select ARM_GIC | |
44 | select PINCTRL | |
45 | help | |
46 | Support for Mediatek MT65xx & MT81xx ARMv8 SoCs | |
47 | ||
48 | config ARCH_QCOM | |
49 | bool "Qualcomm Platforms" | |
50 | select PINCTRL | |
51 | help | |
52 | This enables support for the ARMv8 based Qualcomm chipsets. | |
53 | ||
fbac1c81 HS |
54 | config ARCH_ROCKCHIP |
55 | bool "Rockchip Platforms" | |
56 | select ARCH_HAS_RESET_CONTROLLER | |
57 | select ARCH_REQUIRE_GPIOLIB | |
58 | select PINCTRL | |
59 | select PINCTRL_ROCKCHIP | |
60 | help | |
61 | This enables support for the ARMv8 based Rockchip chipsets, | |
62 | like the RK3368. | |
63 | ||
eed6b3eb OJ |
64 | config ARCH_SEATTLE |
65 | bool "AMD Seattle SoC Family" | |
66 | help | |
67 | This enables support for AMD Seattle SOC Family | |
68 | ||
69 | config ARCH_TEGRA | |
70 | bool "NVIDIA Tegra SoC Family" | |
71 | select ARCH_HAS_RESET_CONTROLLER | |
72 | select ARCH_REQUIRE_GPIOLIB | |
73 | select CLKDEV_LOOKUP | |
74 | select CLKSRC_MMIO | |
75 | select CLKSRC_OF | |
76 | select GENERIC_CLOCKEVENTS | |
77 | select HAVE_CLK | |
78 | select PINCTRL | |
79 | select RESET_CONTROLLER | |
80 | help | |
81 | This enables support for the NVIDIA Tegra SoC family. | |
82 | ||
83 | config ARCH_TEGRA_132_SOC | |
84 | bool "NVIDIA Tegra132 SoC" | |
85 | depends on ARCH_TEGRA | |
86 | select PINCTRL_TEGRA124 | |
87 | select USB_ULPI if USB_PHY | |
88 | select USB_ULPI_VIEWPORT if USB_PHY | |
89 | help | |
90 | Enable support for NVIDIA Tegra132 SoC, based on the Denver | |
91 | ARMv8 CPU. The Tegra132 SoC is similar to the Tegra124 SoC, | |
92 | but contains an NVIDIA Denver CPU complex in place of | |
93 | Tegra124's "4+1" Cortex-A15 CPU complex. | |
94 | ||
95 | config ARCH_SPRD | |
96 | bool "Spreadtrum SoC platform" | |
97 | help | |
98 | Support for Spreadtrum ARM based SoCs | |
99 | ||
100 | config ARCH_THUNDER | |
101 | bool "Cavium Inc. Thunder SoC Family" | |
102 | help | |
103 | This enables support for Cavium's Thunder Family of SoCs. | |
104 | ||
105 | config ARCH_VEXPRESS | |
106 | bool "ARMv8 software model (Versatile Express)" | |
107 | select ARCH_REQUIRE_GPIOLIB | |
108 | select COMMON_CLK_VERSATILE | |
109 | select POWER_RESET_VEXPRESS | |
110 | select VEXPRESS_CONFIG | |
111 | help | |
112 | This enables support for the ARMv8 software model (Versatile | |
113 | Express). | |
114 | ||
115 | config ARCH_XGENE | |
116 | bool "AppliedMicro X-Gene SOC Family" | |
117 | help | |
118 | This enables support for AppliedMicro X-Gene SOC Family | |
119 | ||
120 | config ARCH_ZYNQMP | |
121 | bool "Xilinx ZynqMP Family" | |
122 | help | |
123 | This enables support for Xilinx ZynqMP Family | |
124 | ||
125 | endmenu |