[deliverable/linux.git] / arch / arm64 / boot / dts / apm / apm-shadowcat.dtsi

/*
 * dts file for AppliedMicro (APM) X-Gene Shadowcat SOC
 *
 * Copyright (C) 2015, Applied Micro Circuits Corporation
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 */

/ {
	compatible = "apm,xgene-shadowcat";
	interrupt-parent = <&gic>;
	#address-cells = <2>;
	#size-cells = <2>;

	cpus {
		#address-cells = <2>;
		#size-cells = <0>;

		cpu@000 {
			device_type = "cpu";
			compatible = "apm,strega", "arm,armv8";
			reg = <0x0 0x000>;
			enable-method = "spin-table";
			cpu-release-addr = <0x1 0x0000fff8>;
		};
		cpu@001 {
			device_type = "cpu";
			compatible = "apm,strega", "arm,armv8";
			reg = <0x0 0x001>;
			enable-method = "spin-table";
			cpu-release-addr = <0x1 0x0000fff8>;
		};
		cpu@100 {
			device_type = "cpu";
			compatible = "apm,strega", "arm,armv8";
			reg = <0x0 0x100>;
			enable-method = "spin-table";
			cpu-release-addr = <0x1 0x0000fff8>;
		};
		cpu@101 {
			device_type = "cpu";
			compatible = "apm,strega", "arm,armv8";
			reg = <0x0 0x101>;
			enable-method = "spin-table";
			cpu-release-addr = <0x1 0x0000fff8>;
		};
		cpu@200 {
			device_type = "cpu";
			compatible = "apm,strega", "arm,armv8";
			reg = <0x0 0x200>;
			enable-method = "spin-table";
			cpu-release-addr = <0x1 0x0000fff8>;
		};
		cpu@201 {
			device_type = "cpu";
			compatible = "apm,strega", "arm,armv8";
			reg = <0x0 0x201>;
			enable-method = "spin-table";
			cpu-release-addr = <0x1 0x0000fff8>;
		};
		cpu@300 {
			device_type = "cpu";
			compatible = "apm,strega", "arm,armv8";
			reg = <0x0 0x300>;
			enable-method = "spin-table";
			cpu-release-addr = <0x1 0x0000fff8>;
		};
		cpu@301 {
			device_type = "cpu";
			compatible = "apm,strega", "arm,armv8";
			reg = <0x0 0x301>;
			enable-method = "spin-table";
			cpu-release-addr = <0x1 0x0000fff8>;
		};
	};

	gic: interrupt-controller@78090000 {
		compatible = "arm,cortex-a15-gic";
		#interrupt-cells = <3>;
		#address-cells = <2>;
		#size-cells = <2>;
		interrupt-controller;
		interrupts = <1 9 0xf04>;	/* GIC Maintenence IRQ */
		ranges = <0 0 0 0x79000000 0x0 0x800000>; /* MSI Range */
		reg = <0x0 0x78090000 0x0 0x10000>,	/* GIC Dist */
		      <0x0 0x780A0000 0x0 0x20000>,	/* GIC CPU */
		      <0x0 0x780C0000 0x0 0x10000>,	/* GIC VCPU Control */
		      <0x0 0x780E0000 0x0 0x20000>;	/* GIC VCPU */
	};

	pmu {
		compatible = "arm,armv8-pmuv3";
		interrupts = <1 12 0xff04>;
	};

	timer {
		compatible = "arm,armv8-timer";
		interrupts = <1 0 0xff04>,	/* Secure Phys IRQ */
			     <1 13 0xff04>,	/* Non-secure Phys IRQ */
			     <1 14 0xff04>,	/* Virt IRQ */
			     <1 15 0xff04>;	/* Hyp IRQ */
		clock-frequency = <50000000>;
	};

	soc {
		compatible = "simple-bus";
		#address-cells = <2>;
		#size-cells = <2>;
		ranges;

		clocks {
			#address-cells = <2>;
			#size-cells = <2>;
			ranges;

			refclk: refclk {
				compatible = "fixed-clock";
				#clock-cells = <1>;
				clock-frequency = <100000000>;
				clock-output-names = "refclk";
			};

			socpll: socpll@17000120 {
				compatible = "apm,xgene-socpll-clock";
				#clock-cells = <1>;
				clocks = <&refclk 0>;
				reg = <0x0 0x17000120 0x0 0x1000>;
				clock-output-names = "socpll";
			};

			socplldiv2: socplldiv2  {
				compatible = "fixed-factor-clock";
				#clock-cells = <1>;
				clocks = <&socpll 0>;
				clock-mult = <1>;
				clock-div = <2>;
				clock-output-names = "socplldiv2";
			};

			ahbclk: ahbclk@1f2ac000 {
				compatible = "apm,xgene-device-clock";
				#clock-cells = <1>;
				clocks = <&socplldiv2 0>;
				reg = <0x0 0x1f2ac000 0x0 0x1000
					0x0 0x17000000 0x0 0x2000>;
				reg-names = "csr-reg", "div-reg";
				csr-offset = <0x0>;
				csr-mask = <0x1>;
				enable-offset = <0x8>;
				enable-mask = <0x1>;
				divider-offset = <0x164>;
				divider-width = <0x5>;
				divider-shift = <0x0>;
				clock-output-names = "ahbclk";
			};

			sdioclk: sdioclk@1f2ac000 {
				compatible = "apm,xgene-device-clock";
				#clock-cells = <1>;
				clocks = <&socplldiv2 0>;
				reg = <0x0 0x1f2ac000 0x0 0x1000
					0x0 0x17000000 0x0 0x2000>;
				reg-names = "csr-reg", "div-reg";
				csr-offset = <0x0>;
				csr-mask = <0x2>;
				enable-offset = <0x8>;
				enable-mask = <0x2>;
				divider-offset = <0x178>;
				divider-width = <0x8>;
				divider-shift = <0x0>;
				clock-output-names = "sdioclk";
			};

			pcie0clk: pcie0clk@1f2bc000 {
				compatible = "apm,xgene-device-clock";
				#clock-cells = <1>;
				clocks = <&socplldiv2 0>;
				reg = <0x0 0x1f2bc000 0x0 0x1000>;
				reg-names = "csr-reg";
				clock-output-names = "pcie0clk";
			};

			xge0clk: xge0clk@1f61c000 {
				compatible = "apm,xgene-device-clock";
				#clock-cells = <1>;
				clocks = <&socplldiv2 0>;
				reg = <0x0 0x1f61c000 0x0 0x1000>;
				reg-names = "csr-reg";
				enable-mask = <0x3>;
				csr-mask = <0x3>;
				clock-output-names = "xge0clk";
			};

			xge1clk: xge1clk@1f62c000 {
				compatible = "apm,xgene-device-clock";
				#clock-cells = <1>;
				clocks = <&socplldiv2 0>;
				reg = <0x0 0x1f62c000 0x0 0x1000>;
				reg-names = "csr-reg";
				enable-mask = <0x3>;
				csr-mask = <0x3>;
				clock-output-names = "xge1clk";
			};
		};

		scu: system-clk-controller@17000000 {
			compatible = "apm,xgene-scu","syscon";
			reg = <0x0 0x17000000 0x0 0x400>;
		};

		reboot: reboot@17000014 {
			compatible = "syscon-reboot";
			regmap = <&scu>;
			offset = <0x14>;
			mask = <0x1>;
		};

		serial0: serial@10600000 {
			device_type = "serial";
			compatible = "ns16550";
			reg = <0 0x10600000 0x0 0x1000>;
			reg-shift = <2>;
			clock-frequency = <10000000>;
			interrupt-parent = <&gic>;
			interrupts = <0x0 0x4c 0x4>;
		};

		sata1: sata@1a000000 {
			compatible = "apm,xgene-ahci";
			reg = <0x0 0x1a000000 0x0 0x1000>,
			      <0x0 0x1f200000 0x0 0x1000>,
			      <0x0 0x1f20d000 0x0 0x1000>,
			      <0x0 0x1f20e000 0x0 0x1000>;
			interrupts = <0x0 0x5a 0x4>;
			dma-coherent;
		};

		sata2: sata@1a200000 {
			compatible = "apm,xgene-ahci";
			reg = <0x0 0x1a200000 0x0 0x1000>,
			      <0x0 0x1f210000 0x0 0x1000>,
			      <0x0 0x1f21d000 0x0 0x1000>,
			      <0x0 0x1f21e000 0x0 0x1000>;
			interrupts = <0x0 0x5b 0x4>;
			dma-coherent;
		};

		sata3: sata@1a400000 {
			compatible = "apm,xgene-ahci";
			reg = <0x0 0x1a400000 0x0 0x1000>,
			      <0x0 0x1f220000 0x0 0x1000>,
			      <0x0 0x1f22d000 0x0 0x1000>,
			      <0x0 0x1f22e000 0x0 0x1000>;
			interrupts = <0x0 0x5c 0x4>;
			dma-coherent;
		};

		mmc0: mmc@1c000000 {
			compatible = "arasan,sdhci-4.9a";
			reg = <0x0 0x1c000000 0x0 0x100>;
			interrupts = <0x0 0x49 0x4>;
			dma-coherent;
			no-1-8-v;
			clock-names = "clk_xin", "clk_ahb";
			clocks = <&sdioclk 0>, <&ahbclk 0>;
		};

		sbgpio: sbgpio@17001000{
			compatible = "apm,xgene-gpio-sb";
			reg = <0x0 0x17001000 0x0 0x400>;
			#gpio-cells = <2>;
			gpio-controller;
			interrupts = <0x0 0x28 0x1>,
				     <0x0 0x29 0x1>,
				     <0x0 0x2a 0x1>,
				     <0x0 0x2b 0x1>,
				     <0x0 0x2c 0x1>,
				     <0x0 0x2d 0x1>,
				     <0x0 0x2e 0x1>,
				     <0x0 0x2f 0x1>;
		};

		sgenet0: ethernet@1f610000 {
			compatible = "apm,xgene2-sgenet";
			status = "disabled";
			reg = <0x0 0x1f610000 0x0 0x10000>,
			      <0x0 0x1f600000 0x0 0Xd100>,
			      <0x0 0x20000000 0x0 0X20000>;
			interrupts = <0 96 4>,
				     <0 97 4>;
			dma-coherent;
			clocks = <&xge0clk 0>;
			local-mac-address = [00 01 73 00 00 01];
			phy-connection-type = "sgmii";
		};

		xgenet1: ethernet@1f620000 {
			compatible = "apm,xgene2-xgenet";
			status = "disabled";
			reg = <0x0 0x1f620000 0x0 0x10000>,
			      <0x0 0x1f600000 0x0 0Xd100>,
			      <0x0 0x20000000 0x0 0X220000>;
			interrupts = <0 108 4>,
				     <0 109 4>;
			port-id = <1>;
			dma-coherent;
			clocks = <&xge1clk 0>;
			local-mac-address = [00 01 73 00 00 02];
			phy-connection-type = "xgmii";
		};
	};
};
Commit	Line	Data
e144dc5b FK	1	/*
	2	* dts file for AppliedMicro (APM) X-Gene Shadowcat SOC
	3	*
	4	* Copyright (C) 2015, Applied Micro Circuits Corporation
	5	*
	6	* This program is free software; you can redistribute it and/or
	7	* modify it under the terms of the GNU General Public License as
	8	* published by the Free Software Foundation; either version 2 of
	9	* the License, or (at your option) any later version.
	10	*/
	11
	12	/ {
	13	compatible = "apm,xgene-shadowcat";
	14	interrupt-parent = <&gic>;
	15	#address-cells = <2>;
	16	#size-cells = <2>;
	17
	18	cpus {
	19	#address-cells = <2>;
	20	#size-cells = <0>;
	21
	22	cpu@000 {
	23	device_type = "cpu";
	24	compatible = "apm,strega", "arm,armv8";
	25	reg = <0x0 0x000>;
	26	enable-method = "spin-table";
	27	cpu-release-addr = <0x1 0x0000fff8>;
	28	};
	29	cpu@001 {
	30	device_type = "cpu";
	31	compatible = "apm,strega", "arm,armv8";
	32	reg = <0x0 0x001>;
	33	enable-method = "spin-table";
	34	cpu-release-addr = <0x1 0x0000fff8>;
	35	};
	36	cpu@100 {
	37	device_type = "cpu";
	38	compatible = "apm,strega", "arm,armv8";
	39	reg = <0x0 0x100>;
	40	enable-method = "spin-table";
	41	cpu-release-addr = <0x1 0x0000fff8>;
	42	};
	43	cpu@101 {
	44	device_type = "cpu";
	45	compatible = "apm,strega", "arm,armv8";
	46	reg = <0x0 0x101>;
	47	enable-method = "spin-table";
	48	cpu-release-addr = <0x1 0x0000fff8>;
	49	};
	50	cpu@200 {
	51	device_type = "cpu";
	52	compatible = "apm,strega", "arm,armv8";
	53	reg = <0x0 0x200>;
	54	enable-method = "spin-table";
	55	cpu-release-addr = <0x1 0x0000fff8>;
	56	};
	57	cpu@201 {
	58	device_type = "cpu";
	59	compatible = "apm,strega", "arm,armv8";
	60	reg = <0x0 0x201>;
	61	enable-method = "spin-table";
	62	cpu-release-addr = <0x1 0x0000fff8>;
	63	};
	64	cpu@300 {
65	device_type = "cpu";
66	compatible = "apm,strega", "arm,armv8";
67	reg = <0x0 0x300>;
68	enable-method = "spin-table";
69	cpu-release-addr = <0x1 0x0000fff8>;
70	};
71	cpu@301 {
72	device_type = "cpu";
73	compatible = "apm,strega", "arm,armv8";
74	reg = <0x0 0x301>;
75	enable-method = "spin-table";
76	cpu-release-addr = <0x1 0x0000fff8>;
77	};
78	};
79
80	gic: interrupt-controller@78090000 {
81	compatible = "arm,cortex-a15-gic";
82	#interrupt-cells = <3>;
83	#address-cells = <2>;
84	#size-cells = <2>;
85	interrupt-controller;
86	interrupts = <1 9 0xf04>; /* GIC Maintenence IRQ */
87	ranges = <0 0 0 0x79000000 0x0 0x800000>; /* MSI Range */
88	reg = <0x0 0x78090000 0x0 0x10000>, /* GIC Dist */
89	<0x0 0x780A0000 0x0 0x20000>, /* GIC CPU */
90	<0x0 0x780C0000 0x0 0x10000>, /* GIC VCPU Control */
91	<0x0 0x780E0000 0x0 0x20000>; /* GIC VCPU */
92	};
93
94	pmu {
95	compatible = "arm,armv8-pmuv3";
96	interrupts = <1 12 0xff04>;
97	};
98
99	timer {
100	compatible = "arm,armv8-timer";
101	interrupts = <1 0 0xff04>, /* Secure Phys IRQ */
102	<1 13 0xff04>, /* Non-secure Phys IRQ */
103	<1 14 0xff04>, /* Virt IRQ */
104	<1 15 0xff04>; /* Hyp IRQ */
105	clock-frequency = <50000000>;
106	};
107
108	soc {
109	compatible = "simple-bus";
110	#address-cells = <2>;
111	#size-cells = <2>;
112	ranges;
113
114	clocks {
115	#address-cells = <2>;
116	#size-cells = <2>;
117	ranges;
118
119	refclk: refclk {
120	compatible = "fixed-clock";
121	#clock-cells = <1>;
122	clock-frequency = <100000000>;
123	clock-output-names = "refclk";
124	};
125
126	socpll: socpll@17000120 {
127	compatible = "apm,xgene-socpll-clock";
128	#clock-cells = <1>;
129	clocks = <&refclk 0>;
130	reg = <0x0 0x17000120 0x0 0x1000>;
131	clock-output-names = "socpll";
132	};
133
134	socplldiv2: socplldiv2 {
135	compatible = "fixed-factor-clock";
136	#clock-cells = <1>;
137	clocks = <&socpll 0>;
138	clock-mult = <1>;
139	clock-div = <2>;
140	clock-output-names = "socplldiv2";
141	};
142
0ae8c000 DD	143	ahbclk: ahbclk@1f2ac000 {
	144	compatible = "apm,xgene-device-clock";
	145	#clock-cells = <1>;
	146	clocks = <&socplldiv2 0>;
	147	reg = <0x0 0x1f2ac000 0x0 0x1000
	148	0x0 0x17000000 0x0 0x2000>;
	149	reg-names = "csr-reg", "div-reg";
	150	csr-offset = <0x0>;
	151	csr-mask = <0x1>;
	152	enable-offset = <0x8>;
	153	enable-mask = <0x1>;
	154	divider-offset = <0x164>;
	155	divider-width = <0x5>;
	156	divider-shift = <0x0>;
	157	clock-output-names = "ahbclk";
	158	};
	159
	160	sdioclk: sdioclk@1f2ac000 {
	161	compatible = "apm,xgene-device-clock";
	162	#clock-cells = <1>;
	163	clocks = <&socplldiv2 0>;
	164	reg = <0x0 0x1f2ac000 0x0 0x1000
	165	0x0 0x17000000 0x0 0x2000>;
	166	reg-names = "csr-reg", "div-reg";
	167	csr-offset = <0x0>;
	168	csr-mask = <0x2>;
	169	enable-offset = <0x8>;
	170	enable-mask = <0x2>;
	171	divider-offset = <0x178>;
	172	divider-width = <0x8>;
	173	divider-shift = <0x0>;
	174	clock-output-names = "sdioclk";
	175	};
	176
e144dc5b FK	177	pcie0clk: pcie0clk@1f2bc000 {
	178	compatible = "apm,xgene-device-clock";
	179	#clock-cells = <1>;
	180	clocks = <&socplldiv2 0>;
	181	reg = <0x0 0x1f2bc000 0x0 0x1000>;
	182	reg-names = "csr-reg";
	183	clock-output-names = "pcie0clk";
	184	};
	185
	186	xge0clk: xge0clk@1f61c000 {
	187	compatible = "apm,xgene-device-clock";
	188	#clock-cells = <1>;
	189	clocks = <&socplldiv2 0>;
	190	reg = <0x0 0x1f61c000 0x0 0x1000>;
	191	reg-names = "csr-reg";
	192	enable-mask = <0x3>;
	193	csr-mask = <0x3>;
	194	clock-output-names = "xge0clk";
	195	};
	196
	197	xge1clk: xge1clk@1f62c000 {
	198	compatible = "apm,xgene-device-clock";
	199	#clock-cells = <1>;
	200	clocks = <&socplldiv2 0>;
	201	reg = <0x0 0x1f62c000 0x0 0x1000>;
	202	reg-names = "csr-reg";
	203	enable-mask = <0x3>;
	204	csr-mask = <0x3>;
	205	clock-output-names = "xge1clk";
	206	};
	207	};
	208
991c1292 DD	209	scu: system-clk-controller@17000000 {
	210	compatible = "apm,xgene-scu","syscon";
	211	reg = <0x0 0x17000000 0x0 0x400>;
	212	};
	213
	214	reboot: reboot@17000014 {
	215	compatible = "syscon-reboot";
	216	regmap = <&scu>;
	217	offset = <0x14>;
	218	mask = <0x1>;
	219	};
	220
e144dc5b FK	221	serial0: serial@10600000 {
	222	device_type = "serial";
	223	compatible = "ns16550";
	224	reg = <0 0x10600000 0x0 0x1000>;
	225	reg-shift = <2>;
	226	clock-frequency = <10000000>;
	227	interrupt-parent = <&gic>;
	228	interrupts = <0x0 0x4c 0x4>;
	229	};
	230
	231	sata1: sata@1a000000 {
	232	compatible = "apm,xgene-ahci";
	233	reg = <0x0 0x1a000000 0x0 0x1000>,
	234	<0x0 0x1f200000 0x0 0x1000>,
	235	<0x0 0x1f20d000 0x0 0x1000>,
	236	<0x0 0x1f20e000 0x0 0x1000>;
	237	interrupts = <0x0 0x5a 0x4>;
	238	dma-coherent;
	239	};
	240
	241	sata2: sata@1a200000 {
	242	compatible = "apm,xgene-ahci";
	243	reg = <0x0 0x1a200000 0x0 0x1000>,
	244	<0x0 0x1f210000 0x0 0x1000>,
	245	<0x0 0x1f21d000 0x0 0x1000>,
	246	<0x0 0x1f21e000 0x0 0x1000>;
	247	interrupts = <0x0 0x5b 0x4>;
	248	dma-coherent;
	249	};
	250
	251	sata3: sata@1a400000 {
	252	compatible = "apm,xgene-ahci";
	253	reg = <0x0 0x1a400000 0x0 0x1000>,
	254	<0x0 0x1f220000 0x0 0x1000>,
	255	<0x0 0x1f22d000 0x0 0x1000>,
	256	<0x0 0x1f22e000 0x0 0x1000>;
	257	interrupts = <0x0 0x5c 0x4>;
	258	dma-coherent;
	259	};
	260
0ae8c000 DD	261	mmc0: mmc@1c000000 {
	262	compatible = "arasan,sdhci-4.9a";
	263	reg = <0x0 0x1c000000 0x0 0x100>;
	264	interrupts = <0x0 0x49 0x4>;
	265	dma-coherent;
	266	no-1-8-v;
	267	clock-names = "clk_xin", "clk_ahb";
	268	clocks = <&sdioclk 0>, <&ahbclk 0>;
	269	};
	270
5fc86b51 DD	271	sbgpio: sbgpio@17001000{
	272	compatible = "apm,xgene-gpio-sb";
	273	reg = <0x0 0x17001000 0x0 0x400>;
	274	#gpio-cells = <2>;
	275	gpio-controller;
	276	interrupts = <0x0 0x28 0x1>,
	277	<0x0 0x29 0x1>,
	278	<0x0 0x2a 0x1>,
	279	<0x0 0x2b 0x1>,
	280	<0x0 0x2c 0x1>,
	281	<0x0 0x2d 0x1>,
	282	<0x0 0x2e 0x1>,
	283	<0x0 0x2f 0x1>;
	284	};
	285
e144dc5b FK	286	sgenet0: ethernet@1f610000 {
	287	compatible = "apm,xgene2-sgenet";
	288	status = "disabled";
	289	reg = <0x0 0x1f610000 0x0 0x10000>,
	290	<0x0 0x1f600000 0x0 0Xd100>,
	291	<0x0 0x20000000 0x0 0X20000>;
	292	interrupts = <0 96 4>,
	293	<0 97 4>;
	294	dma-coherent;
	295	clocks = <&xge0clk 0>;
	296	local-mac-address = [00 01 73 00 00 01];
	297	phy-connection-type = "sgmii";
	298	};
	299
	300	xgenet1: ethernet@1f620000 {
	301	compatible = "apm,xgene2-xgenet";
	302	status = "disabled";
	303	reg = <0x0 0x1f620000 0x0 0x10000>,
	304	<0x0 0x1f600000 0x0 0Xd100>,
	305	<0x0 0x20000000 0x0 0X220000>;
	306	interrupts = <0 108 4>,
	307	<0 109 4>;
	308	port-id = <1>;
	309	dma-coherent;
	310	clocks = <&xge1clk 0>;
	311	local-mac-address = [00 01 73 00 00 02];
	312	phy-connection-type = "xgmii";
	313	};
	314	};
	315	};