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arm64: dts: X-Gene v1: I2C0 clock is always on
[deliverable/linux.git] / arch / arm64 / boot / dts / apm / apm-shadowcat.dtsi
CommitLineData
e144dc5b
FK		 1/*
2 * dts file for AppliedMicro (APM) X-Gene Shadowcat SOC
3 *
4 * Copyright (C) 2015, Applied Micro Circuits Corporation
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License as
8 * published by the Free Software Foundation; either version 2 of
9 * the License, or (at your option) any later version.
10 */
11
12/ {
13 compatible = "apm,xgene-shadowcat";
14 interrupt-parent = <&gic>;
15 #address-cells = <2>;
16 #size-cells = <2>;
17
18 cpus {
19 #address-cells = <2>;
20 #size-cells = <0>;
21
22 cpu@000 {
23 device_type = "cpu";
24 compatible = "apm,strega", "arm,armv8";
25 reg = <0x0 0x000>;
26 enable-method = "spin-table";
27 cpu-release-addr = <0x1 0x0000fff8>;
8000bc3f 28 next-level-cache = <&xgene_L2_0>;
e144dc5b
FK		 29 };
30 cpu@001 {
31 device_type = "cpu";
32 compatible = "apm,strega", "arm,armv8";
33 reg = <0x0 0x001>;
34 enable-method = "spin-table";
35 cpu-release-addr = <0x1 0x0000fff8>;
8000bc3f 36 next-level-cache = <&xgene_L2_0>;
e144dc5b
FK		 37 };
38 cpu@100 {
39 device_type = "cpu";
40 compatible = "apm,strega", "arm,armv8";
41 reg = <0x0 0x100>;
42 enable-method = "spin-table";
43 cpu-release-addr = <0x1 0x0000fff8>;
8000bc3f 44 next-level-cache = <&xgene_L2_1>;
e144dc5b
FK		 45 };
46 cpu@101 {
47 device_type = "cpu";
48 compatible = "apm,strega", "arm,armv8";
49 reg = <0x0 0x101>;
50 enable-method = "spin-table";
51 cpu-release-addr = <0x1 0x0000fff8>;
8000bc3f 52 next-level-cache = <&xgene_L2_1>;
e144dc5b
FK		 53 };
54 cpu@200 {
55 device_type = "cpu";
56 compatible = "apm,strega", "arm,armv8";
57 reg = <0x0 0x200>;
58 enable-method = "spin-table";
59 cpu-release-addr = <0x1 0x0000fff8>;
8000bc3f 60 next-level-cache = <&xgene_L2_2>;
e144dc5b
FK		 61 };
62 cpu@201 {
63 device_type = "cpu";
64 compatible = "apm,strega", "arm,armv8";
65 reg = <0x0 0x201>;
66 enable-method = "spin-table";
67 cpu-release-addr = <0x1 0x0000fff8>;
8000bc3f 68 next-level-cache = <&xgene_L2_2>;
e144dc5b
FK		 69 };
70 cpu@300 {
71 device_type = "cpu";
72 compatible = "apm,strega", "arm,armv8";
73 reg = <0x0 0x300>;
74 enable-method = "spin-table";
75 cpu-release-addr = <0x1 0x0000fff8>;
8000bc3f 76 next-level-cache = <&xgene_L2_3>;
e144dc5b
FK		 77 };
78 cpu@301 {
79 device_type = "cpu";
80 compatible = "apm,strega", "arm,armv8";
81 reg = <0x0 0x301>;
82 enable-method = "spin-table";
83 cpu-release-addr = <0x1 0x0000fff8>;
8000bc3f
DD		 84 next-level-cache = <&xgene_L2_3>;
85 };
86 xgene_L2_0: l2-cache-0 {
87 compatible = "cache";
88 };
89 xgene_L2_1: l2-cache-1 {
90 compatible = "cache";
91 };
92 xgene_L2_2: l2-cache-2 {
93 compatible = "cache";
94 };
95 xgene_L2_3: l2-cache-3 {
96 compatible = "cache";
e144dc5b
FK		 97 };
98 };
99
100 gic: interrupt-controller@78090000 {
101 compatible = "arm,cortex-a15-gic";
102 #interrupt-cells = <3>;
103 #address-cells = <2>;
104 #size-cells = <2>;
105 interrupt-controller;
106 interrupts = <1 9 0xf04>; /* GIC Maintenence IRQ */
107 ranges = <0 0 0 0x79000000 0x0 0x800000>; /* MSI Range */
108 reg = <0x0 0x78090000 0x0 0x10000>, /* GIC Dist */
109 <0x0 0x780A0000 0x0 0x20000>, /* GIC CPU */
110 <0x0 0x780C0000 0x0 0x10000>, /* GIC VCPU Control */
111 <0x0 0x780E0000 0x0 0x20000>; /* GIC VCPU */
726e92fd
DD		 112 v2m0: v2m@0x00000 {
113 compatible = "arm,gic-v2m-frame";
114 msi-controller;
115 reg = <0x0 0x0 0x0 0x1000>;
116 };
117 v2m1: v2m@0x10000 {
118 compatible = "arm,gic-v2m-frame";
119 msi-controller;
120 reg = <0x0 0x10000 0x0 0x1000>;
121 };
122 v2m2: v2m@0x20000 {
123 compatible = "arm,gic-v2m-frame";
124 msi-controller;
125 reg = <0x0 0x20000 0x0 0x1000>;
126 };
127 v2m3: v2m@0x30000 {
128 compatible = "arm,gic-v2m-frame";
129 msi-controller;
130 reg = <0x0 0x30000 0x0 0x1000>;
131 };
132 v2m4: v2m@0x40000 {
133 compatible = "arm,gic-v2m-frame";
134 msi-controller;
135 reg = <0x0 0x40000 0x0 0x1000>;
136 };
137 v2m5: v2m@0x50000 {
138 compatible = "arm,gic-v2m-frame";
139 msi-controller;
140 reg = <0x0 0x50000 0x0 0x1000>;
141 };
142 v2m6: v2m@0x60000 {
143 compatible = "arm,gic-v2m-frame";
144 msi-controller;
145 reg = <0x0 0x60000 0x0 0x1000>;
146 };
147 v2m7: v2m@0x70000 {
148 compatible = "arm,gic-v2m-frame";
149 msi-controller;
150 reg = <0x0 0x70000 0x0 0x1000>;
151 };
152 v2m8: v2m@0x80000 {
153 compatible = "arm,gic-v2m-frame";
154 msi-controller;
155 reg = <0x0 0x80000 0x0 0x1000>;
156 };
157 v2m9: v2m@0x90000 {
158 compatible = "arm,gic-v2m-frame";
159 msi-controller;
160 reg = <0x0 0x90000 0x0 0x1000>;
161 };
162 v2m10: v2m@0xA0000 {
163 compatible = "arm,gic-v2m-frame";
164 msi-controller;
165 reg = <0x0 0xA0000 0x0 0x1000>;
166 };
167 v2m11: v2m@0xB0000 {
168 compatible = "arm,gic-v2m-frame";
169 msi-controller;
170 reg = <0x0 0xB0000 0x0 0x1000>;
171 };
172 v2m12: v2m@0xC0000 {
173 compatible = "arm,gic-v2m-frame";
174 msi-controller;
175 reg = <0x0 0xC0000 0x0 0x1000>;
176 };
177 v2m13: v2m@0xD0000 {
178 compatible = "arm,gic-v2m-frame";
179 msi-controller;
180 reg = <0x0 0xD0000 0x0 0x1000>;
181 };
182 v2m14: v2m@0xE0000 {
183 compatible = "arm,gic-v2m-frame";
184 msi-controller;
185 reg = <0x0 0xE0000 0x0 0x1000>;
186 };
187 v2m15: v2m@0xF0000 {
188 compatible = "arm,gic-v2m-frame";
189 msi-controller;
190 reg = <0x0 0xF0000 0x0 0x1000>;
191 };
e144dc5b
FK		 192 };
193
194 pmu {
195 compatible = "arm,armv8-pmuv3";
196 interrupts = <1 12 0xff04>;
197 };
198
199 timer {
200 compatible = "arm,armv8-timer";
201 interrupts = <1 0 0xff04>, /* Secure Phys IRQ */
202 <1 13 0xff04>, /* Non-secure Phys IRQ */
203 <1 14 0xff04>, /* Virt IRQ */
204 <1 15 0xff04>; /* Hyp IRQ */
205 clock-frequency = <50000000>;
206 };
207
208 soc {
209 compatible = "simple-bus";
210 #address-cells = <2>;
211 #size-cells = <2>;
212 ranges;
213
214 clocks {
215 #address-cells = <2>;
216 #size-cells = <2>;
217 ranges;
218
219 refclk: refclk {
220 compatible = "fixed-clock";
221 #clock-cells = <1>;
222 clock-frequency = <100000000>;
223 clock-output-names = "refclk";
224 };
225
226 socpll: socpll@17000120 {
227 compatible = "apm,xgene-socpll-clock";
228 #clock-cells = <1>;
229 clocks = <&refclk 0>;
230 reg = <0x0 0x17000120 0x0 0x1000>;
231 clock-output-names = "socpll";
232 };
233
234 socplldiv2: socplldiv2 {
235 compatible = "fixed-factor-clock";
236 #clock-cells = <1>;
237 clocks = <&socpll 0>;
238 clock-mult = <1>;
239 clock-div = <2>;
240 clock-output-names = "socplldiv2";
241 };
242
b0e7a85a 243 ahbclk: ahbclk@17000000 {
0ae8c000
DD		 244 compatible = "apm,xgene-device-clock";
245 #clock-cells = <1>;
246 clocks = <&socplldiv2 0>;
b0e7a85a
DD		 247 reg = <0x0 0x17000000 0x0 0x2000>;
248 reg-names = "div-reg";
0ae8c000
DD		 249 divider-offset = <0x164>;
250 divider-width = <0x5>;
251 divider-shift = <0x0>;
252 clock-output-names = "ahbclk";
253 };
254
d0181354
DD		 255 sbapbclk: sbapbclk@1704c000 {
256 compatible = "apm,xgene-device-clock";
257 #clock-cells = <1>;
258 clocks = <&ahbclk 0>;
259 reg = <0x0 0x1704c000 0x0 0x2000>;
260 reg-names = "div-reg";
261 divider-offset = <0x10>;
262 divider-width = <0x2>;
263 divider-shift = <0x0>;
264 clock-output-names = "sbapbclk";
265 };
266
0ae8c000
DD		 267 sdioclk: sdioclk@1f2ac000 {
268 compatible = "apm,xgene-device-clock";
269 #clock-cells = <1>;
270 clocks = <&socplldiv2 0>;
271 reg = <0x0 0x1f2ac000 0x0 0x1000
272 0x0 0x17000000 0x0 0x2000>;
273 reg-names = "csr-reg", "div-reg";
274 csr-offset = <0x0>;
275 csr-mask = <0x2>;
276 enable-offset = <0x8>;
277 enable-mask = <0x2>;
278 divider-offset = <0x178>;
279 divider-width = <0x8>;
280 divider-shift = <0x0>;
281 clock-output-names = "sdioclk";
282 };
283
e144dc5b
FK		 284 pcie0clk: pcie0clk@1f2bc000 {
285 compatible = "apm,xgene-device-clock";
286 #clock-cells = <1>;
287 clocks = <&socplldiv2 0>;
288 reg = <0x0 0x1f2bc000 0x0 0x1000>;
289 reg-names = "csr-reg";
290 clock-output-names = "pcie0clk";
291 };
292
b055e9de
DD		 293 pcie1clk: pcie1clk@1f2cc000 {
294 compatible = "apm,xgene-device-clock";
295 #clock-cells = <1>;
296 clocks = <&socplldiv2 0>;
297 reg = <0x0 0x1f2cc000 0x0 0x1000>;
298 reg-names = "csr-reg";
299 clock-output-names = "pcie1clk";
300 };
301
e144dc5b
FK		 302 xge0clk: xge0clk@1f61c000 {
303 compatible = "apm,xgene-device-clock";
304 #clock-cells = <1>;
305 clocks = <&socplldiv2 0>;
306 reg = <0x0 0x1f61c000 0x0 0x1000>;
307 reg-names = "csr-reg";
308 enable-mask = <0x3>;
309 csr-mask = <0x3>;
310 clock-output-names = "xge0clk";
311 };
312
313 xge1clk: xge1clk@1f62c000 {
314 compatible = "apm,xgene-device-clock";
315 #clock-cells = <1>;
316 clocks = <&socplldiv2 0>;
317 reg = <0x0 0x1f62c000 0x0 0x1000>;
318 reg-names = "csr-reg";
319 enable-mask = <0x3>;
320 csr-mask = <0x3>;
321 clock-output-names = "xge1clk";
322 };
e6ae03c4
DD		 323
324 rngpkaclk: rngpkaclk@17000000 {
325 compatible = "apm,xgene-device-clock";
326 #clock-cells = <1>;
327 clocks = <&socplldiv2 0>;
328 reg = <0x0 0x17000000 0x0 0x2000>;
329 reg-names = "csr-reg";
330 csr-offset = <0xc>;
331 csr-mask = <0x10>;
332 enable-offset = <0x10>;
333 enable-mask = <0x10>;
334 clock-output-names = "rngpkaclk";
335 };
d0181354
DD		 336
337 i2c1clk: i2c1clk@17000000 {
338 compatible = "apm,xgene-device-clock";
339 #clock-cells = <1>;
340 clocks = <&sbapbclk 0>;
341 reg = <0x0 0x17000000 0x0 0x2000>;
342 reg-names = "csr-reg";
343 csr-offset = <0xc>;
344 csr-mask = <0x4>;
345 enable-offset = <0x10>;
346 enable-mask = <0x4>;
347 clock-output-names = "i2c1clk";
348 };
349
350 i2c4clk: i2c4clk@1704c000 {
351 compatible = "apm,xgene-device-clock";
352 #clock-cells = <1>;
353 clocks = <&sbapbclk 0>;
354 reg = <0x0 0x1704c000 0x0 0x1000>;
355 reg-names = "csr-reg";
356 csr-offset = <0x0>;
357 csr-mask = <0x40>;
358 enable-offset = <0x8>;
359 enable-mask = <0x40>;
360 clock-output-names = "i2c4clk";
361 };
e144dc5b
FK		 362 };
363
991c1292
DD		 364 scu: system-clk-controller@17000000 {
365 compatible = "apm,xgene-scu","syscon";
366 reg = <0x0 0x17000000 0x0 0x400>;
367 };
368
369 reboot: reboot@17000014 {
370 compatible = "syscon-reboot";
371 regmap = <&scu>;
372 offset = <0x14>;
373 mask = <0x1>;
374 };
375
1a47bc82
DD		 376 csw: csw@7e200000 {
377 compatible = "apm,xgene-csw", "syscon";
378 reg = <0x0 0x7e200000 0x0 0x1000>;
379 };
380
381 mcba: mcba@7e700000 {
382 compatible = "apm,xgene-mcb", "syscon";
383 reg = <0x0 0x7e700000 0x0 0x1000>;
384 };
385
386 mcbb: mcbb@7e720000 {
387 compatible = "apm,xgene-mcb", "syscon";
388 reg = <0x0 0x7e720000 0x0 0x1000>;
389 };
390
391 efuse: efuse@1054a000 {
392 compatible = "apm,xgene-efuse", "syscon";
393 reg = <0x0 0x1054a000 0x0 0x20>;
394 };
395
396 edac@78800000 {
397 compatible = "apm,xgene-edac";
398 #address-cells = <2>;
399 #size-cells = <2>;
400 ranges;
401 regmap-csw = <&csw>;
402 regmap-mcba = <&mcba>;
403 regmap-mcbb = <&mcbb>;
404 regmap-efuse = <&efuse>;
405 reg = <0x0 0x78800000 0x0 0x100>;
406 interrupts = <0x0 0x20 0x4>,
407 <0x0 0x21 0x4>,
408 <0x0 0x27 0x4>;
409
410 edacmc@7e800000 {
411 compatible = "apm,xgene-edac-mc";
412 reg = <0x0 0x7e800000 0x0 0x1000>;
413 memory-controller = <0>;
414 };
415
416 edacmc@7e840000 {
417 compatible = "apm,xgene-edac-mc";
418 reg = <0x0 0x7e840000 0x0 0x1000>;
419 memory-controller = <1>;
420 };
421
422 edacmc@7e880000 {
423 compatible = "apm,xgene-edac-mc";
424 reg = <0x0 0x7e880000 0x0 0x1000>;
425 memory-controller = <2>;
426 };
427
428 edacmc@7e8c0000 {
429 compatible = "apm,xgene-edac-mc";
430 reg = <0x0 0x7e8c0000 0x0 0x1000>;
431 memory-controller = <3>;
432 };
433
434 edacpmd@7c000000 {
435 compatible = "apm,xgene-edac-pmd";
436 reg = <0x0 0x7c000000 0x0 0x200000>;
437 pmd-controller = <0>;
438 };
439
440 edacpmd@7c200000 {
441 compatible = "apm,xgene-edac-pmd";
442 reg = <0x0 0x7c200000 0x0 0x200000>;
443 pmd-controller = <1>;
444 };
445
446 edacpmd@7c400000 {
447 compatible = "apm,xgene-edac-pmd";
448 reg = <0x0 0x7c400000 0x0 0x200000>;
449 pmd-controller = <2>;
450 };
451
452 edacpmd@7c600000 {
453 compatible = "apm,xgene-edac-pmd";
454 reg = <0x0 0x7c600000 0x0 0x200000>;
455 pmd-controller = <3>;
456 };
457
458 edacl3@7e600000 {
459 compatible = "apm,xgene-edac-l3-v2";
460 reg = <0x0 0x7e600000 0x0 0x1000>;
461 };
462
463 edacsoc@7e930000 {
464 compatible = "apm,xgene-edac-soc";
465 reg = <0x0 0x7e930000 0x0 0x1000>;
466 };
467 };
468
e144dc5b
FK		 469 serial0: serial@10600000 {
470 device_type = "serial";
471 compatible = "ns16550";
472 reg = <0 0x10600000 0x0 0x1000>;
473 reg-shift = <2>;
474 clock-frequency = <10000000>;
475 interrupt-parent = <&gic>;
476 interrupts = <0x0 0x4c 0x4>;
477 };
478
93beff2c 479 /* Do not change dwusb name, coded for backward compatibility */
30fd9d51
DD		 480 usb0: dwusb@19000000 {
481 status = "disabled";
482 compatible = "snps,dwc3";
483 reg = <0x0 0x19000000 0x0 0x100000>;
484 interrupts = <0x0 0x5d 0x4>;
485 dma-coherent;
486 dr_mode = "host";
487 };
488
b055e9de
DD		 489 pcie0: pcie@1f2b0000 {
490 status = "disabled";
491 device_type = "pci";
492 compatible = "apm,xgene-pcie", "apm,xgene2-pcie";
493 #interrupt-cells = <1>;
494 #size-cells = <2>;
495 #address-cells = <3>;
496 reg = < 0x00 0x1f2b0000 0x0 0x00010000 /* Controller registers */
497 0xc0 0xd0000000 0x0 0x00040000>; /* PCI config space */
498 reg-names = "csr", "cfg";
499 ranges = <0x01000000 0x00 0x00000000 0xc0 0x10000000 0x00 0x00010000 /* io */
500 0x02000000 0x00 0x20000000 0xc1 0x20000000 0x00 0x20000000 /* mem */
501 0x43000000 0xe0 0x00000000 0xe0 0x00000000 0x20 0x00000000>; /* mem */
502 dma-ranges = <0x42000000 0x80 0x00000000 0x80 0x00000000 0x00 0x80000000
503 0x42000000 0x00 0x00000000 0x00 0x00000000 0x80 0x00000000>;
504 interrupt-map-mask = <0x0 0x0 0x0 0x7>;
505 interrupt-map = <0x0 0x0 0x0 0x1 &gic 0x0 0x0 0x0 0x10 0x1
506 0x0 0x0 0x0 0x2 &gic 0x0 0x0 0x0 0x11 0x1
507 0x0 0x0 0x0 0x3 &gic 0x0 0x0 0x0 0x12 0x1
508 0x0 0x0 0x0 0x4 &gic 0x0 0x0 0x0 0x13 0x1>;
509 dma-coherent;
510 clocks = <&pcie0clk 0>;
511 msi-parent = <&v2m0>;
512 };
513
514 pcie1: pcie@1f2c0000 {
515 status = "disabled";
516 device_type = "pci";
517 compatible = "apm,xgene-pcie", "apm,xgene2-pcie";
518 #interrupt-cells = <1>;
519 #size-cells = <2>;
520 #address-cells = <3>;
521 reg = < 0x00 0x1f2c0000 0x0 0x00010000 /* Controller registers */
522 0xa0 0xd0000000 0x0 0x00040000>; /* PCI config space */
523 reg-names = "csr", "cfg";
524 ranges = <0x01000000 0x00 0x00000000 0xa0 0x10000000 0x00 0x00010000 /* io */
525 0x02000000 0x00 0x20000000 0xa1 0x20000000 0x00 0x20000000 /* mem */
526 0x43000000 0xb0 0x00000000 0xb0 0x00000000 0x10 0x00000000>; /* mem */
527 dma-ranges = <0x42000000 0x80 0x00000000 0x80 0x00000000 0x00 0x80000000
528 0x42000000 0x00 0x00000000 0x00 0x00000000 0x80 0x00000000>;
529 interrupt-map-mask = <0x0 0x0 0x0 0x7>;
530 interrupt-map = <0x0 0x0 0x0 0x1 &gic 0x0 0x0 0x0 0x16 0x1
531 0x0 0x0 0x0 0x2 &gic 0x0 0x0 0x0 0x17 0x1
532 0x0 0x0 0x0 0x3 &gic 0x0 0x0 0x0 0x18 0x1
533 0x0 0x0 0x0 0x4 &gic 0x0 0x0 0x0 0x19 0x1>;
534 dma-coherent;
535 clocks = <&pcie1clk 0>;
536 msi-parent = <&v2m0>;
537 };
538
e144dc5b
FK		 539 sata1: sata@1a000000 {
540 compatible = "apm,xgene-ahci";
541 reg = <0x0 0x1a000000 0x0 0x1000>,
542 <0x0 0x1f200000 0x0 0x1000>,
543 <0x0 0x1f20d000 0x0 0x1000>,
544 <0x0 0x1f20e000 0x0 0x1000>;
545 interrupts = <0x0 0x5a 0x4>;
546 dma-coherent;
547 };
548
549 sata2: sata@1a200000 {
550 compatible = "apm,xgene-ahci";
551 reg = <0x0 0x1a200000 0x0 0x1000>,
552 <0x0 0x1f210000 0x0 0x1000>,
553 <0x0 0x1f21d000 0x0 0x1000>,
554 <0x0 0x1f21e000 0x0 0x1000>;
555 interrupts = <0x0 0x5b 0x4>;
556 dma-coherent;
557 };
558
559 sata3: sata@1a400000 {
560 compatible = "apm,xgene-ahci";
561 reg = <0x0 0x1a400000 0x0 0x1000>,
562 <0x0 0x1f220000 0x0 0x1000>,
563 <0x0 0x1f22d000 0x0 0x1000>,
564 <0x0 0x1f22e000 0x0 0x1000>;
565 interrupts = <0x0 0x5c 0x4>;
566 dma-coherent;
567 };
568
0ae8c000
DD		 569 mmc0: mmc@1c000000 {
570 compatible = "arasan,sdhci-4.9a";
571 reg = <0x0 0x1c000000 0x0 0x100>;
572 interrupts = <0x0 0x49 0x4>;
573 dma-coherent;
574 no-1-8-v;
575 clock-names = "clk_xin", "clk_ahb";
576 clocks = <&sdioclk 0>, <&ahbclk 0>;
577 };
578
93beff2c 579 gfcgpio: gpio@1f63c000 {
9e81a200
DD		 580 compatible = "apm,xgene-gpio";
581 reg = <0x0 0x1f63c000 0x0 0x40>;
582 gpio-controller;
583 #gpio-cells = <2>;
584 };
585
93beff2c 586 dwgpio: gpio@1c024000 {
9ba6739d
DD		 587 compatible = "snps,dw-apb-gpio";
588 reg = <0x0 0x1c024000 0x0 0x1000>;
589 reg-io-width = <4>;
590 #address-cells = <1>;
591 #size-cells = <0>;
592
593 porta: gpio-controller@0 {
594 compatible = "snps,dw-apb-gpio-port";
595 gpio-controller;
596 snps,nr-gpios = <32>;
597 reg = <0>;
598 };
599 };
600
93beff2c 601 sbgpio: gpio@17001000{
5fc86b51
DD		 602 compatible = "apm,xgene-gpio-sb";
603 reg = <0x0 0x17001000 0x0 0x400>;
604 #gpio-cells = <2>;
605 gpio-controller;
606 interrupts = <0x0 0x28 0x1>,
607 <0x0 0x29 0x1>,
608 <0x0 0x2a 0x1>,
609 <0x0 0x2b 0x1>,
610 <0x0 0x2c 0x1>,
611 <0x0 0x2d 0x1>,
612 <0x0 0x2e 0x1>,
613 <0x0 0x2f 0x1>;
614 };
615
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FK		 616 sgenet0: ethernet@1f610000 {
617 compatible = "apm,xgene2-sgenet";
618 status = "disabled";
619 reg = <0x0 0x1f610000 0x0 0x10000>,
620 <0x0 0x1f600000 0x0 0Xd100>,
621 <0x0 0x20000000 0x0 0X20000>;
622 interrupts = <0 96 4>,
623 <0 97 4>;
624 dma-coherent;
625 clocks = <&xge0clk 0>;
626 local-mac-address = [00 01 73 00 00 01];
627 phy-connection-type = "sgmii";
628 };
629
630 xgenet1: ethernet@1f620000 {
631 compatible = "apm,xgene2-xgenet";
632 status = "disabled";
633 reg = <0x0 0x1f620000 0x0 0x10000>,
634 <0x0 0x1f600000 0x0 0Xd100>,
635 <0x0 0x20000000 0x0 0X220000>;
636 interrupts = <0 108 4>,
637 <0 109 4>;
638 port-id = <1>;
639 dma-coherent;
640 clocks = <&xge1clk 0>;
641 local-mac-address = [00 01 73 00 00 02];
642 phy-connection-type = "xgmii";
643 };
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DD		 644
645 rng: rng@10520000 {
646 compatible = "apm,xgene-rng";
647 reg = <0x0 0x10520000 0x0 0x100>;
648 interrupts = <0x0 0x41 0x4>;
649 clocks = <&rngpkaclk 0>;
650 };
d0181354 651
93beff2c 652 i2c1: i2c@10511000 {
d0181354
DD		 653 #address-cells = <1>;
654 #size-cells = <0>;
655 compatible = "snps,designware-i2c";
656 reg = <0x0 0x10511000 0x0 0x1000>;
657 interrupts = <0 0x45 0x4>;
658 #clock-cells = <1>;
659 clocks = <&i2c1clk 0>;
660 bus_num = <1>;
661 };
662
93beff2c 663 i2c4: i2c@10640000 {
d0181354
DD		 664 #address-cells = <1>;
665 #size-cells = <0>;
666 compatible = "snps,designware-i2c";
667 reg = <0x0 0x10640000 0x0 0x1000>;
668 interrupts = <0 0x3A 0x4>;
669 clocks = <&i2c4clk 0>;
670 bus_num = <4>;
671 };
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FK		 672 };
673};
Linux kernel - Deliverables
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