[deliverable/linux.git] / arch / arm64 / boot / dts / apm / apm-storm.dtsi

/*
 * dts file for AppliedMicro (APM) X-Gene Storm SOC
 *
 * Copyright (C) 2013, Applied Micro Circuits Corporation
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 */

/ {
	compatible = "apm,xgene-storm";
	interrupt-parent = <&gic>;
	#address-cells = <2>;
	#size-cells = <2>;

	cpus {
		#address-cells = <2>;
		#size-cells = <0>;

		cpu@000 {
			device_type = "cpu";
			compatible = "apm,potenza", "arm,armv8";
			reg = <0x0 0x000>;
			enable-method = "spin-table";
			cpu-release-addr = <0x1 0x0000fff8>;
		};
		cpu@001 {
			device_type = "cpu";
			compatible = "apm,potenza", "arm,armv8";
			reg = <0x0 0x001>;
			enable-method = "spin-table";
			cpu-release-addr = <0x1 0x0000fff8>;
		};
		cpu@100 {
			device_type = "cpu";
			compatible = "apm,potenza", "arm,armv8";
			reg = <0x0 0x100>;
			enable-method = "spin-table";
			cpu-release-addr = <0x1 0x0000fff8>;
		};
		cpu@101 {
			device_type = "cpu";
			compatible = "apm,potenza", "arm,armv8";
			reg = <0x0 0x101>;
			enable-method = "spin-table";
			cpu-release-addr = <0x1 0x0000fff8>;
		};
		cpu@200 {
			device_type = "cpu";
			compatible = "apm,potenza", "arm,armv8";
			reg = <0x0 0x200>;
			enable-method = "spin-table";
			cpu-release-addr = <0x1 0x0000fff8>;
		};
		cpu@201 {
			device_type = "cpu";
			compatible = "apm,potenza", "arm,armv8";
			reg = <0x0 0x201>;
			enable-method = "spin-table";
			cpu-release-addr = <0x1 0x0000fff8>;
		};
		cpu@300 {
			device_type = "cpu";
			compatible = "apm,potenza", "arm,armv8";
			reg = <0x0 0x300>;
			enable-method = "spin-table";
			cpu-release-addr = <0x1 0x0000fff8>;
		};
		cpu@301 {
			device_type = "cpu";
			compatible = "apm,potenza", "arm,armv8";
			reg = <0x0 0x301>;
			enable-method = "spin-table";
			cpu-release-addr = <0x1 0x0000fff8>;
		};
	};

	gic: interrupt-controller@78010000 {
		compatible = "arm,cortex-a15-gic";
		#interrupt-cells = <3>;
		interrupt-controller;
		reg = <0x0 0x78010000 0x0 0x1000>,	/* GIC Dist */
		      <0x0 0x78020000 0x0 0x1000>,	/* GIC CPU */
		      <0x0 0x78040000 0x0 0x2000>,	/* GIC VCPU Control */
		      <0x0 0x78060000 0x0 0x2000>;	/* GIC VCPU */
		interrupts = <1 9 0xf04>;	/* GIC Maintenence IRQ */
	};

	timer {
		compatible = "arm,armv8-timer";
		interrupts = <1 0 0xff01>,	/* Secure Phys IRQ */
			     <1 13 0xff01>,	/* Non-secure Phys IRQ */
			     <1 14 0xff01>,	/* Virt IRQ */
			     <1 15 0xff01>;	/* Hyp IRQ */
		clock-frequency = <50000000>;
	};

	soc {
		compatible = "simple-bus";
		#address-cells = <2>;
		#size-cells = <2>;
		ranges;

		clocks {
			#address-cells = <2>;
			#size-cells = <2>;
			ranges;
			refclk: refclk {
				compatible = "fixed-clock";
				#clock-cells = <1>;
				clock-frequency = <100000000>;
				clock-output-names = "refclk";
			};

			pcppll: pcppll@17000100 {
				compatible = "apm,xgene-pcppll-clock";
				#clock-cells = <1>;
				clocks = <&refclk 0>;
				clock-names = "pcppll";
				reg = <0x0 0x17000100 0x0 0x1000>;
				clock-output-names = "pcppll";
				type = <0>;
			};

			socpll: socpll@17000120 {
				compatible = "apm,xgene-socpll-clock";
				#clock-cells = <1>;
				clocks = <&refclk 0>;
				clock-names = "socpll";
				reg = <0x0 0x17000120 0x0 0x1000>;
				clock-output-names = "socpll";
				type = <1>;
			};

			socplldiv2: socplldiv2  {
				compatible = "fixed-factor-clock";
				#clock-cells = <1>;
				clocks = <&socpll 0>;
				clock-names = "socplldiv2";
				clock-mult = <1>;
				clock-div = <2>;
				clock-output-names = "socplldiv2";
			};

			qmlclk: qmlclk {
				compatible = "apm,xgene-device-clock";
				#clock-cells = <1>;
				clocks = <&socplldiv2 0>;
				clock-names = "qmlclk";
				reg = <0x0 0x1703C000 0x0 0x1000>;
				reg-names = "csr-reg";
				clock-output-names = "qmlclk";
			};

			ethclk: ethclk {
				compatible = "apm,xgene-device-clock";
				#clock-cells = <1>;
				clocks = <&socplldiv2 0>;
				clock-names = "ethclk";
				reg = <0x0 0x17000000 0x0 0x1000>;
				reg-names = "div-reg";
				divider-offset = <0x238>;
				divider-width = <0x9>;
				divider-shift = <0x0>;
				clock-output-names = "ethclk";
			};

			menetclk: menetclk {
				compatible = "apm,xgene-device-clock";
				#clock-cells = <1>;
				clocks = <&ethclk 0>;
				reg = <0x0 0x1702C000 0x0 0x1000>;
				reg-names = "csr-reg";
				clock-output-names = "menetclk";
			};

			sge0clk: sge0clk@1f21c000 {
				compatible = "apm,xgene-device-clock";
				#clock-cells = <1>;
				clocks = <&socplldiv2 0>;
				reg = <0x0 0x1f21c000 0x0 0x1000>;
				reg-names = "csr-reg";
				csr-mask = <0x3>;
				clock-output-names = "sge0clk";
			};

			sge1clk: sge1clk@1f21c000 {
				compatible = "apm,xgene-device-clock";
				#clock-cells = <1>;
				clocks = <&socplldiv2 0>;
				reg = <0x0 0x1f21c000 0x0 0x1000>;
				reg-names = "csr-reg";
				csr-mask = <0xc>;
				clock-output-names = "sge1clk";
			};

			xge0clk: xge0clk@1f61c000 {
				compatible = "apm,xgene-device-clock";
				#clock-cells = <1>;
				clocks = <&socplldiv2 0>;
				reg = <0x0 0x1f61c000 0x0 0x1000>;
				reg-names = "csr-reg";
				csr-mask = <0x3>;
				clock-output-names = "xge0clk";
			};

			sataphy1clk: sataphy1clk@1f21c000 {
				compatible = "apm,xgene-device-clock";
				#clock-cells = <1>;
				clocks = <&socplldiv2 0>;
				reg = <0x0 0x1f21c000 0x0 0x1000>;
				reg-names = "csr-reg";
				clock-output-names = "sataphy1clk";
				status = "disabled";
				csr-offset = <0x4>;
				csr-mask = <0x00>;
				enable-offset = <0x0>;
				enable-mask = <0x06>;
			};

			sataphy2clk: sataphy1clk@1f22c000 {
				compatible = "apm,xgene-device-clock";
				#clock-cells = <1>;
				clocks = <&socplldiv2 0>;
				reg = <0x0 0x1f22c000 0x0 0x1000>;
				reg-names = "csr-reg";
				clock-output-names = "sataphy2clk";
				status = "ok";
				csr-offset = <0x4>;
				csr-mask = <0x3a>;
				enable-offset = <0x0>;
				enable-mask = <0x06>;
			};

			sataphy3clk: sataphy1clk@1f23c000 {
				compatible = "apm,xgene-device-clock";
				#clock-cells = <1>;
				clocks = <&socplldiv2 0>;
				reg = <0x0 0x1f23c000 0x0 0x1000>;
				reg-names = "csr-reg";
				clock-output-names = "sataphy3clk";
				status = "ok";
				csr-offset = <0x4>;
				csr-mask = <0x3a>;
				enable-offset = <0x0>;
				enable-mask = <0x06>;
			};

			sata01clk: sata01clk@1f21c000 {
				compatible = "apm,xgene-device-clock";
				#clock-cells = <1>;
				clocks = <&socplldiv2 0>;
				reg = <0x0 0x1f21c000 0x0 0x1000>;
				reg-names = "csr-reg";
				clock-output-names = "sata01clk";
				csr-offset = <0x4>;
				csr-mask = <0x05>;
				enable-offset = <0x0>;
				enable-mask = <0x39>;
			};

			sata23clk: sata23clk@1f22c000 {
				compatible = "apm,xgene-device-clock";
				#clock-cells = <1>;
				clocks = <&socplldiv2 0>;
				reg = <0x0 0x1f22c000 0x0 0x1000>;
				reg-names = "csr-reg";
				clock-output-names = "sata23clk";
				csr-offset = <0x4>;
				csr-mask = <0x05>;
				enable-offset = <0x0>;
				enable-mask = <0x39>;
			};

			sata45clk: sata45clk@1f23c000 {
				compatible = "apm,xgene-device-clock";
				#clock-cells = <1>;
				clocks = <&socplldiv2 0>;
				reg = <0x0 0x1f23c000 0x0 0x1000>;
				reg-names = "csr-reg";
				clock-output-names = "sata45clk";
				csr-offset = <0x4>;
				csr-mask = <0x05>;
				enable-offset = <0x0>;
				enable-mask = <0x39>;
			};

			rtcclk: rtcclk@17000000 {
				compatible = "apm,xgene-device-clock";
				#clock-cells = <1>;
				clocks = <&socplldiv2 0>;
				reg = <0x0 0x17000000 0x0 0x2000>;
				reg-names = "csr-reg";
				csr-offset = <0xc>;
				csr-mask = <0x2>;
				enable-offset = <0x10>;
				enable-mask = <0x2>;
				clock-output-names = "rtcclk";
			};

			rngpkaclk: rngpkaclk@17000000 {
				compatible = "apm,xgene-device-clock";
				#clock-cells = <1>;
				clocks = <&socplldiv2 0>;
				reg = <0x0 0x17000000 0x0 0x2000>;
				reg-names = "csr-reg";
				csr-offset = <0xc>;
				csr-mask = <0x10>;
				enable-offset = <0x10>;
				enable-mask = <0x10>;
				clock-output-names = "rngpkaclk";
			};

			pcie0clk: pcie0clk@1f2bc000 {
				status = "disabled";
				compatible = "apm,xgene-device-clock";
				#clock-cells = <1>;
				clocks = <&socplldiv2 0>;
				reg = <0x0 0x1f2bc000 0x0 0x1000>;
				reg-names = "csr-reg";
				clock-output-names = "pcie0clk";
			};

			pcie1clk: pcie1clk@1f2cc000 {
				status = "disabled";
				compatible = "apm,xgene-device-clock";
				#clock-cells = <1>;
				clocks = <&socplldiv2 0>;
				reg = <0x0 0x1f2cc000 0x0 0x1000>;
				reg-names = "csr-reg";
				clock-output-names = "pcie1clk";
			};

			pcie2clk: pcie2clk@1f2dc000 {
				status = "disabled";
				compatible = "apm,xgene-device-clock";
				#clock-cells = <1>;
				clocks = <&socplldiv2 0>;
				reg = <0x0 0x1f2dc000 0x0 0x1000>;
				reg-names = "csr-reg";
				clock-output-names = "pcie2clk";
			};

			pcie3clk: pcie3clk@1f50c000 {
				status = "disabled";
				compatible = "apm,xgene-device-clock";
				#clock-cells = <1>;
				clocks = <&socplldiv2 0>;
				reg = <0x0 0x1f50c000 0x0 0x1000>;
				reg-names = "csr-reg";
				clock-output-names = "pcie3clk";
			};

			pcie4clk: pcie4clk@1f51c000 {
				status = "disabled";
				compatible = "apm,xgene-device-clock";
				#clock-cells = <1>;
				clocks = <&socplldiv2 0>;
				reg = <0x0 0x1f51c000 0x0 0x1000>;
				reg-names = "csr-reg";
				clock-output-names = "pcie4clk";
			};
		};

		pcie0: pcie@1f2b0000 {
			status = "disabled";
			device_type = "pci";
			compatible = "apm,xgene-storm-pcie", "apm,xgene-pcie";
			#interrupt-cells = <1>;
			#size-cells = <2>;
			#address-cells = <3>;
			reg = < 0x00 0x1f2b0000 0x0 0x00010000   /* Controller registers */
				0xe0 0xd0000000 0x0 0x00040000>; /* PCI config space */
			reg-names = "csr", "cfg";
			ranges = <0x01000000 0x00 0x00000000 0xe0 0x10000000 0x00 0x00010000   /* io */
				  0x02000000 0x00 0x80000000 0xe1 0x80000000 0x00 0x80000000>; /* mem */
			dma-ranges = <0x42000000 0x80 0x00000000 0x80 0x00000000 0x00 0x80000000
				      0x42000000 0x00 0x00000000 0x00 0x00000000 0x80 0x00000000>;
			interrupt-map-mask = <0x0 0x0 0x0 0x7>;
			interrupt-map = <0x0 0x0 0x0 0x1 &gic 0x0 0xc2 0x1
					 0x0 0x0 0x0 0x2 &gic 0x0 0xc3 0x1
					 0x0 0x0 0x0 0x3 &gic 0x0 0xc4 0x1
					 0x0 0x0 0x0 0x4 &gic 0x0 0xc5 0x1>;
			dma-coherent;
			clocks = <&pcie0clk 0>;
		};

		pcie1: pcie@1f2c0000 {
			status = "disabled";
			device_type = "pci";
			compatible = "apm,xgene-storm-pcie", "apm,xgene-pcie";
			#interrupt-cells = <1>;
			#size-cells = <2>;
			#address-cells = <3>;
			reg = < 0x00 0x1f2c0000 0x0 0x00010000   /* Controller registers */
				0xd0 0xd0000000 0x0 0x00040000>; /* PCI config space */
			reg-names = "csr", "cfg";
			ranges = <0x01000000 0x0 0x00000000 0xd0 0x10000000 0x00 0x00010000   /* io  */
				  0x02000000 0x0 0x80000000 0xd1 0x80000000 0x00 0x80000000>; /* mem */
			dma-ranges = <0x42000000 0x80 0x00000000 0x80 0x00000000 0x00 0x80000000
				      0x42000000 0x00 0x00000000 0x00 0x00000000 0x80 0x00000000>;
			interrupt-map-mask = <0x0 0x0 0x0 0x7>;
			interrupt-map = <0x0 0x0 0x0 0x1 &gic 0x0 0xc8 0x1
					 0x0 0x0 0x0 0x2 &gic 0x0 0xc9 0x1
					 0x0 0x0 0x0 0x3 &gic 0x0 0xca 0x1
					 0x0 0x0 0x0 0x4 &gic 0x0 0xcb 0x1>;
			dma-coherent;
			clocks = <&pcie1clk 0>;
		};

		pcie2: pcie@1f2d0000 {
			status = "disabled";
			device_type = "pci";
			compatible = "apm,xgene-storm-pcie", "apm,xgene-pcie";
			#interrupt-cells = <1>;
			#size-cells = <2>;
			#address-cells = <3>;
			reg =  < 0x00 0x1f2d0000 0x0 0x00010000   /* Controller registers */
				 0x90 0xd0000000 0x0 0x00040000>; /* PCI config space */
			reg-names = "csr", "cfg";
			ranges = <0x01000000 0x0 0x00000000 0x90 0x10000000 0x0 0x00010000   /* io  */
				  0x02000000 0x0 0x80000000 0x91 0x80000000 0x0 0x80000000>; /* mem */
			dma-ranges = <0x42000000 0x80 0x00000000 0x80 0x00000000 0x00 0x80000000
				      0x42000000 0x00 0x00000000 0x00 0x00000000 0x80 0x00000000>;
			interrupt-map-mask = <0x0 0x0 0x0 0x7>;
			interrupt-map = <0x0 0x0 0x0 0x1 &gic 0x0 0xce 0x1
					 0x0 0x0 0x0 0x2 &gic 0x0 0xcf 0x1
					 0x0 0x0 0x0 0x3 &gic 0x0 0xd0 0x1
					 0x0 0x0 0x0 0x4 &gic 0x0 0xd1 0x1>;
			dma-coherent;
			clocks = <&pcie2clk 0>;
		};

		pcie3: pcie@1f500000 {
			status = "disabled";
			device_type = "pci";
			compatible = "apm,xgene-storm-pcie", "apm,xgene-pcie";
			#interrupt-cells = <1>;
			#size-cells = <2>;
			#address-cells = <3>;
			reg = < 0x00 0x1f500000 0x0 0x00010000   /* Controller registers */
				0xa0 0xd0000000 0x0 0x00040000>; /* PCI config space */
			reg-names = "csr", "cfg";
			ranges = <0x01000000 0x0 0x00000000 0xa0 0x10000000 0x0 0x00010000   /* io   */
				  0x02000000 0x0 0x80000000 0xa1 0x80000000 0x0 0x80000000>; /* mem  */
			dma-ranges = <0x42000000 0x80 0x00000000 0x80 0x00000000 0x00 0x80000000
				      0x42000000 0x00 0x00000000 0x00 0x00000000 0x80 0x00000000>;
			interrupt-map-mask = <0x0 0x0 0x0 0x7>;
			interrupt-map = <0x0 0x0 0x0 0x1 &gic 0x0 0xd4 0x1
					 0x0 0x0 0x0 0x2 &gic 0x0 0xd5 0x1
					 0x0 0x0 0x0 0x3 &gic 0x0 0xd6 0x1
					 0x0 0x0 0x0 0x4 &gic 0x0 0xd7 0x1>;
			dma-coherent;
			clocks = <&pcie3clk 0>;
		};

		pcie4: pcie@1f510000 {
			status = "disabled";
			device_type = "pci";
			compatible = "apm,xgene-storm-pcie", "apm,xgene-pcie";
			#interrupt-cells = <1>;
			#size-cells = <2>;
			#address-cells = <3>;
			reg = < 0x00 0x1f510000 0x0 0x00010000   /* Controller registers */
				0xc0 0xd0000000 0x0 0x00200000>; /* PCI config space */
			reg-names = "csr", "cfg";
			ranges = <0x01000000 0x0 0x00000000 0xc0 0x10000000 0x0 0x00010000   /* io  */
				  0x02000000 0x0 0x80000000 0xc1 0x80000000 0x0 0x80000000>; /* mem */
			dma-ranges = <0x42000000 0x80 0x00000000 0x80 0x00000000 0x00 0x80000000
				      0x42000000 0x00 0x00000000 0x00 0x00000000 0x80 0x00000000>;
			interrupt-map-mask = <0x0 0x0 0x0 0x7>;
			interrupt-map = <0x0 0x0 0x0 0x1 &gic 0x0 0xda 0x1
					 0x0 0x0 0x0 0x2 &gic 0x0 0xdb 0x1
					 0x0 0x0 0x0 0x3 &gic 0x0 0xdc 0x1
					 0x0 0x0 0x0 0x4 &gic 0x0 0xdd 0x1>;
			dma-coherent;
			clocks = <&pcie4clk 0>;
		};

		serial0: serial@1c020000 {
			status = "disabled";
			device_type = "serial";
			compatible = "ns16550a";
			reg = <0 0x1c020000 0x0 0x1000>;
			reg-shift = <2>;
			clock-frequency = <10000000>; /* Updated by bootloader */
			interrupt-parent = <&gic>;
			interrupts = <0x0 0x4c 0x4>;
		};

		serial1: serial@1c021000 {
			status = "disabled";
			device_type = "serial";
			compatible = "ns16550a";
			reg = <0 0x1c021000 0x0 0x1000>;
			reg-shift = <2>;
			clock-frequency = <10000000>; /* Updated by bootloader */
			interrupt-parent = <&gic>;
			interrupts = <0x0 0x4d 0x4>;
		};

		serial2: serial@1c022000 {
			status = "disabled";
			device_type = "serial";
			compatible = "ns16550a";
			reg = <0 0x1c022000 0x0 0x1000>;
			reg-shift = <2>;
			clock-frequency = <10000000>; /* Updated by bootloader */
			interrupt-parent = <&gic>;
			interrupts = <0x0 0x4e 0x4>;
		};

		serial3: serial@1c023000 {
			status = "disabled";
			device_type = "serial";
			compatible = "ns16550a";
			reg = <0 0x1c023000 0x0 0x1000>;
			reg-shift = <2>;
			clock-frequency = <10000000>; /* Updated by bootloader */
			interrupt-parent = <&gic>;
			interrupts = <0x0 0x4f 0x4>;
		};

		phy1: phy@1f21a000 {
			compatible = "apm,xgene-phy";
			reg = <0x0 0x1f21a000 0x0 0x100>;
			#phy-cells = <1>;
			clocks = <&sataphy1clk 0>;
			status = "disabled";
			apm,tx-boost-gain = <30 30 30 30 30 30>;
			apm,tx-eye-tuning = <2 10 10 2 10 10>;
		};

		phy2: phy@1f22a000 {
			compatible = "apm,xgene-phy";
			reg = <0x0 0x1f22a000 0x0 0x100>;
			#phy-cells = <1>;
			clocks = <&sataphy2clk 0>;
			status = "ok";
			apm,tx-boost-gain = <30 30 30 30 30 30>;
			apm,tx-eye-tuning = <1 10 10 2 10 10>;
		};

		phy3: phy@1f23a000 {
			compatible = "apm,xgene-phy";
			reg = <0x0 0x1f23a000 0x0 0x100>;
			#phy-cells = <1>;
			clocks = <&sataphy3clk 0>;
			status = "ok";
			apm,tx-boost-gain = <31 31 31 31 31 31>;
			apm,tx-eye-tuning = <2 10 10 2 10 10>;
		};

		sata1: sata@1a000000 {
			compatible = "apm,xgene-ahci";
			reg = <0x0 0x1a000000 0x0 0x1000>,
			      <0x0 0x1f210000 0x0 0x1000>,
			      <0x0 0x1f21d000 0x0 0x1000>,
			      <0x0 0x1f21e000 0x0 0x1000>,
			      <0x0 0x1f217000 0x0 0x1000>;
			interrupts = <0x0 0x86 0x4>;
			dma-coherent;
			status = "disabled";
			clocks = <&sata01clk 0>;
			phys = <&phy1 0>;
			phy-names = "sata-phy";
		};

		sata2: sata@1a400000 {
			compatible = "apm,xgene-ahci";
			reg = <0x0 0x1a400000 0x0 0x1000>,
			      <0x0 0x1f220000 0x0 0x1000>,
			      <0x0 0x1f22d000 0x0 0x1000>,
			      <0x0 0x1f22e000 0x0 0x1000>,
			      <0x0 0x1f227000 0x0 0x1000>;
			interrupts = <0x0 0x87 0x4>;
			dma-coherent;
			status = "ok";
			clocks = <&sata23clk 0>;
			phys = <&phy2 0>;
			phy-names = "sata-phy";
		};

		sata3: sata@1a800000 {
			compatible = "apm,xgene-ahci";
			reg = <0x0 0x1a800000 0x0 0x1000>,
			      <0x0 0x1f230000 0x0 0x1000>,
			      <0x0 0x1f23d000 0x0 0x1000>,
			      <0x0 0x1f23e000 0x0 0x1000>;
			interrupts = <0x0 0x88 0x4>;
			dma-coherent;
			status = "ok";
			clocks = <&sata45clk 0>;
			phys = <&phy3 0>;
			phy-names = "sata-phy";
		};

		rtc: rtc@10510000 {
			compatible = "apm,xgene-rtc";
			reg = <0x0 0x10510000 0x0 0x400>;
			interrupts = <0x0 0x46 0x4>;
			#clock-cells = <1>;
			clocks = <&rtcclk 0>;
		};

		menet: ethernet@17020000 {
			compatible = "apm,xgene-enet";
			status = "disabled";
			reg = <0x0 0x17020000 0x0 0xd100>,
			      <0x0 0X17030000 0x0 0Xc300>,
			      <0x0 0X10000000 0x0 0X200>;
			reg-names = "enet_csr", "ring_csr", "ring_cmd";
			interrupts = <0x0 0x3c 0x4>;
			dma-coherent;
			clocks = <&menetclk 0>;
			/* mac address will be overwritten by the bootloader */
			local-mac-address = [00 00 00 00 00 00];
			phy-connection-type = "rgmii";
			phy-handle = <&menetphy>;
			mdio {
				compatible = "apm,xgene-mdio";
				#address-cells = <1>;
				#size-cells = <0>;
				menetphy: menetphy@3 {
					compatible = "ethernet-phy-id001c.c915";
					reg = <0x3>;
				};

			};
		};

		sgenet0: ethernet@1f210000 {
			compatible = "apm,xgene1-sgenet";
			status = "disabled";
			reg = <0x0 0x1f210000 0x0 0xd100>,
			      <0x0 0x1f200000 0x0 0Xc300>,
			      <0x0 0x1B000000 0x0 0X200>;
			reg-names = "enet_csr", "ring_csr", "ring_cmd";
			interrupts = <0x0 0xA0 0x4>,
				     <0x0 0xA1 0x4>;
			dma-coherent;
			clocks = <&sge0clk 0>;
			local-mac-address = [00 00 00 00 00 00];
			phy-connection-type = "sgmii";
		};

		sgenet1: ethernet@1f210030 {
			compatible = "apm,xgene1-sgenet";
			status = "disabled";
			reg = <0x0 0x1f210030 0x0 0xd100>,
			      <0x0 0x1f200000 0x0 0Xc300>,
			      <0x0 0x1B000000 0x0 0X8000>;
			reg-names = "enet_csr", "ring_csr", "ring_cmd";
			interrupts = <0x0 0xAC 0x4>,
				     <0x0 0xAD 0x4>;
			port-id = <1>;
			dma-coherent;
			clocks = <&sge1clk 0>;
			local-mac-address = [00 00 00 00 00 00];
			phy-connection-type = "sgmii";
		};

		xgenet: ethernet@1f610000 {
			compatible = "apm,xgene1-xgenet";
			status = "disabled";
			reg = <0x0 0x1f610000 0x0 0xd100>,
			      <0x0 0x1f600000 0x0 0Xc300>,
			      <0x0 0x18000000 0x0 0X200>;
			reg-names = "enet_csr", "ring_csr", "ring_cmd";
			interrupts = <0x0 0x60 0x4>,
				     <0x0 0x61 0x4>;
			dma-coherent;
			clocks = <&xge0clk 0>;
			/* mac address will be overwritten by the bootloader */
			local-mac-address = [00 00 00 00 00 00];
			phy-connection-type = "xgmii";
		};

		rng: rng@10520000 {
			compatible = "apm,xgene-rng";
			reg = <0x0 0x10520000 0x0 0x100>;
			interrupts = <0x0 0x41 0x4>;
			clocks = <&rngpkaclk 0>;
		};
	};
};
Commit	Line	Data
ee877b53 VK	1	/*
	2	* dts file for AppliedMicro (APM) X-Gene Storm SOC
	3	*
	4	* Copyright (C) 2013, Applied Micro Circuits Corporation
	5	*
	6	* This program is free software; you can redistribute it and/or
	7	* modify it under the terms of the GNU General Public License as
	8	* published by the Free Software Foundation; either version 2 of
	9	* the License, or (at your option) any later version.
	10	*/
	11
	12	/ {
	13	compatible = "apm,xgene-storm";
	14	interrupt-parent = <&gic>;
	15	#address-cells = <2>;
	16	#size-cells = <2>;
	17
	18	cpus {
	19	#address-cells = <2>;
	20	#size-cells = <0>;
	21
	22	cpu@000 {
	23	device_type = "cpu";
	24	compatible = "apm,potenza", "arm,armv8";
	25	reg = <0x0 0x000>;
	26	enable-method = "spin-table";
	27	cpu-release-addr = <0x1 0x0000fff8>;
	28	};
	29	cpu@001 {
	30	device_type = "cpu";
	31	compatible = "apm,potenza", "arm,armv8";
	32	reg = <0x0 0x001>;
	33	enable-method = "spin-table";
	34	cpu-release-addr = <0x1 0x0000fff8>;
	35	};
	36	cpu@100 {
	37	device_type = "cpu";
	38	compatible = "apm,potenza", "arm,armv8";
	39	reg = <0x0 0x100>;
	40	enable-method = "spin-table";
	41	cpu-release-addr = <0x1 0x0000fff8>;
	42	};
	43	cpu@101 {
	44	device_type = "cpu";
	45	compatible = "apm,potenza", "arm,armv8";
	46	reg = <0x0 0x101>;
	47	enable-method = "spin-table";
	48	cpu-release-addr = <0x1 0x0000fff8>;
	49	};
	50	cpu@200 {
	51	device_type = "cpu";
	52	compatible = "apm,potenza", "arm,armv8";
	53	reg = <0x0 0x200>;
	54	enable-method = "spin-table";
	55	cpu-release-addr = <0x1 0x0000fff8>;
	56	};
	57	cpu@201 {
	58	device_type = "cpu";
	59	compatible = "apm,potenza", "arm,armv8";
	60	reg = <0x0 0x201>;
	61	enable-method = "spin-table";
	62	cpu-release-addr = <0x1 0x0000fff8>;
	63	};
	64	cpu@300 {
65	device_type = "cpu";
66	compatible = "apm,potenza", "arm,armv8";
67	reg = <0x0 0x300>;
68	enable-method = "spin-table";
69	cpu-release-addr = <0x1 0x0000fff8>;
70	};
71	cpu@301 {
72	device_type = "cpu";
73	compatible = "apm,potenza", "arm,armv8";
74	reg = <0x0 0x301>;
75	enable-method = "spin-table";
76	cpu-release-addr = <0x1 0x0000fff8>;
77	};
78	};
79
80	gic: interrupt-controller@78010000 {
81	compatible = "arm,cortex-a15-gic";
82	#interrupt-cells = <3>;
83	interrupt-controller;
84	reg = <0x0 0x78010000 0x0 0x1000>, /* GIC Dist */
85	<0x0 0x78020000 0x0 0x1000>, /* GIC CPU */
86	<0x0 0x78040000 0x0 0x2000>, /* GIC VCPU Control */
87	<0x0 0x78060000 0x0 0x2000>; /* GIC VCPU */
88	interrupts = <1 9 0xf04>; /* GIC Maintenence IRQ */
89	};
90
91	timer {
92	compatible = "arm,armv8-timer";
93	interrupts = <1 0 0xff01>, /* Secure Phys IRQ */
94	<1 13 0xff01>, /* Non-secure Phys IRQ */
95	<1 14 0xff01>, /* Virt IRQ */
96	<1 15 0xff01>; /* Hyp IRQ */
97	clock-frequency = <50000000>;
98	};
99
100	soc {
101	compatible = "simple-bus";
102	#address-cells = <2>;
103	#size-cells = <2>;
104	ranges;
105
3eb15d84 LH	106	clocks {
	107	#address-cells = <2>;
	108	#size-cells = <2>;
	109	ranges;
	110	refclk: refclk {
	111	compatible = "fixed-clock";
	112	#clock-cells = <1>;
	113	clock-frequency = <100000000>;
	114	clock-output-names = "refclk";
	115	};
	116
	117	pcppll: pcppll@17000100 {
	118	compatible = "apm,xgene-pcppll-clock";
	119	#clock-cells = <1>;
	120	clocks = <&refclk 0>;
	121	clock-names = "pcppll";
	122	reg = <0x0 0x17000100 0x0 0x1000>;
	123	clock-output-names = "pcppll";
	124	type = <0>;
	125	};
	126
	127	socpll: socpll@17000120 {
	128	compatible = "apm,xgene-socpll-clock";
	129	#clock-cells = <1>;
	130	clocks = <&refclk 0>;
	131	clock-names = "socpll";
	132	reg = <0x0 0x17000120 0x0 0x1000>;
	133	clock-output-names = "socpll";
	134	type = <1>;
	135	};
	136
	137	socplldiv2: socplldiv2 {
	138	compatible = "fixed-factor-clock";
	139	#clock-cells = <1>;
	140	clocks = <&socpll 0>;
	141	clock-names = "socplldiv2";
	142	clock-mult = <1>;
	143	clock-div = <2>;
	144	clock-output-names = "socplldiv2";
	145	};
	146
	147	qmlclk: qmlclk {
	148	compatible = "apm,xgene-device-clock";
	149	#clock-cells = <1>;
	150	clocks = <&socplldiv2 0>;
	151	clock-names = "qmlclk";
	152	reg = <0x0 0x1703C000 0x0 0x1000>;
	153	reg-names = "csr-reg";
	154	clock-output-names = "qmlclk";
	155	};
	156
	157	ethclk: ethclk {
	158	compatible = "apm,xgene-device-clock";
	159	#clock-cells = <1>;
	160	clocks = <&socplldiv2 0>;
	161	clock-names = "ethclk";
	162	reg = <0x0 0x17000000 0x0 0x1000>;
	163	reg-names = "div-reg";
	164	divider-offset = <0x238>;
	165	divider-width = <0x9>;
	166	divider-shift = <0x0>;
	167	clock-output-names = "ethclk";
	168	};
	169
3d390425	170	menetclk: menetclk {
3eb15d84 LH	171	compatible = "apm,xgene-device-clock";
	172	#clock-cells = <1>;
	173	clocks = <&ethclk 0>;
3eb15d84 LH	174	reg = <0x0 0x1702C000 0x0 0x1000>;
3eb15d84 LH	175	reg-names = "csr-reg";
3d390425	176	clock-output-names = "menetclk";
3eb15d84	177	};
71b70ee9	178
4c2e7f09 IS	179	sge0clk: sge0clk@1f21c000 {
	180	compatible = "apm,xgene-device-clock";
	181	#clock-cells = <1>;
	182	clocks = <&socplldiv2 0>;
	183	reg = <0x0 0x1f21c000 0x0 0x1000>;
	184	reg-names = "csr-reg";
	185	csr-mask = <0x3>;
	186	clock-output-names = "sge0clk";
	187	};
	188
2d33394e KC	189	sge1clk: sge1clk@1f21c000 {
	190	compatible = "apm,xgene-device-clock";
	191	#clock-cells = <1>;
	192	clocks = <&socplldiv2 0>;
	193	reg = <0x0 0x1f21c000 0x0 0x1000>;
	194	reg-names = "csr-reg";
	195	csr-mask = <0xc>;
	196	clock-output-names = "sge1clk";
	197	};
	198
5fb32417 IS	199	xge0clk: xge0clk@1f61c000 {
	200	compatible = "apm,xgene-device-clock";
	201	#clock-cells = <1>;
	202	clocks = <&socplldiv2 0>;
	203	reg = <0x0 0x1f61c000 0x0 0x1000>;
	204	reg-names = "csr-reg";
	205	csr-mask = <0x3>;
	206	clock-output-names = "xge0clk";
	207	};
	208
71b70ee9 LH	209	sataphy1clk: sataphy1clk@1f21c000 {
	210	compatible = "apm,xgene-device-clock";
	211	#clock-cells = <1>;
	212	clocks = <&socplldiv2 0>;
	213	reg = <0x0 0x1f21c000 0x0 0x1000>;
	214	reg-names = "csr-reg";
	215	clock-output-names = "sataphy1clk";
	216	status = "disabled";
	217	csr-offset = <0x4>;
	218	csr-mask = <0x00>;
	219	enable-offset = <0x0>;
	220	enable-mask = <0x06>;
	221	};
	222
	223	sataphy2clk: sataphy1clk@1f22c000 {
	224	compatible = "apm,xgene-device-clock";
	225	#clock-cells = <1>;
	226	clocks = <&socplldiv2 0>;
	227	reg = <0x0 0x1f22c000 0x0 0x1000>;
	228	reg-names = "csr-reg";
	229	clock-output-names = "sataphy2clk";
	230	status = "ok";
	231	csr-offset = <0x4>;
	232	csr-mask = <0x3a>;
	233	enable-offset = <0x0>;
	234	enable-mask = <0x06>;
	235	};
	236
	237	sataphy3clk: sataphy1clk@1f23c000 {
	238	compatible = "apm,xgene-device-clock";
	239	#clock-cells = <1>;
	240	clocks = <&socplldiv2 0>;
	241	reg = <0x0 0x1f23c000 0x0 0x1000>;
	242	reg-names = "csr-reg";
	243	clock-output-names = "sataphy3clk";
	244	status = "ok";
	245	csr-offset = <0x4>;
	246	csr-mask = <0x3a>;
	247	enable-offset = <0x0>;
	248	enable-mask = <0x06>;
	249	};
db8c0286 LH	250
	251	sata01clk: sata01clk@1f21c000 {
	252	compatible = "apm,xgene-device-clock";
	253	#clock-cells = <1>;
	254	clocks = <&socplldiv2 0>;
	255	reg = <0x0 0x1f21c000 0x0 0x1000>;
	256	reg-names = "csr-reg";
	257	clock-output-names = "sata01clk";
	258	csr-offset = <0x4>;
	259	csr-mask = <0x05>;
	260	enable-offset = <0x0>;
	261	enable-mask = <0x39>;
	262	};
	263
	264	sata23clk: sata23clk@1f22c000 {
	265	compatible = "apm,xgene-device-clock";
	266	#clock-cells = <1>;
	267	clocks = <&socplldiv2 0>;
	268	reg = <0x0 0x1f22c000 0x0 0x1000>;
	269	reg-names = "csr-reg";
	270	clock-output-names = "sata23clk";
	271	csr-offset = <0x4>;
	272	csr-mask = <0x05>;
	273	enable-offset = <0x0>;
	274	enable-mask = <0x39>;
	275	};
	276
	277	sata45clk: sata45clk@1f23c000 {
	278	compatible = "apm,xgene-device-clock";
	279	#clock-cells = <1>;
	280	clocks = <&socplldiv2 0>;
	281	reg = <0x0 0x1f23c000 0x0 0x1000>;
	282	reg-names = "csr-reg";
	283	clock-output-names = "sata45clk";
	284	csr-offset = <0x4>;
	285	csr-mask = <0x05>;
	286	enable-offset = <0x0>;
	287	enable-mask = <0x39>;
	288	};
652ba666 LH	289
	290	rtcclk: rtcclk@17000000 {
	291	compatible = "apm,xgene-device-clock";
	292	#clock-cells = <1>;
	293	clocks = <&socplldiv2 0>;
	294	reg = <0x0 0x17000000 0x0 0x2000>;
	295	reg-names = "csr-reg";
	296	csr-offset = <0xc>;
	297	csr-mask = <0x2>;
	298	enable-offset = <0x10>;
	299	enable-mask = <0x2>;
	300	clock-output-names = "rtcclk";
	301	};
ab818739 FK	302
	303	rngpkaclk: rngpkaclk@17000000 {
	304	compatible = "apm,xgene-device-clock";
	305	#clock-cells = <1>;
	306	clocks = <&socplldiv2 0>;
	307	reg = <0x0 0x17000000 0x0 0x2000>;
	308	reg-names = "csr-reg";
	309	csr-offset = <0xc>;
	310	csr-mask = <0x10>;
	311	enable-offset = <0x10>;
	312	enable-mask = <0x10>;
	313	clock-output-names = "rngpkaclk";
	314	};
80213c03	315
767ebaff TI	316	pcie0clk: pcie0clk@1f2bc000 {
	317	status = "disabled";
	318	compatible = "apm,xgene-device-clock";
	319	#clock-cells = <1>;
	320	clocks = <&socplldiv2 0>;
	321	reg = <0x0 0x1f2bc000 0x0 0x1000>;
	322	reg-names = "csr-reg";
	323	clock-output-names = "pcie0clk";
	324	};
	325
	326	pcie1clk: pcie1clk@1f2cc000 {
	327	status = "disabled";
	328	compatible = "apm,xgene-device-clock";
	329	#clock-cells = <1>;
	330	clocks = <&socplldiv2 0>;
	331	reg = <0x0 0x1f2cc000 0x0 0x1000>;
	332	reg-names = "csr-reg";
	333	clock-output-names = "pcie1clk";
	334	};
	335
	336	pcie2clk: pcie2clk@1f2dc000 {
	337	status = "disabled";
	338	compatible = "apm,xgene-device-clock";
	339	#clock-cells = <1>;
	340	clocks = <&socplldiv2 0>;
	341	reg = <0x0 0x1f2dc000 0x0 0x1000>;
	342	reg-names = "csr-reg";
	343	clock-output-names = "pcie2clk";
	344	};
	345
	346	pcie3clk: pcie3clk@1f50c000 {
	347	status = "disabled";
	348	compatible = "apm,xgene-device-clock";
	349	#clock-cells = <1>;
	350	clocks = <&socplldiv2 0>;
	351	reg = <0x0 0x1f50c000 0x0 0x1000>;
	352	reg-names = "csr-reg";
	353	clock-output-names = "pcie3clk";
	354	};
	355
	356	pcie4clk: pcie4clk@1f51c000 {
	357	status = "disabled";
	358	compatible = "apm,xgene-device-clock";
	359	#clock-cells = <1>;
	360	clocks = <&socplldiv2 0>;
	361	reg = <0x0 0x1f51c000 0x0 0x1000>;
	362	reg-names = "csr-reg";
	363	clock-output-names = "pcie4clk";
	364	};
	365	};
	366
	367	pcie0: pcie@1f2b0000 {
	368	status = "disabled";
	369	device_type = "pci";
	370	compatible = "apm,xgene-storm-pcie", "apm,xgene-pcie";
	371	#interrupt-cells = <1>;
	372	#size-cells = <2>;
	373	#address-cells = <3>;
	374	reg = < 0x00 0x1f2b0000 0x0 0x00010000 /* Controller registers */
	375	0xe0 0xd0000000 0x0 0x00040000>; /* PCI config space */
	376	reg-names = "csr", "cfg";
	377	ranges = <0x01000000 0x00 0x00000000 0xe0 0x10000000 0x00 0x00010000 /* io */
	378	0x02000000 0x00 0x80000000 0xe1 0x80000000 0x00 0x80000000>; /* mem */
	379	dma-ranges = <0x42000000 0x80 0x00000000 0x80 0x00000000 0x00 0x80000000
380	0x42000000 0x00 0x00000000 0x00 0x00000000 0x80 0x00000000>;
381	interrupt-map-mask = <0x0 0x0 0x0 0x7>;
382	interrupt-map = <0x0 0x0 0x0 0x1 &gic 0x0 0xc2 0x1
383	0x0 0x0 0x0 0x2 &gic 0x0 0xc3 0x1
384	0x0 0x0 0x0 0x3 &gic 0x0 0xc4 0x1
385	0x0 0x0 0x0 0x4 &gic 0x0 0xc5 0x1>;
386	dma-coherent;
387	clocks = <&pcie0clk 0>;
388	};
389
390	pcie1: pcie@1f2c0000 {
391	status = "disabled";
392	device_type = "pci";
393	compatible = "apm,xgene-storm-pcie", "apm,xgene-pcie";
394	#interrupt-cells = <1>;
395	#size-cells = <2>;
396	#address-cells = <3>;
397	reg = < 0x00 0x1f2c0000 0x0 0x00010000 /* Controller registers */
398	0xd0 0xd0000000 0x0 0x00040000>; /* PCI config space */
399	reg-names = "csr", "cfg";
400	ranges = <0x01000000 0x0 0x00000000 0xd0 0x10000000 0x00 0x00010000 /* io */
401	0x02000000 0x0 0x80000000 0xd1 0x80000000 0x00 0x80000000>; /* mem */
402	dma-ranges = <0x42000000 0x80 0x00000000 0x80 0x00000000 0x00 0x80000000
403	0x42000000 0x00 0x00000000 0x00 0x00000000 0x80 0x00000000>;
404	interrupt-map-mask = <0x0 0x0 0x0 0x7>;
405	interrupt-map = <0x0 0x0 0x0 0x1 &gic 0x0 0xc8 0x1
406	0x0 0x0 0x0 0x2 &gic 0x0 0xc9 0x1
407	0x0 0x0 0x0 0x3 &gic 0x0 0xca 0x1
408	0x0 0x0 0x0 0x4 &gic 0x0 0xcb 0x1>;
409	dma-coherent;
410	clocks = <&pcie1clk 0>;
411	};
412
413	pcie2: pcie@1f2d0000 {
414	status = "disabled";
415	device_type = "pci";
416	compatible = "apm,xgene-storm-pcie", "apm,xgene-pcie";
417	#interrupt-cells = <1>;
418	#size-cells = <2>;
419	#address-cells = <3>;
420	reg = < 0x00 0x1f2d0000 0x0 0x00010000 /* Controller registers */
421	0x90 0xd0000000 0x0 0x00040000>; /* PCI config space */
422	reg-names = "csr", "cfg";
423	ranges = <0x01000000 0x0 0x00000000 0x90 0x10000000 0x0 0x00010000 /* io */
424	0x02000000 0x0 0x80000000 0x91 0x80000000 0x0 0x80000000>; /* mem */
425	dma-ranges = <0x42000000 0x80 0x00000000 0x80 0x00000000 0x00 0x80000000
426	0x42000000 0x00 0x00000000 0x00 0x00000000 0x80 0x00000000>;
427	interrupt-map-mask = <0x0 0x0 0x0 0x7>;
428	interrupt-map = <0x0 0x0 0x0 0x1 &gic 0x0 0xce 0x1
429	0x0 0x0 0x0 0x2 &gic 0x0 0xcf 0x1
430	0x0 0x0 0x0 0x3 &gic 0x0 0xd0 0x1
431	0x0 0x0 0x0 0x4 &gic 0x0 0xd1 0x1>;
432	dma-coherent;
433	clocks = <&pcie2clk 0>;
434	};
435
436	pcie3: pcie@1f500000 {
437	status = "disabled";
438	device_type = "pci";
439	compatible = "apm,xgene-storm-pcie", "apm,xgene-pcie";
440	#interrupt-cells = <1>;
441	#size-cells = <2>;
442	#address-cells = <3>;
443	reg = < 0x00 0x1f500000 0x0 0x00010000 /* Controller registers */
444	0xa0 0xd0000000 0x0 0x00040000>; /* PCI config space */
445	reg-names = "csr", "cfg";
446	ranges = <0x01000000 0x0 0x00000000 0xa0 0x10000000 0x0 0x00010000 /* io */
447	0x02000000 0x0 0x80000000 0xa1 0x80000000 0x0 0x80000000>; /* mem */
448	dma-ranges = <0x42000000 0x80 0x00000000 0x80 0x00000000 0x00 0x80000000
449	0x42000000 0x00 0x00000000 0x00 0x00000000 0x80 0x00000000>;
450	interrupt-map-mask = <0x0 0x0 0x0 0x7>;
451	interrupt-map = <0x0 0x0 0x0 0x1 &gic 0x0 0xd4 0x1
452	0x0 0x0 0x0 0x2 &gic 0x0 0xd5 0x1
453	0x0 0x0 0x0 0x3 &gic 0x0 0xd6 0x1
454	0x0 0x0 0x0 0x4 &gic 0x0 0xd7 0x1>;
455	dma-coherent;
456	clocks = <&pcie3clk 0>;
457	};
458
459	pcie4: pcie@1f510000 {
460	status = "disabled";
461	device_type = "pci";
462	compatible = "apm,xgene-storm-pcie", "apm,xgene-pcie";
463	#interrupt-cells = <1>;
464	#size-cells = <2>;
465	#address-cells = <3>;
466	reg = < 0x00 0x1f510000 0x0 0x00010000 /* Controller registers */
467	0xc0 0xd0000000 0x0 0x00200000>; /* PCI config space */
468	reg-names = "csr", "cfg";
469	ranges = <0x01000000 0x0 0x00000000 0xc0 0x10000000 0x0 0x00010000 /* io */
470	0x02000000 0x0 0x80000000 0xc1 0x80000000 0x0 0x80000000>; /* mem */
471	dma-ranges = <0x42000000 0x80 0x00000000 0x80 0x00000000 0x00 0x80000000
472	0x42000000 0x00 0x00000000 0x00 0x00000000 0x80 0x00000000>;
473	interrupt-map-mask = <0x0 0x0 0x0 0x7>;
474	interrupt-map = <0x0 0x0 0x0 0x1 &gic 0x0 0xda 0x1
475	0x0 0x0 0x0 0x2 &gic 0x0 0xdb 0x1
476	0x0 0x0 0x0 0x3 &gic 0x0 0xdc 0x1
477	0x0 0x0 0x0 0x4 &gic 0x0 0xdd 0x1>;
478	dma-coherent;
479	clocks = <&pcie4clk 0>;
3eb15d84 LH	480	};
3eb15d84 LH	481
ee877b53	482	serial0: serial@1c020000 {
457ced84	483	status = "disabled";
ee877b53	484	device_type = "serial";
457ced84	485	compatible = "ns16550a";
ee877b53 VK	486	reg = <0 0x1c020000 0x0 0x1000>;
	487	reg-shift = <2>;
	488	clock-frequency = <10000000>; /* Updated by bootloader */
	489	interrupt-parent = <&gic>;
	490	interrupts = <0x0 0x4c 0x4>;
	491	};
71b70ee9	492
457ced84 VK	493	serial1: serial@1c021000 {
	494	status = "disabled";
	495	device_type = "serial";
	496	compatible = "ns16550a";
	497	reg = <0 0x1c021000 0x0 0x1000>;
	498	reg-shift = <2>;
	499	clock-frequency = <10000000>; /* Updated by bootloader */
	500	interrupt-parent = <&gic>;
	501	interrupts = <0x0 0x4d 0x4>;
	502	};
	503
	504	serial2: serial@1c022000 {
	505	status = "disabled";
	506	device_type = "serial";
	507	compatible = "ns16550a";
	508	reg = <0 0x1c022000 0x0 0x1000>;
	509	reg-shift = <2>;
	510	clock-frequency = <10000000>; /* Updated by bootloader */
	511	interrupt-parent = <&gic>;
	512	interrupts = <0x0 0x4e 0x4>;
	513	};
	514
	515	serial3: serial@1c023000 {
	516	status = "disabled";
	517	device_type = "serial";
	518	compatible = "ns16550a";
	519	reg = <0 0x1c023000 0x0 0x1000>;
	520	reg-shift = <2>;
	521	clock-frequency = <10000000>; /* Updated by bootloader */
	522	interrupt-parent = <&gic>;
	523	interrupts = <0x0 0x4f 0x4>;
	524	};
	525
71b70ee9 LH	526	phy1: phy@1f21a000 {
	527	compatible = "apm,xgene-phy";
	528	reg = <0x0 0x1f21a000 0x0 0x100>;
	529	#phy-cells = <1>;
	530	clocks = <&sataphy1clk 0>;
	531	status = "disabled";
	532	apm,tx-boost-gain = <30 30 30 30 30 30>;
	533	apm,tx-eye-tuning = <2 10 10 2 10 10>;
	534	};
	535
	536	phy2: phy@1f22a000 {
	537	compatible = "apm,xgene-phy";
	538	reg = <0x0 0x1f22a000 0x0 0x100>;
	539	#phy-cells = <1>;
	540	clocks = <&sataphy2clk 0>;
	541	status = "ok";
	542	apm,tx-boost-gain = <30 30 30 30 30 30>;
	543	apm,tx-eye-tuning = <1 10 10 2 10 10>;
	544	};
	545
	546	phy3: phy@1f23a000 {
	547	compatible = "apm,xgene-phy";
	548	reg = <0x0 0x1f23a000 0x0 0x100>;
	549	#phy-cells = <1>;
	550	clocks = <&sataphy3clk 0>;
	551	status = "ok";
	552	apm,tx-boost-gain = <31 31 31 31 31 31>;
	553	apm,tx-eye-tuning = <2 10 10 2 10 10>;
	554	};
db8c0286 LH	555
	556	sata1: sata@1a000000 {
	557	compatible = "apm,xgene-ahci";
	558	reg = <0x0 0x1a000000 0x0 0x1000>,
	559	<0x0 0x1f210000 0x0 0x1000>,
	560	<0x0 0x1f21d000 0x0 0x1000>,
	561	<0x0 0x1f21e000 0x0 0x1000>,
	562	<0x0 0x1f217000 0x0 0x1000>;
	563	interrupts = <0x0 0x86 0x4>;
7a8d1ec1	564	dma-coherent;
db8c0286 LH	565	status = "disabled";
	566	clocks = <&sata01clk 0>;
	567	phys = <&phy1 0>;
	568	phy-names = "sata-phy";
	569	};
	570
	571	sata2: sata@1a400000 {
	572	compatible = "apm,xgene-ahci";
	573	reg = <0x0 0x1a400000 0x0 0x1000>,
	574	<0x0 0x1f220000 0x0 0x1000>,
	575	<0x0 0x1f22d000 0x0 0x1000>,
	576	<0x0 0x1f22e000 0x0 0x1000>,
	577	<0x0 0x1f227000 0x0 0x1000>;
	578	interrupts = <0x0 0x87 0x4>;
7a8d1ec1	579	dma-coherent;
db8c0286 LH	580	status = "ok";
	581	clocks = <&sata23clk 0>;
	582	phys = <&phy2 0>;
	583	phy-names = "sata-phy";
	584	};
	585
	586	sata3: sata@1a800000 {
	587	compatible = "apm,xgene-ahci";
	588	reg = <0x0 0x1a800000 0x0 0x1000>,
	589	<0x0 0x1f230000 0x0 0x1000>,
	590	<0x0 0x1f23d000 0x0 0x1000>,
	591	<0x0 0x1f23e000 0x0 0x1000>;
	592	interrupts = <0x0 0x88 0x4>;
7a8d1ec1	593	dma-coherent;
db8c0286 LH	594	status = "ok";
	595	clocks = <&sata45clk 0>;
	596	phys = <&phy3 0>;
	597	phy-names = "sata-phy";
	598	};
652ba666 LH	599
	600	rtc: rtc@10510000 {
	601	compatible = "apm,xgene-rtc";
	602	reg = <0x0 0x10510000 0x0 0x400>;
	603	interrupts = <0x0 0x46 0x4>;
	604	#clock-cells = <1>;
	605	clocks = <&rtcclk 0>;
	606	};
3d390425 IS	607
	608	menet: ethernet@17020000 {
	609	compatible = "apm,xgene-enet";
	610	status = "disabled";
	611	reg = <0x0 0x17020000 0x0 0xd100>,
09c9e059	612	<0x0 0X17030000 0x0 0Xc300>,
3d390425 IS	613	<0x0 0X10000000 0x0 0X200>;
	614	reg-names = "enet_csr", "ring_csr", "ring_cmd";
	615	interrupts = <0x0 0x3c 0x4>;
	616	dma-coherent;
	617	clocks = <&menetclk 0>;
5fb32417 IS	618	/* mac address will be overwritten by the bootloader */
5fb32417 IS	619	local-mac-address = [00 00 00 00 00 00];
3d390425 IS	620	phy-connection-type = "rgmii";
	621	phy-handle = <&menetphy>;
	622	mdio {
	623	compatible = "apm,xgene-mdio";
	624	#address-cells = <1>;
	625	#size-cells = <0>;
	626	menetphy: menetphy@3 {
	627	compatible = "ethernet-phy-id001c.c915";
	628	reg = <0x3>;
	629	};
	630
	631	};
	632	};
ab818739	633
4c2e7f09	634	sgenet0: ethernet@1f210000 {
2a91eb72	635	compatible = "apm,xgene1-sgenet";
4c2e7f09	636	status = "disabled";
09c9e059 IS	637	reg = <0x0 0x1f210000 0x0 0xd100>,
	638	<0x0 0x1f200000 0x0 0Xc300>,
	639	<0x0 0x1B000000 0x0 0X200>;
4c2e7f09	640	reg-names = "enet_csr", "ring_csr", "ring_cmd";
d3134649 IS	641	interrupts = <0x0 0xA0 0x4>,
d3134649 IS	642	<0x0 0xA1 0x4>;
4c2e7f09 IS	643	dma-coherent;
	644	clocks = <&sge0clk 0>;
	645	local-mac-address = [00 00 00 00 00 00];
	646	phy-connection-type = "sgmii";
	647	};
	648
2d33394e KC	649	sgenet1: ethernet@1f210030 {
	650	compatible = "apm,xgene1-sgenet";
	651	status = "disabled";
	652	reg = <0x0 0x1f210030 0x0 0xd100>,
	653	<0x0 0x1f200000 0x0 0Xc300>,
	654	<0x0 0x1B000000 0x0 0X8000>;
	655	reg-names = "enet_csr", "ring_csr", "ring_cmd";
d3134649 IS	656	interrupts = <0x0 0xAC 0x4>,
d3134649 IS	657	<0x0 0xAD 0x4>;
2d33394e KC	658	port-id = <1>;
	659	dma-coherent;
	660	clocks = <&sge1clk 0>;
	661	local-mac-address = [00 00 00 00 00 00];
	662	phy-connection-type = "sgmii";
	663	};
	664
5fb32417	665	xgenet: ethernet@1f610000 {
2a91eb72	666	compatible = "apm,xgene1-xgenet";
5fb32417 IS	667	status = "disabled";
5fb32417 IS	668	reg = <0x0 0x1f610000 0x0 0xd100>,
09c9e059	669	<0x0 0x1f600000 0x0 0Xc300>,
5fb32417 IS	670	<0x0 0x18000000 0x0 0X200>;
5fb32417 IS	671	reg-names = "enet_csr", "ring_csr", "ring_cmd";
d3134649 IS	672	interrupts = <0x0 0x60 0x4>,
d3134649 IS	673	<0x0 0x61 0x4>;
5fb32417 IS	674	dma-coherent;
	675	clocks = <&xge0clk 0>;
	676	/* mac address will be overwritten by the bootloader */
	677	local-mac-address = [00 00 00 00 00 00];
	678	phy-connection-type = "xgmii";
	679	};
	680
ab818739 FK	681	rng: rng@10520000 {
	682	compatible = "apm,xgene-rng";
	683	reg = <0x0 0x10520000 0x0 0x100>;
	684	interrupts = <0x0 0x41 0x4>;
	685	clocks = <&rngpkaclk 0>;
	686	};
ee877b53 VK	687	};
ee877b53 VK	688	};