projects / deliverable / linux.git / blame
| Commit | Line | Data |
|---|---|---|
| ee877b53 VK |
1 | /* |
| 2 | * dts file for AppliedMicro (APM) X-Gene Storm SOC | |
| 3 | * | |
| 4 | * Copyright (C) 2013, Applied Micro Circuits Corporation | |
| 5 | * | |
| 6 | * This program is free software; you can redistribute it and/or | |
| 7 | * modify it under the terms of the GNU General Public License as | |
| 8 | * published by the Free Software Foundation; either version 2 of | |
| 9 | * the License, or (at your option) any later version. | |
| 10 | */ | |
| 11 | ||
| 12 | / { | |
| 13 | compatible = "apm,xgene-storm"; | |
| 14 | interrupt-parent = <&gic>; | |
| 15 | #address-cells = <2>; | |
| 16 | #size-cells = <2>; | |
| 17 | ||
| 18 | cpus { | |
| 19 | #address-cells = <2>; | |
| 20 | #size-cells = <0>; | |
| 21 | ||
| 22 | cpu@000 { | |
| 23 | device_type = "cpu"; | |
| 24 | compatible = "apm,potenza", "arm,armv8"; | |
| 25 | reg = <0x0 0x000>; | |
| 26 | enable-method = "spin-table"; | |
| 27 | cpu-release-addr = <0x1 0x0000fff8>; | |
| 28 | }; | |
| 29 | cpu@001 { | |
| 30 | device_type = "cpu"; | |
| 31 | compatible = "apm,potenza", "arm,armv8"; | |
| 32 | reg = <0x0 0x001>; | |
| 33 | enable-method = "spin-table"; | |
| 34 | cpu-release-addr = <0x1 0x0000fff8>; | |
| 35 | }; | |
| 36 | cpu@100 { | |
| 37 | device_type = "cpu"; | |
| 38 | compatible = "apm,potenza", "arm,armv8"; | |
| 39 | reg = <0x0 0x100>; | |
| 40 | enable-method = "spin-table"; | |
| 41 | cpu-release-addr = <0x1 0x0000fff8>; | |
| 42 | }; | |
| 43 | cpu@101 { | |
| 44 | device_type = "cpu"; | |
| 45 | compatible = "apm,potenza", "arm,armv8"; | |
| 46 | reg = <0x0 0x101>; | |
| 47 | enable-method = "spin-table"; | |
| 48 | cpu-release-addr = <0x1 0x0000fff8>; | |
| 49 | }; | |
| 50 | cpu@200 { | |
| 51 | device_type = "cpu"; | |
| 52 | compatible = "apm,potenza", "arm,armv8"; | |
| 53 | reg = <0x0 0x200>; | |
| 54 | enable-method = "spin-table"; | |
| 55 | cpu-release-addr = <0x1 0x0000fff8>; | |
| 56 | }; | |
| 57 | cpu@201 { | |
| 58 | device_type = "cpu"; | |
| 59 | compatible = "apm,potenza", "arm,armv8"; | |
| 60 | reg = <0x0 0x201>; | |
| 61 | enable-method = "spin-table"; | |
| 62 | cpu-release-addr = <0x1 0x0000fff8>; | |
| 63 | }; | |
| 64 | cpu@300 { | |
| 65 | device_type = "cpu"; | |
| 66 | compatible = "apm,potenza", "arm,armv8"; | |
| 67 | reg = <0x0 0x300>; | |
| 68 | enable-method = "spin-table"; | |
| 69 | cpu-release-addr = <0x1 0x0000fff8>; | |
| 70 | }; | |
| 71 | cpu@301 { | |
| 72 | device_type = "cpu"; | |
| 73 | compatible = "apm,potenza", "arm,armv8"; | |
| 74 | reg = <0x0 0x301>; | |
| 75 | enable-method = "spin-table"; | |
| 76 | cpu-release-addr = <0x1 0x0000fff8>; | |
| 77 | }; | |
| 78 | }; | |
| 79 | ||
| 80 | gic: interrupt-controller@78010000 { | |
| 81 | compatible = "arm,cortex-a15-gic"; | |
| 82 | #interrupt-cells = <3>; | |
| 83 | interrupt-controller; | |
| 84 | reg = <0x0 0x78010000 0x0 0x1000>, /* GIC Dist */ | |
| 85 | <0x0 0x78020000 0x0 0x1000>, /* GIC CPU */ | |
| 86 | <0x0 0x78040000 0x0 0x2000>, /* GIC VCPU Control */ | |
| 87 | <0x0 0x78060000 0x0 0x2000>; /* GIC VCPU */ | |
| 88 | interrupts = <1 9 0xf04>; /* GIC Maintenence IRQ */ | |
| 89 | }; | |
| 90 | ||
| 91 | timer { | |
| 92 | compatible = "arm,armv8-timer"; | |
| 93 | interrupts = <1 0 0xff01>, /* Secure Phys IRQ */ | |
| 94 | <1 13 0xff01>, /* Non-secure Phys IRQ */ | |
| 95 | <1 14 0xff01>, /* Virt IRQ */ | |
| 96 | <1 15 0xff01>; /* Hyp IRQ */ | |
| 97 | clock-frequency = <50000000>; | |
| 98 | }; | |
| 99 | ||
| 100 | soc { | |
| 101 | compatible = "simple-bus"; | |
| 102 | #address-cells = <2>; | |
| 103 | #size-cells = <2>; | |
| 104 | ranges; | |
| 105 | ||
| 3eb15d84 LH |
106 | clocks { |
| 107 | #address-cells = <2>; | |
| 108 | #size-cells = <2>; | |
| 109 | ranges; | |
| 110 | refclk: refclk { | |
| 111 | compatible = "fixed-clock"; | |
| 112 | #clock-cells = <1>; | |
| 113 | clock-frequency = <100000000>; | |
| 114 | clock-output-names = "refclk"; | |
| 115 | }; | |
| 116 | ||
| 117 | pcppll: pcppll@17000100 { | |
| 118 | compatible = "apm,xgene-pcppll-clock"; | |
| 119 | #clock-cells = <1>; | |
| 120 | clocks = <&refclk 0>; | |
| 121 | clock-names = "pcppll"; | |
| 122 | reg = <0x0 0x17000100 0x0 0x1000>; | |
| 123 | clock-output-names = "pcppll"; | |
| 124 | type = <0>; | |
| 125 | }; | |
| 126 | ||
| 127 | socpll: socpll@17000120 { | |
| 128 | compatible = "apm,xgene-socpll-clock"; | |
| 129 | #clock-cells = <1>; | |
| 130 | clocks = <&refclk 0>; | |
| 131 | clock-names = "socpll"; | |
| 132 | reg = <0x0 0x17000120 0x0 0x1000>; | |
| 133 | clock-output-names = "socpll"; | |
| 134 | type = <1>; | |
| 135 | }; | |
| 136 | ||
| 137 | socplldiv2: socplldiv2 { | |
| 138 | compatible = "fixed-factor-clock"; | |
| 139 | #clock-cells = <1>; | |
| 140 | clocks = <&socpll 0>; | |
| 141 | clock-names = "socplldiv2"; | |
| 142 | clock-mult = <1>; | |
| 143 | clock-div = <2>; | |
| 144 | clock-output-names = "socplldiv2"; | |
| 145 | }; | |
| 146 | ||
| 147 | qmlclk: qmlclk { | |
| 148 | compatible = "apm,xgene-device-clock"; | |
| 149 | #clock-cells = <1>; | |
| 150 | clocks = <&socplldiv2 0>; | |
| 151 | clock-names = "qmlclk"; | |
| 152 | reg = <0x0 0x1703C000 0x0 0x1000>; | |
| 153 | reg-names = "csr-reg"; | |
| 154 | clock-output-names = "qmlclk"; | |
| 155 | }; | |
| 156 | ||
| 157 | ethclk: ethclk { | |
| 158 | compatible = "apm,xgene-device-clock"; | |
| 159 | #clock-cells = <1>; | |
| 160 | clocks = <&socplldiv2 0>; | |
| 161 | clock-names = "ethclk"; | |
| 162 | reg = <0x0 0x17000000 0x0 0x1000>; | |
| 163 | reg-names = "div-reg"; | |
| 164 | divider-offset = <0x238>; | |
| 165 | divider-width = <0x9>; | |
| 166 | divider-shift = <0x0>; | |
| 167 | clock-output-names = "ethclk"; | |
| 168 | }; | |
| 169 | ||
| 170 | eth8clk: eth8clk { | |
| 171 | compatible = "apm,xgene-device-clock"; | |
| 172 | #clock-cells = <1>; | |
| 173 | clocks = <ðclk 0>; | |
| 174 | clock-names = "eth8clk"; | |
| 175 | reg = <0x0 0x1702C000 0x0 0x1000>; | |
| 176 | reg-names = "csr-reg"; | |
| 177 | clock-output-names = "eth8clk"; | |
| 178 | }; | |
| 71b70ee9 LH |
179 | |
| 180 | sataphy1clk: sataphy1clk@1f21c000 { | |
| 181 | compatible = "apm,xgene-device-clock"; | |
| 182 | #clock-cells = <1>; | |
| 183 | clocks = <&socplldiv2 0>; | |
| 184 | reg = <0x0 0x1f21c000 0x0 0x1000>; | |
| 185 | reg-names = "csr-reg"; | |
| 186 | clock-output-names = "sataphy1clk"; | |
| 187 | status = "disabled"; | |
| 188 | csr-offset = <0x4>; | |
| 189 | csr-mask = <0x00>; | |
| 190 | enable-offset = <0x0>; | |
| 191 | enable-mask = <0x06>; | |
| 192 | }; | |
| 193 | ||
| 194 | sataphy2clk: sataphy1clk@1f22c000 { | |
| 195 | compatible = "apm,xgene-device-clock"; | |
| 196 | #clock-cells = <1>; | |
| 197 | clocks = <&socplldiv2 0>; | |
| 198 | reg = <0x0 0x1f22c000 0x0 0x1000>; | |
| 199 | reg-names = "csr-reg"; | |
| 200 | clock-output-names = "sataphy2clk"; | |
| 201 | status = "ok"; | |
| 202 | csr-offset = <0x4>; | |
| 203 | csr-mask = <0x3a>; | |
| 204 | enable-offset = <0x0>; | |
| 205 | enable-mask = <0x06>; | |
| 206 | }; | |
| 207 | ||
| 208 | sataphy3clk: sataphy1clk@1f23c000 { | |
| 209 | compatible = "apm,xgene-device-clock"; | |
| 210 | #clock-cells = <1>; | |
| 211 | clocks = <&socplldiv2 0>; | |
| 212 | reg = <0x0 0x1f23c000 0x0 0x1000>; | |
| 213 | reg-names = "csr-reg"; | |
| 214 | clock-output-names = "sataphy3clk"; | |
| 215 | status = "ok"; | |
| 216 | csr-offset = <0x4>; | |
| 217 | csr-mask = <0x3a>; | |
| 218 | enable-offset = <0x0>; | |
| 219 | enable-mask = <0x06>; | |
| 220 | }; | |
| db8c0286 LH |
221 | |
| 222 | sata01clk: sata01clk@1f21c000 { | |
| 223 | compatible = "apm,xgene-device-clock"; | |
| 224 | #clock-cells = <1>; | |
| 225 | clocks = <&socplldiv2 0>; | |
| 226 | reg = <0x0 0x1f21c000 0x0 0x1000>; | |
| 227 | reg-names = "csr-reg"; | |
| 228 | clock-output-names = "sata01clk"; | |
| 229 | csr-offset = <0x4>; | |
| 230 | csr-mask = <0x05>; | |
| 231 | enable-offset = <0x0>; | |
| 232 | enable-mask = <0x39>; | |
| 233 | }; | |
| 234 | ||
| 235 | sata23clk: sata23clk@1f22c000 { | |
| 236 | compatible = "apm,xgene-device-clock"; | |
| 237 | #clock-cells = <1>; | |
| 238 | clocks = <&socplldiv2 0>; | |
| 239 | reg = <0x0 0x1f22c000 0x0 0x1000>; | |
| 240 | reg-names = "csr-reg"; | |
| 241 | clock-output-names = "sata23clk"; | |
| 242 | csr-offset = <0x4>; | |
| 243 | csr-mask = <0x05>; | |
| 244 | enable-offset = <0x0>; | |
| 245 | enable-mask = <0x39>; | |
| 246 | }; | |
| 247 | ||
| 248 | sata45clk: sata45clk@1f23c000 { | |
| 249 | compatible = "apm,xgene-device-clock"; | |
| 250 | #clock-cells = <1>; | |
| 251 | clocks = <&socplldiv2 0>; | |
| 252 | reg = <0x0 0x1f23c000 0x0 0x1000>; | |
| 253 | reg-names = "csr-reg"; | |
| 254 | clock-output-names = "sata45clk"; | |
| 255 | csr-offset = <0x4>; | |
| 256 | csr-mask = <0x05>; | |
| 257 | enable-offset = <0x0>; | |
| 258 | enable-mask = <0x39>; | |
| 259 | }; | |
| 3eb15d84 LH |
260 | }; |
| 261 | ||
| ee877b53 VK |
262 | serial0: serial@1c020000 { |
| 263 | device_type = "serial"; | |
| 264 | compatible = "ns16550"; | |
| 265 | reg = <0 0x1c020000 0x0 0x1000>; | |
| 266 | reg-shift = <2>; | |
| 267 | clock-frequency = <10000000>; /* Updated by bootloader */ | |
| 268 | interrupt-parent = <&gic>; | |
| 269 | interrupts = <0x0 0x4c 0x4>; | |
| 270 | }; | |
| 71b70ee9 LH |
271 | |
| 272 | phy1: phy@1f21a000 { | |
| 273 | compatible = "apm,xgene-phy"; | |
| 274 | reg = <0x0 0x1f21a000 0x0 0x100>; | |
| 275 | #phy-cells = <1>; | |
| 276 | clocks = <&sataphy1clk 0>; | |
| 277 | status = "disabled"; | |
| 278 | apm,tx-boost-gain = <30 30 30 30 30 30>; | |
| 279 | apm,tx-eye-tuning = <2 10 10 2 10 10>; | |
| 280 | }; | |
| 281 | ||
| 282 | phy2: phy@1f22a000 { | |
| 283 | compatible = "apm,xgene-phy"; | |
| 284 | reg = <0x0 0x1f22a000 0x0 0x100>; | |
| 285 | #phy-cells = <1>; | |
| 286 | clocks = <&sataphy2clk 0>; | |
| 287 | status = "ok"; | |
| 288 | apm,tx-boost-gain = <30 30 30 30 30 30>; | |
| 289 | apm,tx-eye-tuning = <1 10 10 2 10 10>; | |
| 290 | }; | |
| 291 | ||
| 292 | phy3: phy@1f23a000 { | |
| 293 | compatible = "apm,xgene-phy"; | |
| 294 | reg = <0x0 0x1f23a000 0x0 0x100>; | |
| 295 | #phy-cells = <1>; | |
| 296 | clocks = <&sataphy3clk 0>; | |
| 297 | status = "ok"; | |
| 298 | apm,tx-boost-gain = <31 31 31 31 31 31>; | |
| 299 | apm,tx-eye-tuning = <2 10 10 2 10 10>; | |
| 300 | }; | |
| db8c0286 LH |
301 | |
| 302 | sata1: sata@1a000000 { | |
| 303 | compatible = "apm,xgene-ahci"; | |
| 304 | reg = <0x0 0x1a000000 0x0 0x1000>, | |
| 305 | <0x0 0x1f210000 0x0 0x1000>, | |
| 306 | <0x0 0x1f21d000 0x0 0x1000>, | |
| 307 | <0x0 0x1f21e000 0x0 0x1000>, | |
| 308 | <0x0 0x1f217000 0x0 0x1000>; | |
| 309 | interrupts = <0x0 0x86 0x4>; | |
| 310 | status = "disabled"; | |
| 311 | clocks = <&sata01clk 0>; | |
| 312 | phys = <&phy1 0>; | |
| 313 | phy-names = "sata-phy"; | |
| 314 | }; | |
| 315 | ||
| 316 | sata2: sata@1a400000 { | |
| 317 | compatible = "apm,xgene-ahci"; | |
| 318 | reg = <0x0 0x1a400000 0x0 0x1000>, | |
| 319 | <0x0 0x1f220000 0x0 0x1000>, | |
| 320 | <0x0 0x1f22d000 0x0 0x1000>, | |
| 321 | <0x0 0x1f22e000 0x0 0x1000>, | |
| 322 | <0x0 0x1f227000 0x0 0x1000>; | |
| 323 | interrupts = <0x0 0x87 0x4>; | |
| 324 | status = "ok"; | |
| 325 | clocks = <&sata23clk 0>; | |
| 326 | phys = <&phy2 0>; | |
| 327 | phy-names = "sata-phy"; | |
| 328 | }; | |
| 329 | ||
| 330 | sata3: sata@1a800000 { | |
| 331 | compatible = "apm,xgene-ahci"; | |
| 332 | reg = <0x0 0x1a800000 0x0 0x1000>, | |
| 333 | <0x0 0x1f230000 0x0 0x1000>, | |
| 334 | <0x0 0x1f23d000 0x0 0x1000>, | |
| 335 | <0x0 0x1f23e000 0x0 0x1000>; | |
| 336 | interrupts = <0x0 0x88 0x4>; | |
| 337 | status = "ok"; | |
| 338 | clocks = <&sata45clk 0>; | |
| 339 | phys = <&phy3 0>; | |
| 340 | phy-names = "sata-phy"; | |
| 341 | }; | |
| ee877b53 VK |
342 | }; |
| 343 | }; |