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arm64: dts: add random number generator dts node to APM X-Gene platform.
[deliverable/linux.git] / arch / arm64 / boot / dts / apm-storm.dtsi
CommitLineData
ee877b53
VK		 1/*
2 * dts file for AppliedMicro (APM) X-Gene Storm SOC
3 *
4 * Copyright (C) 2013, Applied Micro Circuits Corporation
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License as
8 * published by the Free Software Foundation; either version 2 of
9 * the License, or (at your option) any later version.
10 */
11
12/ {
13 compatible = "apm,xgene-storm";
14 interrupt-parent = <&gic>;
15 #address-cells = <2>;
16 #size-cells = <2>;
17
18 cpus {
19 #address-cells = <2>;
20 #size-cells = <0>;
21
22 cpu@000 {
23 device_type = "cpu";
24 compatible = "apm,potenza", "arm,armv8";
25 reg = <0x0 0x000>;
26 enable-method = "spin-table";
27 cpu-release-addr = <0x1 0x0000fff8>;
28 };
29 cpu@001 {
30 device_type = "cpu";
31 compatible = "apm,potenza", "arm,armv8";
32 reg = <0x0 0x001>;
33 enable-method = "spin-table";
34 cpu-release-addr = <0x1 0x0000fff8>;
35 };
36 cpu@100 {
37 device_type = "cpu";
38 compatible = "apm,potenza", "arm,armv8";
39 reg = <0x0 0x100>;
40 enable-method = "spin-table";
41 cpu-release-addr = <0x1 0x0000fff8>;
42 };
43 cpu@101 {
44 device_type = "cpu";
45 compatible = "apm,potenza", "arm,armv8";
46 reg = <0x0 0x101>;
47 enable-method = "spin-table";
48 cpu-release-addr = <0x1 0x0000fff8>;
49 };
50 cpu@200 {
51 device_type = "cpu";
52 compatible = "apm,potenza", "arm,armv8";
53 reg = <0x0 0x200>;
54 enable-method = "spin-table";
55 cpu-release-addr = <0x1 0x0000fff8>;
56 };
57 cpu@201 {
58 device_type = "cpu";
59 compatible = "apm,potenza", "arm,armv8";
60 reg = <0x0 0x201>;
61 enable-method = "spin-table";
62 cpu-release-addr = <0x1 0x0000fff8>;
63 };
64 cpu@300 {
65 device_type = "cpu";
66 compatible = "apm,potenza", "arm,armv8";
67 reg = <0x0 0x300>;
68 enable-method = "spin-table";
69 cpu-release-addr = <0x1 0x0000fff8>;
70 };
71 cpu@301 {
72 device_type = "cpu";
73 compatible = "apm,potenza", "arm,armv8";
74 reg = <0x0 0x301>;
75 enable-method = "spin-table";
76 cpu-release-addr = <0x1 0x0000fff8>;
77 };
78 };
79
80 gic: interrupt-controller@78010000 {
81 compatible = "arm,cortex-a15-gic";
82 #interrupt-cells = <3>;
83 interrupt-controller;
84 reg = <0x0 0x78010000 0x0 0x1000>, /* GIC Dist */
85 <0x0 0x78020000 0x0 0x1000>, /* GIC CPU */
86 <0x0 0x78040000 0x0 0x2000>, /* GIC VCPU Control */
87 <0x0 0x78060000 0x0 0x2000>; /* GIC VCPU */
88 interrupts = <1 9 0xf04>; /* GIC Maintenence IRQ */
89 };
90
91 timer {
92 compatible = "arm,armv8-timer";
93 interrupts = <1 0 0xff01>, /* Secure Phys IRQ */
94 <1 13 0xff01>, /* Non-secure Phys IRQ */
95 <1 14 0xff01>, /* Virt IRQ */
96 <1 15 0xff01>; /* Hyp IRQ */
97 clock-frequency = <50000000>;
98 };
99
100 soc {
101 compatible = "simple-bus";
102 #address-cells = <2>;
103 #size-cells = <2>;
104 ranges;
105
3eb15d84
LH		 106 clocks {
107 #address-cells = <2>;
108 #size-cells = <2>;
109 ranges;
110 refclk: refclk {
111 compatible = "fixed-clock";
112 #clock-cells = <1>;
113 clock-frequency = <100000000>;
114 clock-output-names = "refclk";
115 };
116
117 pcppll: pcppll@17000100 {
118 compatible = "apm,xgene-pcppll-clock";
119 #clock-cells = <1>;
120 clocks = <&refclk 0>;
121 clock-names = "pcppll";
122 reg = <0x0 0x17000100 0x0 0x1000>;
123 clock-output-names = "pcppll";
124 type = <0>;
125 };
126
127 socpll: socpll@17000120 {
128 compatible = "apm,xgene-socpll-clock";
129 #clock-cells = <1>;
130 clocks = <&refclk 0>;
131 clock-names = "socpll";
132 reg = <0x0 0x17000120 0x0 0x1000>;
133 clock-output-names = "socpll";
134 type = <1>;
135 };
136
137 socplldiv2: socplldiv2 {
138 compatible = "fixed-factor-clock";
139 #clock-cells = <1>;
140 clocks = <&socpll 0>;
141 clock-names = "socplldiv2";
142 clock-mult = <1>;
143 clock-div = <2>;
144 clock-output-names = "socplldiv2";
145 };
146
147 qmlclk: qmlclk {
148 compatible = "apm,xgene-device-clock";
149 #clock-cells = <1>;
150 clocks = <&socplldiv2 0>;
151 clock-names = "qmlclk";
152 reg = <0x0 0x1703C000 0x0 0x1000>;
153 reg-names = "csr-reg";
154 clock-output-names = "qmlclk";
155 };
156
157 ethclk: ethclk {
158 compatible = "apm,xgene-device-clock";
159 #clock-cells = <1>;
160 clocks = <&socplldiv2 0>;
161 clock-names = "ethclk";
162 reg = <0x0 0x17000000 0x0 0x1000>;
163 reg-names = "div-reg";
164 divider-offset = <0x238>;
165 divider-width = <0x9>;
166 divider-shift = <0x0>;
167 clock-output-names = "ethclk";
168 };
169
3d390425 170 menetclk: menetclk {
3eb15d84
LH		 171 compatible = "apm,xgene-device-clock";
172 #clock-cells = <1>;
173 clocks = <&ethclk 0>;
3eb15d84
LH		 174 reg = <0x0 0x1702C000 0x0 0x1000>;
175 reg-names = "csr-reg";
3d390425 176 clock-output-names = "menetclk";
3eb15d84 177 };
71b70ee9
LH		 178
179 sataphy1clk: sataphy1clk@1f21c000 {
180 compatible = "apm,xgene-device-clock";
181 #clock-cells = <1>;
182 clocks = <&socplldiv2 0>;
183 reg = <0x0 0x1f21c000 0x0 0x1000>;
184 reg-names = "csr-reg";
185 clock-output-names = "sataphy1clk";
186 status = "disabled";
187 csr-offset = <0x4>;
188 csr-mask = <0x00>;
189 enable-offset = <0x0>;
190 enable-mask = <0x06>;
191 };
192
193 sataphy2clk: sataphy1clk@1f22c000 {
194 compatible = "apm,xgene-device-clock";
195 #clock-cells = <1>;
196 clocks = <&socplldiv2 0>;
197 reg = <0x0 0x1f22c000 0x0 0x1000>;
198 reg-names = "csr-reg";
199 clock-output-names = "sataphy2clk";
200 status = "ok";
201 csr-offset = <0x4>;
202 csr-mask = <0x3a>;
203 enable-offset = <0x0>;
204 enable-mask = <0x06>;
205 };
206
207 sataphy3clk: sataphy1clk@1f23c000 {
208 compatible = "apm,xgene-device-clock";
209 #clock-cells = <1>;
210 clocks = <&socplldiv2 0>;
211 reg = <0x0 0x1f23c000 0x0 0x1000>;
212 reg-names = "csr-reg";
213 clock-output-names = "sataphy3clk";
214 status = "ok";
215 csr-offset = <0x4>;
216 csr-mask = <0x3a>;
217 enable-offset = <0x0>;
218 enable-mask = <0x06>;
219 };
db8c0286
LH		 220
221 sata01clk: sata01clk@1f21c000 {
222 compatible = "apm,xgene-device-clock";
223 #clock-cells = <1>;
224 clocks = <&socplldiv2 0>;
225 reg = <0x0 0x1f21c000 0x0 0x1000>;
226 reg-names = "csr-reg";
227 clock-output-names = "sata01clk";
228 csr-offset = <0x4>;
229 csr-mask = <0x05>;
230 enable-offset = <0x0>;
231 enable-mask = <0x39>;
232 };
233
234 sata23clk: sata23clk@1f22c000 {
235 compatible = "apm,xgene-device-clock";
236 #clock-cells = <1>;
237 clocks = <&socplldiv2 0>;
238 reg = <0x0 0x1f22c000 0x0 0x1000>;
239 reg-names = "csr-reg";
240 clock-output-names = "sata23clk";
241 csr-offset = <0x4>;
242 csr-mask = <0x05>;
243 enable-offset = <0x0>;
244 enable-mask = <0x39>;
245 };
246
247 sata45clk: sata45clk@1f23c000 {
248 compatible = "apm,xgene-device-clock";
249 #clock-cells = <1>;
250 clocks = <&socplldiv2 0>;
251 reg = <0x0 0x1f23c000 0x0 0x1000>;
252 reg-names = "csr-reg";
253 clock-output-names = "sata45clk";
254 csr-offset = <0x4>;
255 csr-mask = <0x05>;
256 enable-offset = <0x0>;
257 enable-mask = <0x39>;
258 };
652ba666
LH		 259
260 rtcclk: rtcclk@17000000 {
261 compatible = "apm,xgene-device-clock";
262 #clock-cells = <1>;
263 clocks = <&socplldiv2 0>;
264 reg = <0x0 0x17000000 0x0 0x2000>;
265 reg-names = "csr-reg";
266 csr-offset = <0xc>;
267 csr-mask = <0x2>;
268 enable-offset = <0x10>;
269 enable-mask = <0x2>;
270 clock-output-names = "rtcclk";
271 };
ab818739
FK		 272
273 rngpkaclk: rngpkaclk@17000000 {
274 compatible = "apm,xgene-device-clock";
275 #clock-cells = <1>;
276 clocks = <&socplldiv2 0>;
277 reg = <0x0 0x17000000 0x0 0x2000>;
278 reg-names = "csr-reg";
279 csr-offset = <0xc>;
280 csr-mask = <0x10>;
281 enable-offset = <0x10>;
282 enable-mask = <0x10>;
283 clock-output-names = "rngpkaclk";
284 };
3eb15d84
LH		 285 };
286
ee877b53 287 serial0: serial@1c020000 {
457ced84 288 status = "disabled";
ee877b53 289 device_type = "serial";
457ced84 290 compatible = "ns16550a";
ee877b53
VK		 291 reg = <0 0x1c020000 0x0 0x1000>;
292 reg-shift = <2>;
293 clock-frequency = <10000000>; /* Updated by bootloader */
294 interrupt-parent = <&gic>;
295 interrupts = <0x0 0x4c 0x4>;
296 };
71b70ee9 297
457ced84
VK		 298 serial1: serial@1c021000 {
299 status = "disabled";
300 device_type = "serial";
301 compatible = "ns16550a";
302 reg = <0 0x1c021000 0x0 0x1000>;
303 reg-shift = <2>;
304 clock-frequency = <10000000>; /* Updated by bootloader */
305 interrupt-parent = <&gic>;
306 interrupts = <0x0 0x4d 0x4>;
307 };
308
309 serial2: serial@1c022000 {
310 status = "disabled";
311 device_type = "serial";
312 compatible = "ns16550a";
313 reg = <0 0x1c022000 0x0 0x1000>;
314 reg-shift = <2>;
315 clock-frequency = <10000000>; /* Updated by bootloader */
316 interrupt-parent = <&gic>;
317 interrupts = <0x0 0x4e 0x4>;
318 };
319
320 serial3: serial@1c023000 {
321 status = "disabled";
322 device_type = "serial";
323 compatible = "ns16550a";
324 reg = <0 0x1c023000 0x0 0x1000>;
325 reg-shift = <2>;
326 clock-frequency = <10000000>; /* Updated by bootloader */
327 interrupt-parent = <&gic>;
328 interrupts = <0x0 0x4f 0x4>;
329 };
330
71b70ee9
LH		 331 phy1: phy@1f21a000 {
332 compatible = "apm,xgene-phy";
333 reg = <0x0 0x1f21a000 0x0 0x100>;
334 #phy-cells = <1>;
335 clocks = <&sataphy1clk 0>;
336 status = "disabled";
337 apm,tx-boost-gain = <30 30 30 30 30 30>;
338 apm,tx-eye-tuning = <2 10 10 2 10 10>;
339 };
340
341 phy2: phy@1f22a000 {
342 compatible = "apm,xgene-phy";
343 reg = <0x0 0x1f22a000 0x0 0x100>;
344 #phy-cells = <1>;
345 clocks = <&sataphy2clk 0>;
346 status = "ok";
347 apm,tx-boost-gain = <30 30 30 30 30 30>;
348 apm,tx-eye-tuning = <1 10 10 2 10 10>;
349 };
350
351 phy3: phy@1f23a000 {
352 compatible = "apm,xgene-phy";
353 reg = <0x0 0x1f23a000 0x0 0x100>;
354 #phy-cells = <1>;
355 clocks = <&sataphy3clk 0>;
356 status = "ok";
357 apm,tx-boost-gain = <31 31 31 31 31 31>;
358 apm,tx-eye-tuning = <2 10 10 2 10 10>;
359 };
db8c0286
LH		 360
361 sata1: sata@1a000000 {
362 compatible = "apm,xgene-ahci";
363 reg = <0x0 0x1a000000 0x0 0x1000>,
364 <0x0 0x1f210000 0x0 0x1000>,
365 <0x0 0x1f21d000 0x0 0x1000>,
366 <0x0 0x1f21e000 0x0 0x1000>,
367 <0x0 0x1f217000 0x0 0x1000>;
368 interrupts = <0x0 0x86 0x4>;
7a8d1ec1 369 dma-coherent;
db8c0286
LH		 370 status = "disabled";
371 clocks = <&sata01clk 0>;
372 phys = <&phy1 0>;
373 phy-names = "sata-phy";
374 };
375
376 sata2: sata@1a400000 {
377 compatible = "apm,xgene-ahci";
378 reg = <0x0 0x1a400000 0x0 0x1000>,
379 <0x0 0x1f220000 0x0 0x1000>,
380 <0x0 0x1f22d000 0x0 0x1000>,
381 <0x0 0x1f22e000 0x0 0x1000>,
382 <0x0 0x1f227000 0x0 0x1000>;
383 interrupts = <0x0 0x87 0x4>;
7a8d1ec1 384 dma-coherent;
db8c0286
LH		 385 status = "ok";
386 clocks = <&sata23clk 0>;
387 phys = <&phy2 0>;
388 phy-names = "sata-phy";
389 };
390
391 sata3: sata@1a800000 {
392 compatible = "apm,xgene-ahci";
393 reg = <0x0 0x1a800000 0x0 0x1000>,
394 <0x0 0x1f230000 0x0 0x1000>,
395 <0x0 0x1f23d000 0x0 0x1000>,
396 <0x0 0x1f23e000 0x0 0x1000>;
397 interrupts = <0x0 0x88 0x4>;
7a8d1ec1 398 dma-coherent;
db8c0286
LH		 399 status = "ok";
400 clocks = <&sata45clk 0>;
401 phys = <&phy3 0>;
402 phy-names = "sata-phy";
403 };
652ba666
LH		 404
405 rtc: rtc@10510000 {
406 compatible = "apm,xgene-rtc";
407 reg = <0x0 0x10510000 0x0 0x400>;
408 interrupts = <0x0 0x46 0x4>;
409 #clock-cells = <1>;
410 clocks = <&rtcclk 0>;
411 };
3d390425
IS		 412
413 menet: ethernet@17020000 {
414 compatible = "apm,xgene-enet";
415 status = "disabled";
416 reg = <0x0 0x17020000 0x0 0xd100>,
417 <0x0 0X17030000 0x0 0X400>,
418 <0x0 0X10000000 0x0 0X200>;
419 reg-names = "enet_csr", "ring_csr", "ring_cmd";
420 interrupts = <0x0 0x3c 0x4>;
421 dma-coherent;
422 clocks = <&menetclk 0>;
423 local-mac-address = [00 01 73 00 00 01];
424 phy-connection-type = "rgmii";
425 phy-handle = <&menetphy>;
426 mdio {
427 compatible = "apm,xgene-mdio";
428 #address-cells = <1>;
429 #size-cells = <0>;
430 menetphy: menetphy@3 {
431 compatible = "ethernet-phy-id001c.c915";
432 reg = <0x3>;
433 };
434
435 };
436 };
ab818739
FK		 437
438 rng: rng@10520000 {
439 compatible = "apm,xgene-rng";
440 reg = <0x0 0x10520000 0x0 0x100>;
441 interrupts = <0x0 0x41 0x4>;
442 clocks = <&rngpkaclk 0>;
443 };
444
ee877b53
VK		 445 };
446};
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