Commit | Line | Data |
---|---|---|
e8020874 LD |
1 | /* |
2 | * Devices shared by all Juno boards | |
3 | */ | |
4 | ||
79502355 LD |
5 | memtimer: timer@2a810000 { |
6 | compatible = "arm,armv7-timer-mem"; | |
7 | reg = <0x0 0x2a810000 0x0 0x10000>; | |
8 | clock-frequency = <50000000>; | |
9 | #address-cells = <2>; | |
10 | #size-cells = <2>; | |
11 | ranges; | |
12 | status = "disabled"; | |
13 | frame@2a830000 { | |
14 | frame-number = <1>; | |
15 | interrupts = <0 60 4>; | |
16 | reg = <0x0 0x2a830000 0x0 0x10000>; | |
17 | }; | |
18 | }; | |
19 | ||
ff9a6262 SH |
20 | mailbox: mhu@2b1f0000 { |
21 | compatible = "arm,mhu", "arm,primecell"; | |
22 | reg = <0x0 0x2b1f0000 0x0 0x1000>; | |
23 | interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>, | |
24 | <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; | |
25 | interrupt-names = "mhu_lpri_rx", | |
26 | "mhu_hpri_rx"; | |
27 | #mbox-cells = <1>; | |
28 | clocks = <&soc_refclk100mhz>; | |
29 | clock-names = "apb_pclk"; | |
30 | }; | |
31 | ||
e8020874 LD |
32 | gic: interrupt-controller@2c010000 { |
33 | compatible = "arm,gic-400", "arm,cortex-a15-gic"; | |
34 | reg = <0x0 0x2c010000 0 0x1000>, | |
35 | <0x0 0x2c02f000 0 0x2000>, | |
36 | <0x0 0x2c04f000 0 0x2000>, | |
37 | <0x0 0x2c06f000 0 0x2000>; | |
9e6f374f | 38 | #address-cells = <2>; |
e8020874 | 39 | #interrupt-cells = <3>; |
9e6f374f | 40 | #size-cells = <2>; |
e8020874 LD |
41 | interrupt-controller; |
42 | interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_HIGH)>; | |
9e6f374f LD |
43 | ranges = <0 0 0 0x2c1c0000 0 0x40000>; |
44 | v2m_0: v2m@0 { | |
45 | compatible = "arm,gic-v2m-frame"; | |
46 | msi-controller; | |
47 | reg = <0 0 0 0x1000>; | |
48 | }; | |
e8020874 LD |
49 | }; |
50 | ||
51 | timer { | |
52 | compatible = "arm,armv8-timer"; | |
53 | interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>, | |
54 | <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>, | |
55 | <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>, | |
56 | <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>; | |
57 | }; | |
58 | ||
3e287cf6 SH |
59 | /* |
60 | * Juno TRMs specify the size for these coresight components as 64K. | |
61 | * The actual size is just 4K though 64K is reserved. Access to the | |
62 | * unmapped reserved region results in a DECERR response. | |
63 | */ | |
64 | etf@20010000 { | |
65 | compatible = "arm,coresight-tmc", "arm,primecell"; | |
66 | reg = <0 0x20010000 0 0x1000>; | |
67 | ||
68 | clocks = <&soc_smc50mhz>; | |
69 | clock-names = "apb_pclk"; | |
bdeaa21a | 70 | power-domains = <&scpi_devpd 0>; |
3e287cf6 SH |
71 | ports { |
72 | #address-cells = <1>; | |
73 | #size-cells = <0>; | |
74 | ||
75 | /* input port */ | |
76 | port@0 { | |
77 | reg = <0>; | |
78 | etf_in_port: endpoint { | |
79 | slave-mode; | |
80 | remote-endpoint = <&main_funnel_out_port>; | |
81 | }; | |
82 | }; | |
83 | ||
84 | /* output port */ | |
85 | port@1 { | |
86 | reg = <0>; | |
87 | etf_out_port: endpoint { | |
88 | remote-endpoint = <&replicator_in_port0>; | |
89 | }; | |
90 | }; | |
91 | }; | |
92 | }; | |
93 | ||
94 | tpiu@20030000 { | |
95 | compatible = "arm,coresight-tpiu", "arm,primecell"; | |
96 | reg = <0 0x20030000 0 0x1000>; | |
97 | ||
98 | clocks = <&soc_smc50mhz>; | |
99 | clock-names = "apb_pclk"; | |
bdeaa21a | 100 | power-domains = <&scpi_devpd 0>; |
3e287cf6 SH |
101 | port { |
102 | tpiu_in_port: endpoint { | |
103 | slave-mode; | |
104 | remote-endpoint = <&replicator_out_port0>; | |
105 | }; | |
106 | }; | |
107 | }; | |
108 | ||
109 | main-funnel@20040000 { | |
110 | compatible = "arm,coresight-funnel", "arm,primecell"; | |
111 | reg = <0 0x20040000 0 0x1000>; | |
112 | ||
113 | clocks = <&soc_smc50mhz>; | |
114 | clock-names = "apb_pclk"; | |
bdeaa21a | 115 | power-domains = <&scpi_devpd 0>; |
3e287cf6 SH |
116 | ports { |
117 | #address-cells = <1>; | |
118 | #size-cells = <0>; | |
119 | ||
120 | port@0 { | |
121 | reg = <0>; | |
122 | main_funnel_out_port: endpoint { | |
123 | remote-endpoint = <&etf_in_port>; | |
124 | }; | |
125 | }; | |
126 | ||
127 | port@1 { | |
128 | reg = <0>; | |
129 | main_funnel_in_port0: endpoint { | |
130 | slave-mode; | |
131 | remote-endpoint = <&cluster0_funnel_out_port>; | |
132 | }; | |
133 | }; | |
134 | ||
135 | port@2 { | |
136 | reg = <1>; | |
137 | main_funnel_in_port1: endpoint { | |
138 | slave-mode; | |
139 | remote-endpoint = <&cluster1_funnel_out_port>; | |
140 | }; | |
141 | }; | |
142 | ||
143 | }; | |
144 | }; | |
145 | ||
146 | etr@20070000 { | |
147 | compatible = "arm,coresight-tmc", "arm,primecell"; | |
148 | reg = <0 0x20070000 0 0x1000>; | |
149 | ||
150 | clocks = <&soc_smc50mhz>; | |
151 | clock-names = "apb_pclk"; | |
bdeaa21a | 152 | power-domains = <&scpi_devpd 0>; |
3e287cf6 SH |
153 | port { |
154 | etr_in_port: endpoint { | |
155 | slave-mode; | |
156 | remote-endpoint = <&replicator_out_port1>; | |
157 | }; | |
158 | }; | |
159 | }; | |
160 | ||
161 | etm0: etm@22040000 { | |
162 | compatible = "arm,coresight-etm4x", "arm,primecell"; | |
163 | reg = <0 0x22040000 0 0x1000>; | |
164 | ||
165 | clocks = <&soc_smc50mhz>; | |
166 | clock-names = "apb_pclk"; | |
bdeaa21a | 167 | power-domains = <&scpi_devpd 0>; |
3e287cf6 SH |
168 | port { |
169 | cluster0_etm0_out_port: endpoint { | |
170 | remote-endpoint = <&cluster0_funnel_in_port0>; | |
171 | }; | |
172 | }; | |
173 | }; | |
174 | ||
175 | cluster0-funnel@220c0000 { | |
176 | compatible = "arm,coresight-funnel", "arm,primecell"; | |
177 | reg = <0 0x220c0000 0 0x1000>; | |
178 | ||
179 | clocks = <&soc_smc50mhz>; | |
180 | clock-names = "apb_pclk"; | |
bdeaa21a | 181 | power-domains = <&scpi_devpd 0>; |
3e287cf6 SH |
182 | ports { |
183 | #address-cells = <1>; | |
184 | #size-cells = <0>; | |
185 | ||
186 | port@0 { | |
187 | reg = <0>; | |
188 | cluster0_funnel_out_port: endpoint { | |
189 | remote-endpoint = <&main_funnel_in_port0>; | |
190 | }; | |
191 | }; | |
192 | ||
193 | port@1 { | |
194 | reg = <0>; | |
195 | cluster0_funnel_in_port0: endpoint { | |
196 | slave-mode; | |
197 | remote-endpoint = <&cluster0_etm0_out_port>; | |
198 | }; | |
199 | }; | |
200 | ||
201 | port@2 { | |
202 | reg = <1>; | |
203 | cluster0_funnel_in_port1: endpoint { | |
204 | slave-mode; | |
205 | remote-endpoint = <&cluster0_etm1_out_port>; | |
206 | }; | |
207 | }; | |
208 | }; | |
209 | }; | |
210 | ||
211 | etm1: etm@22140000 { | |
212 | compatible = "arm,coresight-etm4x", "arm,primecell"; | |
213 | reg = <0 0x22140000 0 0x1000>; | |
214 | ||
215 | clocks = <&soc_smc50mhz>; | |
216 | clock-names = "apb_pclk"; | |
bdeaa21a | 217 | power-domains = <&scpi_devpd 0>; |
3e287cf6 SH |
218 | port { |
219 | cluster0_etm1_out_port: endpoint { | |
220 | remote-endpoint = <&cluster0_funnel_in_port1>; | |
221 | }; | |
222 | }; | |
223 | }; | |
224 | ||
225 | etm2: etm@23040000 { | |
226 | compatible = "arm,coresight-etm4x", "arm,primecell"; | |
227 | reg = <0 0x23040000 0 0x1000>; | |
228 | ||
229 | clocks = <&soc_smc50mhz>; | |
230 | clock-names = "apb_pclk"; | |
bdeaa21a | 231 | power-domains = <&scpi_devpd 0>; |
3e287cf6 SH |
232 | port { |
233 | cluster1_etm0_out_port: endpoint { | |
234 | remote-endpoint = <&cluster1_funnel_in_port0>; | |
235 | }; | |
236 | }; | |
237 | }; | |
238 | ||
239 | cluster1-funnel@230c0000 { | |
240 | compatible = "arm,coresight-funnel", "arm,primecell"; | |
241 | reg = <0 0x230c0000 0 0x1000>; | |
242 | ||
243 | clocks = <&soc_smc50mhz>; | |
244 | clock-names = "apb_pclk"; | |
bdeaa21a | 245 | power-domains = <&scpi_devpd 0>; |
3e287cf6 SH |
246 | ports { |
247 | #address-cells = <1>; | |
248 | #size-cells = <0>; | |
249 | ||
250 | port@0 { | |
251 | reg = <0>; | |
252 | cluster1_funnel_out_port: endpoint { | |
253 | remote-endpoint = <&main_funnel_in_port1>; | |
254 | }; | |
255 | }; | |
256 | ||
257 | port@1 { | |
258 | reg = <0>; | |
259 | cluster1_funnel_in_port0: endpoint { | |
260 | slave-mode; | |
261 | remote-endpoint = <&cluster1_etm0_out_port>; | |
262 | }; | |
263 | }; | |
264 | ||
265 | port@2 { | |
266 | reg = <1>; | |
267 | cluster1_funnel_in_port1: endpoint { | |
268 | slave-mode; | |
269 | remote-endpoint = <&cluster1_etm1_out_port>; | |
270 | }; | |
271 | }; | |
272 | port@3 { | |
273 | reg = <2>; | |
274 | cluster1_funnel_in_port2: endpoint { | |
275 | slave-mode; | |
276 | remote-endpoint = <&cluster1_etm2_out_port>; | |
277 | }; | |
278 | }; | |
279 | port@4 { | |
280 | reg = <3>; | |
281 | cluster1_funnel_in_port3: endpoint { | |
282 | slave-mode; | |
283 | remote-endpoint = <&cluster1_etm3_out_port>; | |
284 | }; | |
285 | }; | |
286 | }; | |
287 | }; | |
288 | ||
289 | etm3: etm@23140000 { | |
290 | compatible = "arm,coresight-etm4x", "arm,primecell"; | |
291 | reg = <0 0x23140000 0 0x1000>; | |
292 | ||
293 | clocks = <&soc_smc50mhz>; | |
294 | clock-names = "apb_pclk"; | |
bdeaa21a | 295 | power-domains = <&scpi_devpd 0>; |
3e287cf6 SH |
296 | port { |
297 | cluster1_etm1_out_port: endpoint { | |
298 | remote-endpoint = <&cluster1_funnel_in_port1>; | |
299 | }; | |
300 | }; | |
301 | }; | |
302 | ||
303 | etm4: etm@23240000 { | |
304 | compatible = "arm,coresight-etm4x", "arm,primecell"; | |
305 | reg = <0 0x23240000 0 0x1000>; | |
306 | ||
307 | clocks = <&soc_smc50mhz>; | |
308 | clock-names = "apb_pclk"; | |
bdeaa21a | 309 | power-domains = <&scpi_devpd 0>; |
3e287cf6 SH |
310 | port { |
311 | cluster1_etm2_out_port: endpoint { | |
312 | remote-endpoint = <&cluster1_funnel_in_port2>; | |
313 | }; | |
314 | }; | |
315 | }; | |
316 | ||
317 | etm5: etm@23340000 { | |
318 | compatible = "arm,coresight-etm4x", "arm,primecell"; | |
319 | reg = <0 0x23340000 0 0x1000>; | |
320 | ||
321 | clocks = <&soc_smc50mhz>; | |
322 | clock-names = "apb_pclk"; | |
bdeaa21a | 323 | power-domains = <&scpi_devpd 0>; |
3e287cf6 SH |
324 | port { |
325 | cluster1_etm3_out_port: endpoint { | |
326 | remote-endpoint = <&cluster1_funnel_in_port3>; | |
327 | }; | |
328 | }; | |
329 | }; | |
330 | ||
331 | coresight-replicator { | |
332 | /* | |
333 | * Non-configurable replicators don't show up on the | |
334 | * AMBA bus. As such no need to add "arm,primecell". | |
335 | */ | |
336 | compatible = "arm,coresight-replicator"; | |
337 | ||
338 | ports { | |
339 | #address-cells = <1>; | |
340 | #size-cells = <0>; | |
341 | ||
342 | /* replicator output ports */ | |
343 | port@0 { | |
344 | reg = <0>; | |
345 | replicator_out_port0: endpoint { | |
346 | remote-endpoint = <&tpiu_in_port>; | |
347 | }; | |
348 | }; | |
349 | ||
350 | port@1 { | |
351 | reg = <1>; | |
352 | replicator_out_port1: endpoint { | |
353 | remote-endpoint = <&etr_in_port>; | |
354 | }; | |
355 | }; | |
356 | ||
357 | /* replicator input port */ | |
358 | port@2 { | |
359 | reg = <0>; | |
360 | replicator_in_port0: endpoint { | |
361 | slave-mode; | |
362 | remote-endpoint = <&etf_out_port>; | |
363 | }; | |
364 | }; | |
365 | }; | |
366 | }; | |
367 | ||
ff9a6262 SH |
368 | sram: sram@2e000000 { |
369 | compatible = "arm,juno-sram-ns", "mmio-sram"; | |
370 | reg = <0x0 0x2e000000 0x0 0x8000>; | |
371 | ||
372 | #address-cells = <1>; | |
373 | #size-cells = <1>; | |
374 | ranges = <0 0x0 0x2e000000 0x8000>; | |
375 | ||
376 | cpu_scp_lpri: scp-shmem@0 { | |
377 | compatible = "arm,juno-scp-shmem"; | |
378 | reg = <0x0 0x200>; | |
379 | }; | |
380 | ||
381 | cpu_scp_hpri: scp-shmem@200 { | |
382 | compatible = "arm,juno-scp-shmem"; | |
383 | reg = <0x200 0x200>; | |
384 | }; | |
385 | }; | |
386 | ||
36582c60 SH |
387 | pcie_ctlr: pcie-controller@40000000 { |
388 | compatible = "arm,juno-r1-pcie", "plda,xpressrich3-axi", "pci-host-ecam-generic"; | |
389 | device_type = "pci"; | |
390 | reg = <0 0x40000000 0 0x10000000>; /* ECAM config space */ | |
391 | bus-range = <0 255>; | |
392 | linux,pci-domain = <0>; | |
393 | #address-cells = <3>; | |
394 | #size-cells = <2>; | |
395 | dma-coherent; | |
396 | ranges = <0x01000000 0x00 0x5f800000 0x00 0x5f800000 0x0 0x00800000>, | |
397 | <0x02000000 0x00 0x50000000 0x00 0x50000000 0x0 0x08000000>, | |
398 | <0x42000000 0x40 0x00000000 0x40 0x00000000 0x1 0x00000000>; | |
399 | #interrupt-cells = <1>; | |
400 | interrupt-map-mask = <0 0 0 7>; | |
401 | interrupt-map = <0 0 0 1 &gic 0 0 0 136 4>, | |
402 | <0 0 0 2 &gic 0 0 0 137 4>, | |
403 | <0 0 0 3 &gic 0 0 0 138 4>, | |
404 | <0 0 0 4 &gic 0 0 0 139 4>; | |
405 | msi-parent = <&v2m_0>; | |
406 | status = "disabled"; | |
407 | }; | |
408 | ||
ff9a6262 SH |
409 | scpi { |
410 | compatible = "arm,scpi"; | |
411 | mboxes = <&mailbox 1>; | |
412 | shmem = <&cpu_scp_hpri>; | |
413 | ||
414 | clocks { | |
415 | compatible = "arm,scpi-clocks"; | |
416 | ||
6d6acd14 | 417 | scpi_dvfs: scpi-dvfs { |
ff9a6262 SH |
418 | compatible = "arm,scpi-dvfs-clocks"; |
419 | #clock-cells = <1>; | |
420 | clock-indices = <0>, <1>, <2>; | |
421 | clock-output-names = "atlclk", "aplclk","gpuclk"; | |
422 | }; | |
6d6acd14 | 423 | scpi_clk: scpi-clk { |
ff9a6262 SH |
424 | compatible = "arm,scpi-variable-clocks"; |
425 | #clock-cells = <1>; | |
9fd9288e LD |
426 | clock-indices = <3>; |
427 | clock-output-names = "pxlclk"; | |
ff9a6262 SH |
428 | }; |
429 | }; | |
dfacaf0e | 430 | |
bdeaa21a SH |
431 | scpi_devpd: scpi-power-domains { |
432 | compatible = "arm,scpi-power-domains"; | |
433 | num-domains = <2>; | |
434 | #power-domain-cells = <1>; | |
435 | }; | |
436 | ||
dfacaf0e PA |
437 | scpi_sensors0: sensors { |
438 | compatible = "arm,scpi-sensors"; | |
439 | #thermal-sensor-cells = <1>; | |
440 | }; | |
ff9a6262 SH |
441 | }; |
442 | ||
e8020874 LD |
443 | /include/ "juno-clocks.dtsi" |
444 | ||
445 | dma@7ff00000 { | |
446 | compatible = "arm,pl330", "arm,primecell"; | |
447 | reg = <0x0 0x7ff00000 0 0x1000>; | |
448 | #dma-cells = <1>; | |
449 | #dma-channels = <8>; | |
450 | #dma-requests = <32>; | |
451 | interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>, | |
452 | <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>, | |
453 | <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>, | |
454 | <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>, | |
aeb2ee56 | 455 | <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>, |
e8020874 LD |
456 | <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, |
457 | <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, | |
458 | <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, | |
459 | <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>; | |
460 | clocks = <&soc_faxiclk>; | |
461 | clock-names = "apb_pclk"; | |
462 | }; | |
463 | ||
9fd9288e LD |
464 | hdlcd@7ff50000 { |
465 | compatible = "arm,hdlcd"; | |
466 | reg = <0 0x7ff50000 0 0x1000>; | |
467 | interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>; | |
468 | clocks = <&scpi_clk 3>; | |
469 | clock-names = "pxlclk"; | |
470 | ||
471 | port { | |
6d6acd14 | 472 | hdlcd1_output: hdlcd1-endpoint { |
9fd9288e LD |
473 | remote-endpoint = <&tda998x_1_input>; |
474 | }; | |
475 | }; | |
476 | }; | |
477 | ||
478 | hdlcd@7ff60000 { | |
479 | compatible = "arm,hdlcd"; | |
480 | reg = <0 0x7ff60000 0 0x1000>; | |
481 | interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>; | |
482 | clocks = <&scpi_clk 3>; | |
483 | clock-names = "pxlclk"; | |
484 | ||
485 | port { | |
6d6acd14 | 486 | hdlcd0_output: hdlcd0-endpoint { |
9fd9288e LD |
487 | remote-endpoint = <&tda998x_0_input>; |
488 | }; | |
489 | }; | |
490 | }; | |
491 | ||
e8020874 LD |
492 | soc_uart0: uart@7ff80000 { |
493 | compatible = "arm,pl011", "arm,primecell"; | |
494 | reg = <0x0 0x7ff80000 0x0 0x1000>; | |
495 | interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; | |
496 | clocks = <&soc_uartclk>, <&soc_refclk100mhz>; | |
497 | clock-names = "uartclk", "apb_pclk"; | |
498 | }; | |
499 | ||
500 | i2c@7ffa0000 { | |
501 | compatible = "snps,designware-i2c"; | |
502 | reg = <0x0 0x7ffa0000 0x0 0x1000>; | |
503 | #address-cells = <1>; | |
504 | #size-cells = <0>; | |
505 | interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>; | |
506 | clock-frequency = <400000>; | |
507 | i2c-sda-hold-time-ns = <500>; | |
508 | clocks = <&soc_smc50mhz>; | |
509 | ||
9fd9288e | 510 | hdmi-transmitter@70 { |
e8020874 LD |
511 | compatible = "nxp,tda998x"; |
512 | reg = <0x70>; | |
9fd9288e | 513 | port { |
6d6acd14 | 514 | tda998x_0_input: tda998x-0-endpoint { |
9fd9288e LD |
515 | remote-endpoint = <&hdlcd0_output>; |
516 | }; | |
517 | }; | |
e8020874 LD |
518 | }; |
519 | ||
9fd9288e | 520 | hdmi-transmitter@71 { |
e8020874 LD |
521 | compatible = "nxp,tda998x"; |
522 | reg = <0x71>; | |
9fd9288e | 523 | port { |
6d6acd14 | 524 | tda998x_1_input: tda998x-1-endpoint { |
9fd9288e LD |
525 | remote-endpoint = <&hdlcd1_output>; |
526 | }; | |
527 | }; | |
e8020874 LD |
528 | }; |
529 | }; | |
530 | ||
531 | ohci@7ffb0000 { | |
532 | compatible = "generic-ohci"; | |
533 | reg = <0x0 0x7ffb0000 0x0 0x10000>; | |
534 | interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; | |
535 | clocks = <&soc_usb48mhz>; | |
536 | }; | |
537 | ||
538 | ehci@7ffc0000 { | |
539 | compatible = "generic-ehci"; | |
540 | reg = <0x0 0x7ffc0000 0x0 0x10000>; | |
541 | interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>; | |
542 | clocks = <&soc_usb48mhz>; | |
543 | }; | |
544 | ||
545 | memory-controller@7ffd0000 { | |
546 | compatible = "arm,pl354", "arm,primecell"; | |
547 | reg = <0 0x7ffd0000 0 0x1000>; | |
548 | interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>, | |
549 | <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>; | |
550 | clocks = <&soc_smc50mhz>; | |
551 | clock-names = "apb_pclk"; | |
552 | }; | |
553 | ||
554 | memory@80000000 { | |
555 | device_type = "memory"; | |
556 | /* last 16MB of the first memory area is reserved for secure world use by firmware */ | |
557 | reg = <0x00000000 0x80000000 0x0 0x7f000000>, | |
558 | <0x00000008 0x80000000 0x1 0x80000000>; | |
559 | }; | |
560 | ||
6d6acd14 | 561 | smb@08000000 { |
e8020874 LD |
562 | compatible = "simple-bus"; |
563 | #address-cells = <2>; | |
564 | #size-cells = <1>; | |
565 | ranges = <0 0 0 0x08000000 0x04000000>, | |
566 | <1 0 0 0x14000000 0x04000000>, | |
567 | <2 0 0 0x18000000 0x04000000>, | |
568 | <3 0 0 0x1c000000 0x04000000>, | |
569 | <4 0 0 0x0c000000 0x04000000>, | |
570 | <5 0 0 0x10000000 0x04000000>; | |
571 | ||
572 | #interrupt-cells = <1>; | |
573 | interrupt-map-mask = <0 0 15>; | |
9e6f374f LD |
574 | interrupt-map = <0 0 0 &gic 0 0 0 68 IRQ_TYPE_LEVEL_HIGH>, |
575 | <0 0 1 &gic 0 0 0 69 IRQ_TYPE_LEVEL_HIGH>, | |
576 | <0 0 2 &gic 0 0 0 70 IRQ_TYPE_LEVEL_HIGH>, | |
577 | <0 0 3 &gic 0 0 0 160 IRQ_TYPE_LEVEL_HIGH>, | |
578 | <0 0 4 &gic 0 0 0 161 IRQ_TYPE_LEVEL_HIGH>, | |
579 | <0 0 5 &gic 0 0 0 162 IRQ_TYPE_LEVEL_HIGH>, | |
580 | <0 0 6 &gic 0 0 0 163 IRQ_TYPE_LEVEL_HIGH>, | |
581 | <0 0 7 &gic 0 0 0 164 IRQ_TYPE_LEVEL_HIGH>, | |
582 | <0 0 8 &gic 0 0 0 165 IRQ_TYPE_LEVEL_HIGH>, | |
583 | <0 0 9 &gic 0 0 0 166 IRQ_TYPE_LEVEL_HIGH>, | |
584 | <0 0 10 &gic 0 0 0 167 IRQ_TYPE_LEVEL_HIGH>, | |
585 | <0 0 11 &gic 0 0 0 168 IRQ_TYPE_LEVEL_HIGH>, | |
586 | <0 0 12 &gic 0 0 0 169 IRQ_TYPE_LEVEL_HIGH>; | |
e8020874 LD |
587 | |
588 | /include/ "juno-motherboard.dtsi" | |
589 | }; | |
f5f7e455 BS |
590 | |
591 | site2: tlx@60000000 { | |
592 | compatible = "simple-bus"; | |
593 | #address-cells = <1>; | |
594 | #size-cells = <1>; | |
595 | ranges = <0 0 0x60000000 0x10000000>; | |
596 | #interrupt-cells = <1>; | |
597 | interrupt-map-mask = <0 0>; | |
598 | interrupt-map = <0 0 &gic 0 0 0 168 IRQ_TYPE_LEVEL_HIGH>; | |
599 | }; |