arm64: dts: enable pinctrl for Broadcom NS2 SoC
[deliverable/linux.git] / arch / arm64 / boot / dts / broadcom / ns2-svk.dts
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1/*
2 * BSD LICENSE
3 *
4 * Copyright(c) 2015 Broadcom Corporation. All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:
9 *
10 * * Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * * Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in
14 * the documentation and/or other materials provided with the
15 * distribution.
16 * * Neither the name of Broadcom Corporation nor the names of its
17 * contributors may be used to endorse or promote products derived
18 * from this software without specific prior written permission.
19 *
20 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
21 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
22 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
23 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
24 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
25 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
26 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
27 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
28 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
30 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
31 */
32
33/dts-v1/;
34
35#include "ns2.dtsi"
36
37/ {
38 model = "Broadcom NS2 SVK";
39 compatible = "brcm,ns2-svk", "brcm,ns2";
40
41 aliases {
42 serial0 = &uart3;
43 };
44
45 chosen {
46 stdout-path = "serial0:115200n8";
47 };
48
49 memory {
50 device_type = "memory";
51 reg = <0x000000000 0x80000000 0x00000000 0x40000000>;
52 };
c6fe9a2e 53};
6aad8bf9 54
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55&pcie0 {
56 status = "ok";
57};
58
59&pcie4 {
60 status = "ok";
61};
62
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63&i2c0 {
64 status = "ok";
65};
7ac674e8 66
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67&i2c1 {
68 status = "ok";
69};
70
71&uart3 {
72 status = "ok";
73};
7ac674e8 74
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75&ssp0 {
76 status = "ok";
77
78 slic@0 {
79 compatible = "silabs,si3226x";
80 reg = <0>;
81 spi-max-frequency = <5000000>;
82 spi-cpha = <1>;
83 spi-cpol = <1>;
84 pl022,hierarchy = <0>;
85 pl022,interface = <0>;
86 pl022,slave-tx-disable = <0>;
87 pl022,com-mode = <0>;
88 pl022,rx-level-trig = <1>;
89 pl022,tx-level-trig = <1>;
90 pl022,ctrl-len = <11>;
91 pl022,wait-state = <0>;
92 pl022,duplex = <0>;
93 };
94};
95
96&ssp1 {
97 status = "ok";
98
99 at25@0 {
100 compatible = "atmel,at25";
101 reg = <0>;
102 spi-max-frequency = <5000000>;
103 at25,byte-len = <0x8000>;
104 at25,addr-mode = <2>;
105 at25,page-size = <64>;
106 spi-cpha = <1>;
107 spi-cpol = <1>;
108 pl022,hierarchy = <0>;
109 pl022,interface = <0>;
110 pl022,slave-tx-disable = <0>;
111 pl022,com-mode = <0>;
112 pl022,rx-level-trig = <1>;
113 pl022,tx-level-trig = <1>;
114 pl022,ctrl-len = <11>;
115 pl022,wait-state = <0>;
116 pl022,duplex = <0>;
117 };
118};
119
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120&sata_phy0 {
121 status = "ok";
122};
123
124&sata_phy1 {
125 status = "ok";
126};
127
128&sata {
129 status = "ok";
130};
131
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132&sdio0 {
133 status = "ok";
134};
135
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136&nand {
137 nandcs@0 {
138 compatible = "brcm,nandcs";
139 reg = <0>;
140 nand-ecc-mode = "hw";
141 nand-ecc-strength = <8>;
142 nand-ecc-step-size = <512>;
143 #address-cells = <1>;
144 #size-cells = <1>;
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145 };
146};
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147
148&pinctrl {
149 pinctrl-names = "default";
150 pinctrl-0 = <&nand_sel>;
151 nand_sel: nand_sel {
152 function = "nand";
153 groups = "nand_grp";
154 };
155};
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