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6aad8bf9 RJ |
1 | /* |
2 | * BSD LICENSE | |
3 | * | |
59a5bede | 4 | * Copyright (c) 2015 Broadcom. All rights reserved. |
6aad8bf9 RJ |
5 | * |
6 | * Redistribution and use in source and binary forms, with or without | |
7 | * modification, are permitted provided that the following conditions | |
8 | * are met: | |
9 | * | |
10 | * * Redistributions of source code must retain the above copyright | |
11 | * notice, this list of conditions and the following disclaimer. | |
12 | * * Redistributions in binary form must reproduce the above copyright | |
13 | * notice, this list of conditions and the following disclaimer in | |
14 | * the documentation and/or other materials provided with the | |
15 | * distribution. | |
16 | * * Neither the name of Broadcom Corporation nor the names of its | |
17 | * contributors may be used to endorse or promote products derived | |
18 | * from this software without specific prior written permission. | |
19 | * | |
20 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS | |
21 | * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT | |
22 | * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR | |
23 | * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT | |
24 | * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, | |
25 | * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT | |
26 | * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, | |
27 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY | |
28 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT | |
29 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE | |
30 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. | |
31 | */ | |
32 | ||
33 | #include <dt-bindings/interrupt-controller/arm-gic.h> | |
d8bd64c1 | 34 | #include <dt-bindings/clock/bcm-ns2.h> |
6aad8bf9 | 35 | |
6aad8bf9 RJ |
36 | / { |
37 | compatible = "brcm,ns2"; | |
38 | interrupt-parent = <&gic>; | |
39 | #address-cells = <2>; | |
40 | #size-cells = <2>; | |
41 | ||
42 | cpus { | |
43 | #address-cells = <2>; | |
44 | #size-cells = <0>; | |
45 | ||
5b31d875 | 46 | A57_0: cpu@0 { |
6aad8bf9 RJ |
47 | device_type = "cpu"; |
48 | compatible = "arm,cortex-a57", "arm,armv8"; | |
49 | reg = <0 0>; | |
a9abb475 | 50 | enable-method = "psci"; |
33a93aa4 | 51 | next-level-cache = <&CLUSTER0_L2>; |
6aad8bf9 RJ |
52 | }; |
53 | ||
5b31d875 | 54 | A57_1: cpu@1 { |
6aad8bf9 RJ |
55 | device_type = "cpu"; |
56 | compatible = "arm,cortex-a57", "arm,armv8"; | |
57 | reg = <0 1>; | |
a9abb475 | 58 | enable-method = "psci"; |
33a93aa4 | 59 | next-level-cache = <&CLUSTER0_L2>; |
6aad8bf9 RJ |
60 | }; |
61 | ||
5b31d875 | 62 | A57_2: cpu@2 { |
6aad8bf9 RJ |
63 | device_type = "cpu"; |
64 | compatible = "arm,cortex-a57", "arm,armv8"; | |
65 | reg = <0 2>; | |
a9abb475 | 66 | enable-method = "psci"; |
33a93aa4 | 67 | next-level-cache = <&CLUSTER0_L2>; |
6aad8bf9 RJ |
68 | }; |
69 | ||
5b31d875 | 70 | A57_3: cpu@3 { |
6aad8bf9 RJ |
71 | device_type = "cpu"; |
72 | compatible = "arm,cortex-a57", "arm,armv8"; | |
73 | reg = <0 3>; | |
a9abb475 | 74 | enable-method = "psci"; |
33a93aa4 AP |
75 | next-level-cache = <&CLUSTER0_L2>; |
76 | }; | |
77 | ||
78 | CLUSTER0_L2: l2-cache@000 { | |
79 | compatible = "cache"; | |
6aad8bf9 RJ |
80 | }; |
81 | }; | |
82 | ||
a9abb475 LS |
83 | psci { |
84 | compatible = "arm,psci-1.0"; | |
85 | method = "smc"; | |
86 | }; | |
87 | ||
6aad8bf9 RJ |
88 | timer { |
89 | compatible = "arm,armv8-timer"; | |
90 | interrupts = <GIC_PPI 13 (GIC_CPU_MASK_RAW(0xff) | | |
585dcaca | 91 | IRQ_TYPE_LEVEL_LOW)>, |
6aad8bf9 | 92 | <GIC_PPI 14 (GIC_CPU_MASK_RAW(0xff) | |
585dcaca | 93 | IRQ_TYPE_LEVEL_LOW)>, |
6aad8bf9 | 94 | <GIC_PPI 11 (GIC_CPU_MASK_RAW(0xff) | |
585dcaca | 95 | IRQ_TYPE_LEVEL_LOW)>, |
6aad8bf9 | 96 | <GIC_PPI 10 (GIC_CPU_MASK_RAW(0xff) | |
585dcaca | 97 | IRQ_TYPE_LEVEL_LOW)>; |
6aad8bf9 RJ |
98 | }; |
99 | ||
5b31d875 AP |
100 | pmu { |
101 | compatible = "arm,armv8-pmuv3"; | |
102 | interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>, | |
103 | <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>, | |
104 | <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, | |
105 | <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>; | |
106 | interrupt-affinity = <&A57_0>, | |
107 | <&A57_1>, | |
108 | <&A57_2>, | |
109 | <&A57_3>; | |
110 | }; | |
111 | ||
fd5e5dd5 RJ |
112 | pcie0: pcie@20020000 { |
113 | compatible = "brcm,iproc-pcie"; | |
114 | reg = <0 0x20020000 0 0x1000>; | |
115 | ||
116 | #interrupt-cells = <1>; | |
117 | interrupt-map-mask = <0 0 0 0>; | |
118 | interrupt-map = <0 0 0 0 &gic GIC_SPI 281 IRQ_TYPE_NONE>; | |
119 | ||
120 | linux,pci-domain = <0>; | |
121 | ||
122 | bus-range = <0x00 0xff>; | |
123 | ||
124 | #address-cells = <3>; | |
125 | #size-cells = <2>; | |
126 | device_type = "pci"; | |
127 | ranges = <0x83000000 0 0x00000000 0 0x00000000 0 0x20000000>; | |
128 | ||
129 | brcm,pcie-ob; | |
130 | brcm,pcie-ob-oarr-size; | |
131 | brcm,pcie-ob-axi-offset = <0x00000000>; | |
132 | brcm,pcie-ob-window-size = <256>; | |
133 | ||
134 | status = "disabled"; | |
135 | ||
136 | msi-parent = <&msi0>; | |
137 | msi0: msi@20020000 { | |
138 | compatible = "brcm,iproc-msi"; | |
139 | msi-controller; | |
140 | interrupt-parent = <&gic>; | |
141 | interrupts = <GIC_SPI 277 IRQ_TYPE_NONE>, | |
142 | <GIC_SPI 278 IRQ_TYPE_NONE>, | |
143 | <GIC_SPI 279 IRQ_TYPE_NONE>, | |
144 | <GIC_SPI 280 IRQ_TYPE_NONE>; | |
145 | brcm,num-eq-region = <1>; | |
146 | brcm,num-msi-msg-region = <1>; | |
147 | }; | |
148 | }; | |
149 | ||
150 | pcie4: pcie@50020000 { | |
151 | compatible = "brcm,iproc-pcie"; | |
152 | reg = <0 0x50020000 0 0x1000>; | |
153 | ||
154 | #interrupt-cells = <1>; | |
155 | interrupt-map-mask = <0 0 0 0>; | |
156 | interrupt-map = <0 0 0 0 &gic GIC_SPI 305 IRQ_TYPE_NONE>; | |
157 | ||
158 | linux,pci-domain = <4>; | |
159 | ||
160 | bus-range = <0x00 0xff>; | |
161 | ||
162 | #address-cells = <3>; | |
163 | #size-cells = <2>; | |
164 | device_type = "pci"; | |
165 | ranges = <0x83000000 0 0x00000000 0 0x30000000 0 0x20000000>; | |
166 | ||
167 | brcm,pcie-ob; | |
168 | brcm,pcie-ob-oarr-size; | |
169 | brcm,pcie-ob-axi-offset = <0x30000000>; | |
170 | brcm,pcie-ob-window-size = <256>; | |
171 | ||
172 | status = "disabled"; | |
173 | ||
174 | msi-parent = <&msi4>; | |
175 | msi4: msi@50020000 { | |
176 | compatible = "brcm,iproc-msi"; | |
177 | msi-controller; | |
178 | interrupt-parent = <&gic>; | |
179 | interrupts = <GIC_SPI 301 IRQ_TYPE_NONE>, | |
180 | <GIC_SPI 302 IRQ_TYPE_NONE>, | |
181 | <GIC_SPI 303 IRQ_TYPE_NONE>, | |
182 | <GIC_SPI 304 IRQ_TYPE_NONE>; | |
183 | }; | |
184 | }; | |
185 | ||
6aad8bf9 RJ |
186 | soc: soc { |
187 | compatible = "simple-bus"; | |
188 | #address-cells = <1>; | |
189 | #size-cells = <1>; | |
190 | ranges = <0 0 0 0xffffffff>; | |
191 | ||
59a5bede AP |
192 | #include "ns2-clock.dtsi" |
193 | ||
538fb37c AP |
194 | dma0: dma@61360000 { |
195 | compatible = "arm,pl330", "arm,primecell"; | |
196 | reg = <0x61360000 0x1000>; | |
197 | interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>, | |
198 | <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>, | |
199 | <GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>, | |
200 | <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>, | |
201 | <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>, | |
202 | <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>, | |
203 | <GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>, | |
204 | <GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>, | |
205 | <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>; | |
206 | #dma-cells = <1>; | |
207 | #dma-channels = <8>; | |
208 | #dma-requests = <32>; | |
209 | clocks = <&iprocslow>; | |
210 | clock-names = "apb_pclk"; | |
211 | }; | |
212 | ||
6ec5f3c5 AP |
213 | smmu: mmu@64000000 { |
214 | compatible = "arm,mmu-500"; | |
215 | reg = <0x64000000 0x40000>; | |
216 | #global-interrupts = <2>; | |
217 | interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>, | |
218 | <GIC_SPI 230 IRQ_TYPE_LEVEL_HIGH>, | |
219 | <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>, | |
220 | <GIC_SPI 232 IRQ_TYPE_LEVEL_HIGH>, | |
221 | <GIC_SPI 233 IRQ_TYPE_LEVEL_HIGH>, | |
222 | <GIC_SPI 234 IRQ_TYPE_LEVEL_HIGH>, | |
223 | <GIC_SPI 235 IRQ_TYPE_LEVEL_HIGH>, | |
224 | <GIC_SPI 236 IRQ_TYPE_LEVEL_HIGH>, | |
225 | <GIC_SPI 237 IRQ_TYPE_LEVEL_HIGH>, | |
226 | <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, | |
227 | <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>, | |
228 | <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, | |
229 | <GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH>, | |
230 | <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>, | |
231 | <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>, | |
232 | <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>, | |
233 | <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>, | |
234 | <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>, | |
235 | <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>, | |
236 | <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>, | |
237 | <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>, | |
238 | <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>, | |
239 | <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>, | |
240 | <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>, | |
241 | <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>, | |
242 | <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>, | |
243 | <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>, | |
244 | <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>, | |
245 | <GIC_SPI 257 IRQ_TYPE_LEVEL_HIGH>, | |
246 | <GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH>, | |
247 | <GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH>, | |
248 | <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>, | |
249 | <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>, | |
250 | <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>; | |
251 | mmu-masters; | |
252 | }; | |
253 | ||
97b1504a YRDR |
254 | pinctrl: pinctrl@6501d130 { |
255 | compatible = "brcm,ns2-pinmux"; | |
256 | reg = <0x6501d130 0x08>, | |
257 | <0x660a0028 0x04>, | |
258 | <0x660009b0 0x40>; | |
259 | }; | |
260 | ||
5f2fb241 YRDR |
261 | gpio_aon: gpio@65024800 { |
262 | compatible = "brcm,iproc-gpio"; | |
263 | reg = <0x65024800 0x50>, | |
264 | <0x65024008 0x18>; | |
265 | ngpios = <6>; | |
266 | #gpio-cells = <2>; | |
267 | gpio-controller; | |
268 | }; | |
269 | ||
6aad8bf9 RJ |
270 | gic: interrupt-controller@65210000 { |
271 | compatible = "arm,gic-400"; | |
272 | #interrupt-cells = <3>; | |
273 | interrupt-controller; | |
274 | reg = <0x65210000 0x1000>, | |
275 | <0x65220000 0x1000>, | |
276 | <0x65240000 0x2000>, | |
277 | <0x65260000 0x1000>; | |
b2f9cd48 AP |
278 | interrupts = <GIC_PPI 9 (GIC_CPU_MASK_RAW(0xf) | |
279 | IRQ_TYPE_LEVEL_HIGH)>; | |
6aad8bf9 RJ |
280 | }; |
281 | ||
5dcc9c76 JM |
282 | cci@65590000 { |
283 | compatible = "arm,cci-400"; | |
284 | #address-cells = <1>; | |
285 | #size-cells = <1>; | |
286 | reg = <0x65590000 0x1000>; | |
287 | ranges = <0 0x65590000 0x10000>; | |
288 | ||
289 | pmu@9000 { | |
290 | compatible = "arm,cci-400-pmu,r1", | |
291 | "arm,cci-400-pmu"; | |
292 | reg = <0x9000 0x4000>; | |
293 | interrupts = <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>, | |
294 | <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>, | |
295 | <GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH>, | |
296 | <GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH>, | |
297 | <GIC_SPI 348 IRQ_TYPE_LEVEL_HIGH>, | |
298 | <GIC_SPI 349 IRQ_TYPE_LEVEL_HIGH>; | |
299 | }; | |
300 | }; | |
301 | ||
5f1a067b PK |
302 | mdio_mux_iproc: mdio-mux@6602023c { |
303 | compatible = "brcm,mdio-mux-iproc"; | |
304 | reg = <0x6602023c 0x14>; | |
305 | #address-cells = <1>; | |
306 | #size-cells = <0>; | |
307 | ||
308 | mdio@0 { | |
309 | reg = <0x0>; | |
310 | #address-cells = <1>; | |
311 | #size-cells = <0>; | |
312 | ||
313 | pci_phy0: pci-phy@0 { | |
314 | compatible = "brcm,ns2-pcie-phy"; | |
315 | reg = <0x0>; | |
316 | #phy-cells = <0>; | |
317 | status = "disabled"; | |
318 | }; | |
319 | }; | |
320 | ||
321 | mdio@7 { | |
322 | reg = <0x7>; | |
323 | #address-cells = <1>; | |
324 | #size-cells = <0>; | |
325 | ||
326 | pci_phy1: pci-phy@0 { | |
327 | compatible = "brcm,ns2-pcie-phy"; | |
328 | reg = <0x0>; | |
329 | #phy-cells = <0>; | |
330 | status = "disabled"; | |
331 | }; | |
332 | }; | |
333 | ||
334 | mdio@10 { | |
335 | reg = <0x10>; | |
336 | #address-cells = <1>; | |
337 | #size-cells = <0>; | |
338 | }; | |
339 | }; | |
340 | ||
e99df8fd AP |
341 | timer0: timer@66030000 { |
342 | compatible = "arm,sp804", "arm,primecell"; | |
343 | reg = <0x66030000 0x1000>; | |
344 | interrupts = <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>; | |
345 | clocks = <&iprocslow>, | |
346 | <&iprocslow>, | |
347 | <&iprocslow>; | |
348 | clock-names = "timer1", "timer2", "apb_pclk"; | |
349 | }; | |
350 | ||
351 | timer1: timer@66040000 { | |
352 | compatible = "arm,sp804", "arm,primecell"; | |
353 | reg = <0x66040000 0x1000>; | |
354 | interrupts = <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>; | |
355 | clocks = <&iprocslow>, | |
356 | <&iprocslow>, | |
357 | <&iprocslow>; | |
358 | clock-names = "timer1", "timer2", "apb_pclk"; | |
359 | }; | |
360 | ||
361 | timer2: timer@66050000 { | |
362 | compatible = "arm,sp804", "arm,primecell"; | |
363 | reg = <0x66050000 0x1000>; | |
364 | interrupts = <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>; | |
365 | clocks = <&iprocslow>, | |
366 | <&iprocslow>, | |
367 | <&iprocslow>; | |
368 | clock-names = "timer1", "timer2", "apb_pclk"; | |
369 | }; | |
370 | ||
371 | timer3: timer@66060000 { | |
372 | compatible = "arm,sp804", "arm,primecell"; | |
373 | reg = <0x66060000 0x1000>; | |
374 | interrupts = <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>; | |
375 | clocks = <&iprocslow>, | |
376 | <&iprocslow>, | |
377 | <&iprocslow>; | |
378 | clock-names = "timer1", "timer2", "apb_pclk"; | |
379 | }; | |
380 | ||
7ac674e8 RJ |
381 | i2c0: i2c@66080000 { |
382 | compatible = "brcm,iproc-i2c"; | |
383 | reg = <0x66080000 0x100>; | |
384 | #address-cells = <1>; | |
385 | #size-cells = <0>; | |
386 | interrupts = <GIC_SPI 394 IRQ_TYPE_NONE>; | |
387 | clock-frequency = <100000>; | |
388 | status = "disabled"; | |
389 | }; | |
390 | ||
6e79e7cf AP |
391 | wdt0: watchdog@66090000 { |
392 | compatible = "arm,sp805", "arm,primecell"; | |
393 | reg = <0x66090000 0x1000>; | |
394 | interrupts = <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>; | |
395 | clocks = <&iprocslow>, <&iprocslow>; | |
396 | clock-names = "wdogclk", "apb_pclk"; | |
397 | }; | |
398 | ||
5f2fb241 YRDR |
399 | gpio_g: gpio@660a0000 { |
400 | compatible = "brcm,iproc-gpio"; | |
401 | reg = <0x660a0000 0x50>; | |
402 | ngpios = <32>; | |
403 | #gpio-cells = <2>; | |
404 | gpio-controller; | |
405 | interrupt-controller; | |
406 | interrupts = <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>; | |
407 | }; | |
408 | ||
7ac674e8 RJ |
409 | i2c1: i2c@660b0000 { |
410 | compatible = "brcm,iproc-i2c"; | |
411 | reg = <0x660b0000 0x100>; | |
412 | #address-cells = <1>; | |
413 | #size-cells = <0>; | |
414 | interrupts = <GIC_SPI 395 IRQ_TYPE_NONE>; | |
415 | clock-frequency = <100000>; | |
416 | status = "disabled"; | |
417 | }; | |
418 | ||
1e0fdee8 JM |
419 | uart0: serial@66100000 { |
420 | compatible = "snps,dw-apb-uart"; | |
421 | reg = <0x66100000 0x100>; | |
422 | interrupts = <GIC_SPI 390 IRQ_TYPE_LEVEL_HIGH>; | |
423 | clocks = <&iprocslow>; | |
424 | reg-shift = <2>; | |
425 | reg-io-width = <4>; | |
426 | status = "disabled"; | |
427 | }; | |
428 | ||
429 | uart1: serial@66110000 { | |
430 | compatible = "snps,dw-apb-uart"; | |
431 | reg = <0x66110000 0x100>; | |
432 | interrupts = <GIC_SPI 391 IRQ_TYPE_LEVEL_HIGH>; | |
433 | clocks = <&iprocslow>; | |
434 | reg-shift = <2>; | |
435 | reg-io-width = <4>; | |
436 | status = "disabled"; | |
437 | }; | |
438 | ||
439 | uart2: serial@66120000 { | |
440 | compatible = "snps,dw-apb-uart"; | |
441 | reg = <0x66120000 0x100>; | |
442 | interrupts = <GIC_SPI 392 IRQ_TYPE_LEVEL_HIGH>; | |
443 | clocks = <&iprocslow>; | |
444 | reg-shift = <2>; | |
445 | reg-io-width = <4>; | |
446 | status = "disabled"; | |
447 | }; | |
448 | ||
6aad8bf9 RJ |
449 | uart3: serial@66130000 { |
450 | compatible = "snps,dw-apb-uart"; | |
451 | reg = <0x66130000 0x100>; | |
452 | interrupts = <GIC_SPI 393 IRQ_TYPE_LEVEL_HIGH>; | |
453 | reg-shift = <2>; | |
454 | reg-io-width = <4>; | |
d8bd64c1 | 455 | clocks = <&osc>; |
6aad8bf9 RJ |
456 | status = "disabled"; |
457 | }; | |
e8a6e265 | 458 | |
d69dbd9f AP |
459 | ssp0: ssp@66180000 { |
460 | compatible = "arm,pl022", "arm,primecell"; | |
461 | reg = <0x66180000 0x1000>; | |
462 | interrupts = <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>; | |
463 | clocks = <&iprocslow>, <&iprocslow>; | |
464 | clock-names = "spiclk", "apb_pclk"; | |
465 | #address-cells = <1>; | |
466 | #size-cells = <0>; | |
467 | status = "disabled"; | |
468 | }; | |
469 | ||
470 | ssp1: ssp@66190000 { | |
471 | compatible = "arm,pl022", "arm,primecell"; | |
472 | reg = <0x66190000 0x1000>; | |
473 | interrupts = <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>; | |
474 | clocks = <&iprocslow>, <&iprocslow>; | |
475 | clock-names = "spiclk", "apb_pclk"; | |
476 | #address-cells = <1>; | |
477 | #size-cells = <0>; | |
478 | status = "disabled"; | |
479 | }; | |
480 | ||
e8a6e265 AP |
481 | hwrng: hwrng@66220000 { |
482 | compatible = "brcm,iproc-rng200"; | |
483 | reg = <0x66220000 0x28>; | |
484 | }; | |
c6fe9a2e | 485 | |
ac9aae00 AP |
486 | sata_phy: sata_phy@663f0100 { |
487 | compatible = "brcm,iproc-ns2-sata-phy"; | |
488 | reg = <0x663f0100 0x1f00>, | |
489 | <0x663f004c 0x10>; | |
490 | reg-names = "phy", "phy-ctrl"; | |
491 | #address-cells = <1>; | |
492 | #size-cells = <0>; | |
493 | ||
494 | sata_phy0: sata-phy@0 { | |
495 | reg = <0>; | |
496 | #phy-cells = <0>; | |
497 | status = "disabled"; | |
498 | }; | |
499 | ||
500 | sata_phy1: sata-phy@1 { | |
501 | reg = <1>; | |
502 | #phy-cells = <0>; | |
503 | status = "disabled"; | |
504 | }; | |
505 | }; | |
506 | ||
507 | sata: ahci@663f2000 { | |
508 | compatible = "brcm,iproc-ahci", "generic-ahci"; | |
509 | reg = <0x663f2000 0x1000>; | |
510 | reg-names = "ahci"; | |
511 | interrupts = <GIC_SPI 438 IRQ_TYPE_LEVEL_HIGH>; | |
512 | #address-cells = <1>; | |
513 | #size-cells = <0>; | |
514 | status = "disabled"; | |
515 | ||
516 | sata0: sata-port@0 { | |
517 | reg = <0>; | |
518 | phys = <&sata_phy0>; | |
519 | phy-names = "sata-phy"; | |
520 | }; | |
521 | ||
522 | sata1: sata-port@1 { | |
523 | reg = <1>; | |
524 | phys = <&sata_phy1>; | |
525 | phy-names = "sata-phy"; | |
526 | }; | |
527 | }; | |
528 | ||
efc87767 AP |
529 | sdio0: sdhci@66420000 { |
530 | compatible = "brcm,sdhci-iproc-cygnus"; | |
531 | reg = <0x66420000 0x100>; | |
532 | interrupts = <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>; | |
533 | bus-width = <8>; | |
534 | clocks = <&genpll_sw BCM_NS2_GENPLL_SW_SDIO_CLK>; | |
535 | status = "disabled"; | |
536 | }; | |
537 | ||
538 | sdio1: sdhci@66430000 { | |
539 | compatible = "brcm,sdhci-iproc-cygnus"; | |
540 | reg = <0x66430000 0x100>; | |
541 | interrupts = <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>; | |
542 | bus-width = <8>; | |
543 | clocks = <&genpll_sw BCM_NS2_GENPLL_SW_SDIO_CLK>; | |
544 | status = "disabled"; | |
545 | }; | |
546 | ||
c6fe9a2e AP |
547 | nand: nand@66460000 { |
548 | compatible = "brcm,nand-iproc", "brcm,brcmnand-v6.1"; | |
549 | reg = <0x66460000 0x600>, | |
550 | <0x67015408 0x600>, | |
551 | <0x66460f00 0x20>; | |
552 | reg-names = "nand", "iproc-idm", "iproc-ext"; | |
553 | interrupts = <GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH>; | |
554 | ||
555 | #address-cells = <1>; | |
556 | #size-cells = <0>; | |
557 | ||
558 | brcm,nand-has-wp; | |
559 | }; | |
6aad8bf9 RJ |
560 | }; |
561 | }; |