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5bfb3889 ZSL |
1 | /* |
2 | * dtsi file for Broadcom (BRCM) Vulcan processor | |
3 | * | |
4 | * Copyright (c) 2013-2016 Broadcom | |
5 | * Author: Zi Shen Lim <zlim@broadcom.com> | |
6 | * | |
7 | * This program is free software; you can redistribute it and/or | |
8 | * modify it under the terms of the GNU General Public License as | |
9 | * published by the Free Software Foundation; either version 2 of | |
10 | * the License, or (at your option) any later version. | |
11 | */ | |
12 | ||
13 | #include <dt-bindings/interrupt-controller/arm-gic.h> | |
14 | ||
15 | / { | |
16 | model = "Broadcom Vulcan"; | |
17 | compatible = "brcm,vulcan-soc"; | |
18 | interrupt-parent = <&gic>; | |
19 | #address-cells = <2>; | |
20 | #size-cells = <2>; | |
21 | ||
22 | /* just 4 cpus now, 128 needed in full config */ | |
23 | cpus { | |
24 | #address-cells = <0x2>; | |
25 | #size-cells = <0x0>; | |
26 | ||
27 | cpu@0 { | |
28 | device_type = "cpu"; | |
29 | compatible = "brcm,vulcan", "arm,armv8"; | |
30 | reg = <0x0 0x0>; | |
31 | enable-method = "psci"; | |
32 | }; | |
33 | ||
34 | cpu@1 { | |
35 | device_type = "cpu"; | |
36 | compatible = "brcm,vulcan", "arm,armv8"; | |
37 | reg = <0x0 0x1>; | |
38 | enable-method = "psci"; | |
39 | }; | |
40 | ||
41 | cpu@2 { | |
42 | device_type = "cpu"; | |
43 | compatible = "brcm,vulcan", "arm,armv8"; | |
44 | reg = <0x0 0x2>; | |
45 | enable-method = "psci"; | |
46 | }; | |
47 | ||
48 | cpu@3 { | |
49 | device_type = "cpu"; | |
50 | compatible = "brcm,vulcan", "arm,armv8"; | |
51 | reg = <0x0 0x3>; | |
52 | enable-method = "psci"; | |
53 | }; | |
54 | }; | |
55 | ||
56 | psci { | |
57 | compatible = "arm,psci-0.2"; | |
58 | method = "smc"; | |
59 | }; | |
60 | ||
61 | gic: interrupt-controller@400080000 { | |
62 | compatible = "arm,gic-v3"; | |
63 | #interrupt-cells = <3>; | |
64 | #address-cells = <2>; | |
65 | #size-cells = <2>; | |
66 | ranges; | |
67 | interrupt-controller; | |
68 | #redistributor-regions = <1>; | |
69 | reg = <0x04 0x00080000 0x0 0x20000>, /* GICD */ | |
70 | <0x04 0x01000000 0x0 0x1000000>; /* GICR */ | |
71 | interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; | |
72 | ||
73 | gicits: gic-its@40010000 { | |
74 | compatible = "arm,gic-v3-its"; | |
75 | msi-controller; | |
76 | reg = <0x04 0x00100000 0x0 0x20000>; /* GIC ITS */ | |
77 | }; | |
78 | }; | |
79 | ||
80 | timer { | |
81 | compatible = "arm,armv8-timer"; | |
82 | interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH>, | |
83 | <GIC_PPI 14 IRQ_TYPE_LEVEL_HIGH>, | |
84 | <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH>, | |
85 | <GIC_PPI 10 IRQ_TYPE_LEVEL_HIGH>; | |
86 | }; | |
87 | ||
88 | pmu { | |
89 | compatible = "arm,armv8-pmuv3"; | |
90 | interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>; /* PMU overflow */ | |
91 | }; | |
92 | ||
93 | clk125mhz: uart_clk125mhz { | |
94 | compatible = "fixed-clock"; | |
95 | #clock-cells = <0>; | |
96 | clock-frequency = <125000000>; | |
97 | clock-output-names = "clk125mhz"; | |
98 | }; | |
99 | ||
100 | pci { | |
101 | compatible = "pci-host-ecam-generic"; | |
102 | device_type = "pci"; | |
103 | #interrupt-cells = <1>; | |
104 | #address-cells = <3>; | |
105 | #size-cells = <2>; | |
106 | ||
107 | /* ECAM at 0x3000_0000 - 0x4000_0000 */ | |
108 | reg = <0x0 0x30000000 0x0 0x10000000>; | |
109 | reg-names = "PCI ECAM"; | |
110 | ||
e6cc3be5 J |
111 | /* |
112 | * PCI ranges: | |
113 | * IO no supported | |
114 | * MEM 0x4000_0000 - 0x6000_0000 | |
115 | * MEM64 pref 0x40_0000_0000 - 0x60_0000_0000 | |
116 | */ | |
117 | ranges = | |
118 | <0x02000000 0 0x40000000 0 0x40000000 0 0x20000000 | |
119 | 0x43000000 0x40 0x00000000 0x40 0x00000000 0x20 0x00000000>; | |
5bfb3889 ZSL |
120 | interrupt-map-mask = <0 0 0 7>; |
121 | interrupt-map = | |
122 | /* addr pin ic icaddr icintr */ | |
123 | <0 0 0 1 &gic 0 0 GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH | |
124 | 0 0 0 2 &gic 0 0 GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH | |
125 | 0 0 0 3 &gic 0 0 GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH | |
126 | 0 0 0 4 &gic 0 0 GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; | |
127 | msi-parent = <&gicits>; | |
128 | dma-coherent; | |
129 | }; | |
130 | ||
131 | soc { | |
132 | compatible = "simple-bus"; | |
133 | #address-cells = <2>; | |
134 | #size-cells = <2>; | |
135 | ranges; | |
136 | ||
137 | uart0: serial@402020000 { | |
138 | compatible = "arm,pl011", "arm,primecell"; | |
139 | reg = <0x04 0x02020000 0x0 0x1000>; | |
140 | interrupt-parent = <&gic>; | |
141 | interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>; | |
142 | clocks = <&clk125mhz>; | |
143 | clock-names = "apb_pclk"; | |
144 | }; | |
145 | }; | |
146 | ||
147 | }; |