[deliverable/linux.git] / arch / arm64 / boot / dts / exynos / exynos7.dtsi

/*
 * SAMSUNG EXYNOS7 SoC device tree source
 *
 * Copyright (c) 2014 Samsung Electronics Co., Ltd.
 *		http://www.samsung.com
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */

#include <dt-bindings/clock/exynos7-clk.h>

/ {
	compatible = "samsung,exynos7";
	interrupt-parent = <&gic>;
	#address-cells = <2>;
	#size-cells = <2>;

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		cpu@0 {
			device_type = "cpu";
			compatible = "arm,cortex-a57", "arm,armv8";
			reg = <0x0>;
			enable-method = "psci";
		};

		cpu@1 {
			device_type = "cpu";
			compatible = "arm,cortex-a57", "arm,armv8";
			reg = <0x1>;
			enable-method = "psci";
		};

		cpu@2 {
			device_type = "cpu";
			compatible = "arm,cortex-a57", "arm,armv8";
			reg = <0x2>;
			enable-method = "psci";
		};

		cpu@3 {
			device_type = "cpu";
			compatible = "arm,cortex-a57", "arm,armv8";
			reg = <0x3>;
			enable-method = "psci";
		};
	};

	psci {
		compatible = "arm,psci-0.2";
		method = "smc";
	};

	soc: soc {
		compatible = "simple-bus";
		#address-cells = <1>;
		#size-cells = <1>;
		ranges = <0 0 0 0x18000000>;

		chipid@10000000 {
			compatible = "samsung,exynos4210-chipid";
			reg = <0x10000000 0x100>;
		};

		fin_pll: xxti {
			compatible = "fixed-clock";
			clock-output-names = "fin_pll";
			#clock-cells = <0>;
		};

		gic: interrupt-controller@11001000 {
			compatible = "arm,gic-400";
			#interrupt-cells = <3>;
			#address-cells = <0>;
			interrupt-controller;
			reg =	<0x11001000 0x1000>,
				<0x11002000 0x1000>,
				<0x11004000 0x2000>,
				<0x11006000 0x2000>;
		};

		clock_topc: clock-controller@10570000 {
			compatible = "samsung,exynos7-clock-topc";
			reg = <0x10570000 0x10000>;
			#clock-cells = <1>;
		};

		clock_top0: clock-controller@105d0000 {
			compatible = "samsung,exynos7-clock-top0";
			reg = <0x105d0000 0xb000>;
			#clock-cells = <1>;
			clocks = <&fin_pll>, <&clock_topc DOUT_SCLK_BUS0_PLL>,
				 <&clock_topc DOUT_SCLK_BUS1_PLL>,
				 <&clock_topc DOUT_SCLK_CC_PLL>,
				 <&clock_topc DOUT_SCLK_MFC_PLL>;
			clock-names = "fin_pll", "dout_sclk_bus0_pll",
				      "dout_sclk_bus1_pll", "dout_sclk_cc_pll",
				      "dout_sclk_mfc_pll";
		};

		clock_peric0: clock-controller@13610000 {
			compatible = "samsung,exynos7-clock-peric0";
			reg = <0x13610000 0xd00>;
			#clock-cells = <1>;
			clocks = <&fin_pll>, <&clock_top0 DOUT_ACLK_PERIC0>,
				 <&clock_top0 CLK_SCLK_UART0>;
			clock-names = "fin_pll", "dout_aclk_peric0_66",
				      "sclk_uart0";
		};

		clock_peric1: clock-controller@14c80000 {
			compatible = "samsung,exynos7-clock-peric1";
			reg = <0x14c80000 0xd00>;
			#clock-cells = <1>;
			clocks = <&fin_pll>, <&clock_top0 DOUT_ACLK_PERIC1>,
				 <&clock_top0 CLK_SCLK_UART1>,
				 <&clock_top0 CLK_SCLK_UART2>,
				 <&clock_top0 CLK_SCLK_UART3>;
			clock-names = "fin_pll", "dout_aclk_peric1_66",
				      "sclk_uart1", "sclk_uart2", "sclk_uart3";
		};

		clock_peris: clock-controller@10040000 {
			compatible = "samsung,exynos7-clock-peris";
			reg = <0x10040000 0xd00>;
			#clock-cells = <1>;
			clocks = <&fin_pll>, <&clock_topc DOUT_ACLK_PERIS>;
			clock-names = "fin_pll", "dout_aclk_peris_66";
		};

		serial_0: serial@13630000 {
			compatible = "samsung,exynos4210-uart";
			reg = <0x13630000 0x100>;
			interrupts = <0 440 0>;
			clocks = <&clock_peric0 PCLK_UART0>,
				 <&clock_peric0 SCLK_UART0>;
			clock-names = "uart", "clk_uart_baud0";
			status = "disabled";
		};

		serial_1: serial@14c20000 {
			compatible = "samsung,exynos4210-uart";
			reg = <0x14c20000 0x100>;
			interrupts = <0 456 0>;
			clocks = <&clock_peric1 PCLK_UART1>,
				 <&clock_peric1 SCLK_UART1>;
			clock-names = "uart", "clk_uart_baud0";
			status = "disabled";
		};

		serial_2: serial@14c30000 {
			compatible = "samsung,exynos4210-uart";
			reg = <0x14c30000 0x100>;
			interrupts = <0 457 0>;
			clocks = <&clock_peric1 PCLK_UART2>,
				 <&clock_peric1 SCLK_UART2>;
			clock-names = "uart", "clk_uart_baud0";
			status = "disabled";
		};

		serial_3: serial@14c40000 {
			compatible = "samsung,exynos4210-uart";
			reg = <0x14c40000 0x100>;
			interrupts = <0 458 0>;
			clocks = <&clock_peric1 PCLK_UART3>,
				 <&clock_peric1 SCLK_UART3>;
			clock-names = "uart", "clk_uart_baud0";
			status = "disabled";
		};

		timer {
			compatible = "arm,armv8-timer";
			interrupts = <1 13 0xff01>,
				     <1 14 0xff01>,
				     <1 11 0xff01>,
				     <1 10 0xff01>;
		};
	};
};
Commit	Line	Data
b9024cbc NKC	1	/*
	2	* SAMSUNG EXYNOS7 SoC device tree source
	3	*
	4	* Copyright (c) 2014 Samsung Electronics Co., Ltd.
	5	* http://www.samsung.com
	6	*
	7	* This program is free software; you can redistribute it and/or modify
	8	* it under the terms of the GNU General Public License version 2 as
	9	* published by the Free Software Foundation.
	10	*/
	11
	12	#include <dt-bindings/clock/exynos7-clk.h>
	13
	14	/ {
	15	compatible = "samsung,exynos7";
	16	interrupt-parent = <&gic>;
	17	#address-cells = <2>;
	18	#size-cells = <2>;
	19
	20	cpus {
	21	#address-cells = <1>;
	22	#size-cells = <0>;
	23
	24	cpu@0 {
	25	device_type = "cpu";
	26	compatible = "arm,cortex-a57", "arm,armv8";
	27	reg = <0x0>;
	28	enable-method = "psci";
	29	};
	30
	31	cpu@1 {
	32	device_type = "cpu";
	33	compatible = "arm,cortex-a57", "arm,armv8";
	34	reg = <0x1>;
	35	enable-method = "psci";
	36	};
	37
	38	cpu@2 {
	39	device_type = "cpu";
	40	compatible = "arm,cortex-a57", "arm,armv8";
	41	reg = <0x2>;
	42	enable-method = "psci";
	43	};
	44
	45	cpu@3 {
	46	device_type = "cpu";
	47	compatible = "arm,cortex-a57", "arm,armv8";
	48	reg = <0x3>;
	49	enable-method = "psci";
	50	};
	51	};
	52
	53	psci {
	54	compatible = "arm,psci-0.2";
	55	method = "smc";
	56	};
	57
	58	soc: soc {
	59	compatible = "simple-bus";
	60	#address-cells = <1>;
	61	#size-cells = <1>;
	62	ranges = <0 0 0 0x18000000>;
	63
	64	chipid@10000000 {
65	compatible = "samsung,exynos4210-chipid";
66	reg = <0x10000000 0x100>;
67	};
68
69	fin_pll: xxti {
70	compatible = "fixed-clock";
71	clock-output-names = "fin_pll";
72	#clock-cells = <0>;
73	};
74
75	gic: interrupt-controller@11001000 {
76	compatible = "arm,gic-400";
77	#interrupt-cells = <3>;
78	#address-cells = <0>;
79	interrupt-controller;
80	reg = <0x11001000 0x1000>,
81	<0x11002000 0x1000>,
82	<0x11004000 0x2000>,
83	<0x11006000 0x2000>;
84	};
85
86	clock_topc: clock-controller@10570000 {
87	compatible = "samsung,exynos7-clock-topc";
88	reg = <0x10570000 0x10000>;
89	#clock-cells = <1>;
90	};
91
92	clock_top0: clock-controller@105d0000 {
93	compatible = "samsung,exynos7-clock-top0";
94	reg = <0x105d0000 0xb000>;
95	#clock-cells = <1>;
96	clocks = <&fin_pll>, <&clock_topc DOUT_SCLK_BUS0_PLL>,
97	<&clock_topc DOUT_SCLK_BUS1_PLL>,
98	<&clock_topc DOUT_SCLK_CC_PLL>,
99	<&clock_topc DOUT_SCLK_MFC_PLL>;
100	clock-names = "fin_pll", "dout_sclk_bus0_pll",
101	"dout_sclk_bus1_pll", "dout_sclk_cc_pll",
102	"dout_sclk_mfc_pll";
103	};
104
105	clock_peric0: clock-controller@13610000 {
106	compatible = "samsung,exynos7-clock-peric0";
107	reg = <0x13610000 0xd00>;
108	#clock-cells = <1>;
109	clocks = <&fin_pll>, <&clock_top0 DOUT_ACLK_PERIC0>,
110	<&clock_top0 CLK_SCLK_UART0>;
111	clock-names = "fin_pll", "dout_aclk_peric0_66",
112	"sclk_uart0";
113	};
114
115	clock_peric1: clock-controller@14c80000 {
116	compatible = "samsung,exynos7-clock-peric1";
117	reg = <0x14c80000 0xd00>;
118	#clock-cells = <1>;
119	clocks = <&fin_pll>, <&clock_top0 DOUT_ACLK_PERIC1>,
120	<&clock_top0 CLK_SCLK_UART1>,
121	<&clock_top0 CLK_SCLK_UART2>,
122	<&clock_top0 CLK_SCLK_UART3>;
123	clock-names = "fin_pll", "dout_aclk_peric1_66",
124	"sclk_uart1", "sclk_uart2", "sclk_uart3";
125	};
126
127	clock_peris: clock-controller@10040000 {
128	compatible = "samsung,exynos7-clock-peris";
129	reg = <0x10040000 0xd00>;
130	#clock-cells = <1>;
131	clocks = <&fin_pll>, <&clock_topc DOUT_ACLK_PERIS>;
132	clock-names = "fin_pll", "dout_aclk_peris_66";
133	};
134
135	serial_0: serial@13630000 {
136	compatible = "samsung,exynos4210-uart";
137	reg = <0x13630000 0x100>;
138	interrupts = <0 440 0>;
139	clocks = <&clock_peric0 PCLK_UART0>,
140	<&clock_peric0 SCLK_UART0>;
141	clock-names = "uart", "clk_uart_baud0";
142	status = "disabled";
143	};
144
145	serial_1: serial@14c20000 {
146	compatible = "samsung,exynos4210-uart";
147	reg = <0x14c20000 0x100>;
148	interrupts = <0 456 0>;
149	clocks = <&clock_peric1 PCLK_UART1>,
150	<&clock_peric1 SCLK_UART1>;
151	clock-names = "uart", "clk_uart_baud0";
152	status = "disabled";
153	};
154
155	serial_2: serial@14c30000 {
156	compatible = "samsung,exynos4210-uart";
157	reg = <0x14c30000 0x100>;
158	interrupts = <0 457 0>;
159	clocks = <&clock_peric1 PCLK_UART2>,
160	<&clock_peric1 SCLK_UART2>;
161	clock-names = "uart", "clk_uart_baud0";
162	status = "disabled";
163	};
164
165	serial_3: serial@14c40000 {
166	compatible = "samsung,exynos4210-uart";
167	reg = <0x14c40000 0x100>;
168	interrupts = <0 458 0>;
169	clocks = <&clock_peric1 PCLK_UART3>,
170	<&clock_peric1 SCLK_UART3>;
171	clock-names = "uart", "clk_uart_baud0";
172	status = "disabled";
173	};
174
175	timer {
176	compatible = "arm,armv8-timer";
177	interrupts = <1 13 0xff01>,
178	<1 14 0xff01>,
179	<1 11 0xff01>,
180	<1 10 0xff01>;
181	};
182	};
183	};